From: Chanwoo Choi <cw00.choi@samsung.com>
To: kgene@kernel.org
Cc: mark.rutland@arm.com, marc.zyngier@arm.com, arnd@arndb.de,
olof@lixom.net, catalin.marinas@arm.com, will.deacon@arm.com,
inki.dae@samsung.com, chanho61.park@samsung.com,
cw00.choi@samsung.com, jaewon02.kim@samsung.com,
beomho.seo@samsung.com, jy0922.shim@samsung.com,
a.kesavan@samsung.com, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH 3/6] arm64: dts: exynos: Add USB3.0 Host dt node for Exynos5433
Date: Thu, 02 Apr 2015 17:34:34 +0900 [thread overview]
Message-ID: <1427963677-32661-4-git-send-email-cw00.choi@samsung.com> (raw)
In-Reply-To: <1427963677-32661-1-git-send-email-cw00.choi@samsung.com>
From: Jaewon Kim <jaewon02.kim@samsung.com>
This patch adds PHY and USB3.0 Host device tree node
using DWC3 chip and set USB3.0 Host related clock parent
for Exynos5433.
Cc: Kukjin Kim <kgene@kernel.org>
Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
---
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 46 ++++++++++++++++++++++++++++++
1 file changed, 46 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index b460f5f..9cca236 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -1006,6 +1006,52 @@
samsung,pmu-syscon = <&pmu_system_controller>;
status = "disabled";
};
+
+ usbhost30_phy: phy@15580000 {
+ compatible = "samsung,exynos5433-usbdrd-phy";
+ reg = <0x15580000 0x100>;
+ clocks = <&cmu_fsys CLK_ACLK_USBHOST30>, <&xxti>,
+ <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK>,
+ <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK>,
+ <&cmu_fsys CLK_SCLK_USBHOST30>;
+ clock-names = "phy", "ref", "phy_utmi", "phy_pipe", "itp";
+ assigned-clocks =
+ <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER>,
+ <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER>;
+ assigned-clock-parents =
+ <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY>,
+ <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY>;
+ #phy-cells = <1>;
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ status = "disabled";
+ };
+
+ usbhost30: usb@15a00000 {
+ compatible = "samsung,exynos5250-dwusb3";
+ clocks = <&cmu_fsys CLK_ACLK_USBHOST30>,
+ <&cmu_fsys CLK_SCLK_USBHOST30>;
+ clock-names = "usbdrd30", "usbdrd30_susp_clk";
+ assigned-clocks =
+ <&cmu_fsys CLK_MOUT_SCLK_USBHOST30_USER>,
+ <&cmu_top CLK_MOUT_SCLK_USBHOST30>,
+ <&cmu_top CLK_DIV_SCLK_USBHOST30>;
+ assigned-clock-parents =
+ <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
+ <&cmu_top CLK_MOUT_BUS_PLL_USER>;
+ assigned-clock-rates = <0>, <0>, <66700000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ status = "disabled";
+
+ dwc3 {
+ compatible = "snps,dwc3";
+ reg = <0x154a0000 0x10000>;
+ interrupts = <0 244 0>;
+ phys = <&usbhost30_phy 0>, <&usbhost30_phy 1>;
+ phy-names = "usb2-phy", "usb3-phy";
+ };
+ };
};
timer {
--
1.8.5.5
next prev parent reply other threads:[~2015-04-02 8:36 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-04-02 8:34 [PATCH 0/6] arm64: dts: exynos: Add USB/PWM/UART3/reboot dt node for Exynos5433 SoC Chanwoo Choi
2015-04-02 8:34 ` [PATCH 1/6] arm64: dts: exynos: Add EHCI and OHCI dt node for Exynos5433 Chanwoo Choi
2015-04-02 8:34 ` [PATCH 2/6] arm64: dts: exynos: Add USB Device " Chanwoo Choi
2015-04-02 8:34 ` Chanwoo Choi [this message]
2015-04-02 8:34 ` [PATCH 4/6] arm64: dts: exynos: Add PWM dt node and pinctrl for Exynos5433 SoC Chanwoo Choi
2015-04-02 8:34 ` [PATCH 5/6] arm64: dts: exynos: Add UART3 dt node " Chanwoo Choi
2015-04-02 8:34 ` [PATCH 6/6] arm64: dts: exynos: add reboot node for exynos5433 Chanwoo Choi
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