From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753459AbbDCAa6 (ORCPT ); Thu, 2 Apr 2015 20:30:58 -0400 Received: from mailout2.samsung.com ([203.254.224.25]:20373 "EHLO mailout2.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753083AbbDCA3f (ORCPT ); Thu, 2 Apr 2015 20:29:35 -0400 X-AuditID: cbfee691-f79b86d000004a5a-4a-551dded94251 From: Chanwoo Choi To: s.nawrocki@samsung.com, tomasz.figa@gmail.com, mturquette@linaro.org Cc: kgene@kernel.org, inki.dae@samsung.com, chanho61.park@samsung.com, cw00.choi@samsung.com, jonghwa3.lee@samsung.com, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 6/6] clk: samsung: exynos5433: Add CLK_SET_RATE_PARENT to support DVFS for big.LITTLE core Date: Fri, 03 Apr 2015 09:29:11 +0900 Message-id: <1428020951-30428-7-git-send-email-cw00.choi@samsung.com> X-Mailer: git-send-email 1.8.5.5 In-reply-to: <1428020951-30428-1-git-send-email-cw00.choi@samsung.com> References: <1428020951-30428-1-git-send-email-cw00.choi@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrALMWRmVeSWpSXmKPExsWyRsSkRPfWPdlQg87PbBaX92tbXP/ynNVi /pFzrBaT7k9gseg8+4TZov/xa2aLy7vmsFnMOL+PyeLphItsFofftLNarNr1h9GB22PnrLvs HptWdbJ53Lm2h82jb8sqRo/Pm+QCWKO4bFJSczLLUov07RK4Mm51TWUtOKpccerkU7YGxg65 LkZODgkBE4kdq14wQ9hiEhfurWfrYuTiEBJYyihx/fILdpiiCa+PMkIkpjNKrL3TxQzhfGGU WLpnPVg7m4CWxP4XN9hAbBEBD4nTz26ygBQxC9xklGh6vJoFJCEskC/xYfp1VhCbRUBV4uTa Z4wgNq+Aq8SUyx9YINYpSCxbPhOshlPATaLl6xywuBBQTd/Mv+wgQyUEdrFLLJj1lQVikIDE t8mHgGwOoISsxKYDUP9IShxccYNlAqPwAkaGVYyiqQXJBcVJ6UWmesWJucWleel6yfm5mxiB EXH637OJOxjvH7A+xCjAwajEw5uxRyZUiDWxrLgy9xCjKdCGicxSosn5wLjLK4k3NDYzsjA1 MTU2Mrc0UxLn1ZH+GSwkkJ5YkpqdmlqQWhRfVJqTWnyIkYmDU6qB8ejtXV+XllaqbG9vjYtM tS0se2jWH5h4j/8rQ6yR7qW/K98V6wnsdWF9VbDBv1u95PTpvTs0JirdEOX2OL3WlVl6n4RC 5YNTPyY5navXmsH/Z9ni8vrdwRovIi7nNR/g+ObosfCHQ/HNp1OUTBQtOhJa8tv3XFuZMXVy ZrDfuZ7Qv8e/xdVpK7EUZyQaajEXFScCAKSBY/WDAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrFIsWRmVeSWpSXmKPExsVy+t9jQd2b92RDDRr7rS0u79e2uP7lOavF /CPnWC0m3Z/AYtF59gmzRf/j18wWl3fNYbOYcX4fk8XTCRfZLA6/aWe1WLXrD6MDt8fOWXfZ PTat6mTzuHNtD5tH35ZVjB6fN8kFsEY1MNpkpCampBYppOYl56dk5qXbKnkHxzvHm5oZGOoa WlqYKynkJeam2iq5+AToumXmAJ2mpFCWmFMKFApILC5W0rfDNCE0xE3XAqYxQtc3JAiux8gA DSSsYcy41TWVteCocsWpk0/ZGhg75LoYOTkkBEwkJrw+yghhi0lcuLeerYuRi0NIYDqjxNo7 XcwQzhdGiaV71jODVLEJaEnsf3GDDcQWEfCQOP3sJgtIEbPATUaJpserWUASwgL5Eh+mX2cF sVkEVCVOrn0GtoJXwFViyuUPLBDrFCSWLZ8JVsMp4CbR8nUOWFwIqKZv5l/2CYy8CxgZVjGK phYkFxQnpeca6RUn5haX5qXrJefnbmIEx9sz6R2MqxosDjEKcDAq8fBm7JEJFWJNLCuuzD3E KMHBrCTCu2K3bKgQb0piZVVqUX58UWlOavEhRlOgqyYyS4km5wNTQV5JvKGxiZmRpZG5oYWR sbmSOK+SfVuIkEB6YklqdmpqQWoRTB8TB6dUA2Or+6erL8xkNqY/MTgcKdF4YV/V1lPT1lmF bz68MvmqcVnyNOlUz4fHUnrOpJvcsM7IXX3XMH3q3Esel27Kix5IcV23W+iA/MZF6hNlmw5L WEXIrdg9VdE+2GXN/IgiXebZVgqTjyo+cLgacfJUdsKU3M8Pz9w6dMw9vmH9g9vb96c4G8fv OfxZiaU4I9FQi7moOBEAe+vPss0CAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds CLK_SET_RATE_PARENT flag to support DVFS of Cortex-{A53|A57} core (big.LITTLE core) because 'sclk_{apollo|atlas}' leaf clock is used to change the CPU frequency of Cortex-{A53|A57} core in arm_big_little.c driver. - 'apollo' word means the LITTLE core (Cortex-A53 core) in Exynos5433 TRM. - 'atlas' word means the big core (Cortex-A57 core) in Exynos5433 TRM. Cc: Sylwester Nawrocki Cc: Tomasz Figa Signed-off-by: Chanwoo Choi --- drivers/clk/samsung/clk-exynos5433.c | 26 ++++++++++++-------------- 1 file changed, 12 insertions(+), 14 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c index 44f3dd5..0e6dce8 100644 --- a/drivers/clk/samsung/clk-exynos5433.c +++ b/drivers/clk/samsung/clk-exynos5433.c @@ -3582,7 +3582,7 @@ static struct samsung_pll_clock apollo_pll_clks[] __initdata = { static struct samsung_mux_clock apollo_mux_clks[] __initdata = { /* MUX_SEL_APOLLO0 */ MUX_F(CLK_MOUT_APOLLO_PLL, "mout_apollo_pll", mout_apollo_pll_p, - MUX_SEL_APOLLO0, 0, 1, 0, CLK_MUX_READ_ONLY), + MUX_SEL_APOLLO0, 0, 1, CLK_SET_RATE_PARENT, 0), /* MUX_SEL_APOLLO1 */ MUX(CLK_MOUT_BUS_PLL_APOLLO_USER, "mout_bus_pll_apollo_user", @@ -3590,7 +3590,7 @@ static struct samsung_mux_clock apollo_mux_clks[] __initdata = { /* MUX_SEL_APOLLO2 */ MUX_F(CLK_MOUT_APOLLO, "mout_apollo", mout_apollo_p, MUX_SEL_APOLLO2, - 0, 1, 0, CLK_MUX_READ_ONLY), + 0, 1, CLK_SET_RATE_PARENT, 0), }; static struct samsung_div_clock apollo_div_clks[] __initdata = { @@ -3611,11 +3611,9 @@ static struct samsung_div_clock apollo_div_clks[] __initdata = { DIV_APOLLO0, 8, 3, CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), DIV_F(CLK_DIV_APOLLO2, "div_apollo2", "div_apollo1", - DIV_APOLLO0, 4, 3, CLK_GET_RATE_NOCACHE, - CLK_DIVIDER_READ_ONLY), + DIV_APOLLO0, 4, 3, CLK_SET_RATE_PARENT, 0), DIV_F(CLK_DIV_APOLLO1, "div_apollo1", "mout_apollo", - DIV_APOLLO0, 0, 3, CLK_GET_RATE_NOCACHE, - CLK_DIVIDER_READ_ONLY), + DIV_APOLLO0, 0, 3, CLK_SET_RATE_PARENT, 0), /* DIV_APOLLO1 */ DIV_F(CLK_DIV_SCLK_HPM_APOLLO, "div_sclk_hpm_apollo", "mout_apollo", @@ -3666,7 +3664,8 @@ static struct samsung_gate_clock apollo_gate_clks[] __initdata = { GATE(CLK_SCLK_HPM_APOLLO, "sclk_hpm_apollo", "div_sclk_hpm_apollo", ENABLE_SCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0), GATE(CLK_SCLK_APOLLO, "sclk_apollo", "div_apollo2", - ENABLE_SCLK_APOLLO, 0, CLK_IGNORE_UNUSED, 0), + ENABLE_SCLK_APOLLO, 0, + CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), }; static struct samsung_cmu_info apollo_cmu_info __initdata = { @@ -3775,7 +3774,7 @@ static struct samsung_pll_clock atlas_pll_clks[] __initdata = { static struct samsung_mux_clock atlas_mux_clks[] __initdata = { /* MUX_SEL_ATLAS0 */ MUX_F(CLK_MOUT_ATLAS_PLL, "mout_atlas_pll", mout_atlas_pll_p, - MUX_SEL_ATLAS0, 0, 1, 0, CLK_MUX_READ_ONLY), + MUX_SEL_ATLAS0, 0, 1, CLK_SET_RATE_PARENT, 0), /* MUX_SEL_ATLAS1 */ MUX(CLK_MOUT_BUS_PLL_ATLAS_USER, "mout_bus_pll_atlas_user", @@ -3783,7 +3782,7 @@ static struct samsung_mux_clock atlas_mux_clks[] __initdata = { /* MUX_SEL_ATLAS2 */ MUX_F(CLK_MOUT_ATLAS, "mout_atlas", mout_atlas_p, MUX_SEL_ATLAS2, - 0, 1, 0, CLK_MUX_READ_ONLY), + 0, 1, CLK_SET_RATE_PARENT, 0), }; static struct samsung_div_clock atlas_div_clks[] __initdata = { @@ -3804,11 +3803,9 @@ static struct samsung_div_clock atlas_div_clks[] __initdata = { DIV_ATLAS0, 8, 3, CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), DIV_F(CLK_DIV_ATLAS2, "div_atlas2", "div_atlas1", - DIV_ATLAS0, 4, 3, CLK_GET_RATE_NOCACHE, - CLK_DIVIDER_READ_ONLY), + DIV_ATLAS0, 4, 3, CLK_SET_RATE_PARENT, 0), DIV_F(CLK_DIV_ATLAS1, "div_atlas1", "mout_atlas", - DIV_ATLAS0, 0, 3, CLK_GET_RATE_NOCACHE, - CLK_DIVIDER_READ_ONLY), + DIV_ATLAS0, 0, 3, CLK_SET_RATE_PARENT, 0), /* DIV_ATLAS1 */ DIV_F(CLK_DIV_SCLK_HPM_ATLAS, "div_sclk_hpm_atlas", "mout_atlas", @@ -3885,7 +3882,8 @@ static struct samsung_gate_clock atlas_gate_clks[] __initdata = { GATE(CLK_ATCLK, "atclk", "div_atclk_atlas", ENABLE_SCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0), GATE(CLK_SCLK_ATLAS, "sclk_atlas", "div_atlas2", - ENABLE_SCLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0), + ENABLE_SCLK_ATLAS, 0, + CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), }; static struct samsung_cmu_info atlas_cmu_info __initdata = { -- 1.8.5.5