From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752657AbbDCEq2 (ORCPT ); Fri, 3 Apr 2015 00:46:28 -0400 Received: from mail-bn1bon0098.outbound.protection.outlook.com ([157.56.111.98]:60192 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752562AbbDCEqW (ORCPT ); Fri, 3 Apr 2015 00:46:22 -0400 Authentication-Results: spf=fail (sender IP is 66.35.236.236) smtp.mailfrom=opensource.altera.com; codeaurora.org; dkim=none (message not signed) header.d=none; From: To: , CC: , , , , , , , , , Dinh Nguyen Subject: [PATCH 1/3] clk: socfpga: update clk.h so for Arria10 platform to use Date: Thu, 2 Apr 2015 23:40:53 -0500 Message-ID: <1428036055-27607-2-git-send-email-dinguyen@opensource.altera.com> X-Mailer: git-send-email 2.2.1 In-Reply-To: <1428036055-27607-1-git-send-email-dinguyen@opensource.altera.com> References: <1428036055-27607-1-git-send-email-dinguyen@opensource.altera.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [64.129.157.38] X-ClientProxiedBy: BLUPR08CA0061.namprd08.prod.outlook.com (10.141.200.41) To BY1PR03MB1370.namprd03.prod.outlook.com (25.162.109.28) Authentication-Results: codeaurora.org; dkim=none (message not signed) header.d=none; X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BY1PR03MB1370;UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BLUPR03MB019; X-Forefront-Antispam-Report-Untrusted: BMV:1;SFV:NSPM;SFS:(10009020)(6009001)(229853001)(86152002)(62966003)(86362001)(42186005)(53416004)(2950100001)(92566002)(40100003)(33646002)(47776003)(50226001)(77156002)(122386002)(50986999)(46102003)(50466002)(19580395003)(66066001)(19580405001)(87976001)(76176999)(48376002);DIR:OUT;SFP:1101;SCL:1;SRVR:BY1PR03MB1370;H:linux-builds1.altera.com;FPR:;SPF:None;MLV:sfv;LANG:en; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:;UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(601004)(5002010)(5005006);SRVR:BY1PR03MB1370;BCL:0;PCL:0;RULEID:;SRVR:BY1PR03MB1370;BCL:0;PCL:0;RULEID:(601004)(5005006)(5002010);SRVR:BLUPR03MB019;BCL:0;PCL:0;RULEID:;SRVR:BLUPR03MB019; X-Forefront-PRVS: 05352A48BE X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY1PR03MB1370 X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: BY2FFO11OLC010.protection.gbl X-Forefront-Antispam-Report: CIP:66.35.236.236;CTRY:US;IPV:NLI;EFV:NLI;BMV:1;SFV:NSPM;SFS:(10009020)(6009001)(339900001)(199003)(189002)(48376002)(76176999)(47776003)(92566002)(50986999)(50226001)(50466002)(62966003)(77156002)(53416004)(2950100001)(19580405001)(64706001)(66066001)(6806004)(86362001)(122386002)(229853001)(16796002)(40100003)(33646002)(87936001)(86152002)(19580395003)(85426001)(46102003)(106466001)(105606002)(7099025);DIR:OUT;SFP:1101;SCL:1;SRVR:BLUPR03MB019;H:sj-itexedge04.altera.priv.altera.com;FPR:;SPF:Fail;MLV:ovrnspm;A:0;MX:1;PTR:InfoDomainNonexistent;LANG:en; X-Forefront-PRVS: 05352A48BE X-OriginatorOrg: opensource.altera.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Apr 2015 04:46:18.3471 (UTC) X-MS-Exchange-CrossTenant-Id: fbd72e03-d4a5-4110-adce-614d51f2077a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=fbd72e03-d4a5-4110-adce-614d51f2077a;Ip=[66.35.236.236];Helo=[sj-itexedge04.altera.priv.altera.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLUPR03MB019 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Dinh Nguyen There are 5 possible parent clocks for the SoCFPGA Arria10. Move the define SYSMGR_SDMMC_CTRL_SET and streq() to clk.h so that the Arria clock driver can use. Signed-off-by: Dinh Nguyen --- drivers/clk/socfpga/clk-gate.c | 4 ---- drivers/clk/socfpga/clk.h | 6 +++++- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c index dd3a78c..607ab35 100644 --- a/drivers/clk/socfpga/clk-gate.c +++ b/drivers/clk/socfpga/clk-gate.c @@ -32,14 +32,10 @@ #define SOCFPGA_MMC_CLK "sdmmc_clk" #define SOCFPGA_GPIO_DB_CLK_OFFSET 0xA8 -#define streq(a, b) (strcmp((a), (b)) == 0) - #define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw) /* SDMMC Group for System Manager defines */ #define SYSMGR_SDMMCGRP_CTRL_OFFSET 0x108 -#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \ - ((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0)) static u8 socfpga_clk_get_parent(struct clk_hw *hwclk) { diff --git a/drivers/clk/socfpga/clk.h b/drivers/clk/socfpga/clk.h index d291f60..b09a5d5 100644 --- a/drivers/clk/socfpga/clk.h +++ b/drivers/clk/socfpga/clk.h @@ -26,9 +26,13 @@ #define CLKMGR_L4SRC 0x70 #define CLKMGR_PERPLL_SRC 0xAC -#define SOCFPGA_MAX_PARENTS 3 +#define SOCFPGA_MAX_PARENTS 5 #define div_mask(width) ((1 << (width)) - 1) +#define streq(a, b) (strcmp((a), (b)) == 0) +#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \ + ((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0)) + extern void __iomem *clk_mgr_base_addr; void __init socfpga_pll_init(struct device_node *node); -- 2.2.1