From: Zhen Lei <thunder.leizhen@huawei.com>
To: Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>,
Marc Zyngier <marc.zyngier@arm.com>,
linux-kernel <linux-kernel@vger.kernel.org>
Cc: Zefan Li <lizefan@huawei.com>, Xinwei Hu <huxinwei@huawei.com>,
"Tianhong Ding" <dingtianhong@huawei.com>,
Kefeng Wang <wangkefeng.wang@huawei.com>,
"Yun Wu" <wuyun.wu@huawei.com>,
Zhen Lei <thunder.leizhen@huawei.com>
Subject: [PATCH 2/3] irqchip/gicv3-its: remove GITS_BASER_TYPE_CPU base on latest spec
Date: Tue, 7 Apr 2015 15:47:33 +0800 [thread overview]
Message-ID: <1428392854-3228-2-git-send-email-thunder.leizhen@huawei.com> (raw)
In-Reply-To: <1428392854-3228-1-git-send-email-thunder.leizhen@huawei.com>
In the latest specification(version 24.0), clause 5.12.13 GITS_BASERn.
The meaning of value=0x3 in "Type" field was revised to reserved. As
below:
0x3. Reserved.
In the early versions(like 19.0), it defined as below:
0x3. Physical Processors.
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
---
drivers/irqchip/irq-gic-v3-its.c | 2 +-
include/linux/irqchip/arm-gic-v3.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index 2577f06..bbf9504 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -777,7 +777,7 @@ static int __init its_alloc_lpi_tables(void)
static const char *its_base_type_string[] = {
[GITS_BASER_TYPE_DEVICE] = "Devices",
[GITS_BASER_TYPE_VCPU] = "Virtual CPUs",
- [GITS_BASER_TYPE_CPU] = "Physical CPUs",
+ [GITS_BASER_TYPE_RESERVED3] = "Reserved (3)",
[GITS_BASER_TYPE_COLLECTION] = "Interrupt Collections",
[GITS_BASER_TYPE_RESERVED5] = "Reserved (5)",
[GITS_BASER_TYPE_RESERVED6] = "Reserved (6)",
diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
index ffbc034..67f5779 100644
--- a/include/linux/irqchip/arm-gic-v3.h
+++ b/include/linux/irqchip/arm-gic-v3.h
@@ -233,7 +233,7 @@
#define GITS_BASER_TYPE_NONE 0
#define GITS_BASER_TYPE_DEVICE 1
#define GITS_BASER_TYPE_VCPU 2
-#define GITS_BASER_TYPE_CPU 3
+#define GITS_BASER_TYPE_RESERVED3 3
#define GITS_BASER_TYPE_COLLECTION 4
#define GITS_BASER_TYPE_RESERVED5 5
#define GITS_BASER_TYPE_RESERVED6 6
--
1.8.0
next prev parent reply other threads:[~2015-04-07 7:48 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-04-07 7:47 [PATCH 1/3] irqchip/gicv3-its: Adjust the implementation of its_alloc_tables Zhen Lei
2015-04-07 7:47 ` Zhen Lei [this message]
2015-04-07 7:47 ` [PATCH 3/3] irqchip/gicv3-its: treat type reserved as 0x0 Zhen Lei
2015-04-07 9:33 ` [PATCH 1/3] irqchip/gicv3-its: Adjust the implementation of its_alloc_tables Marc Zyngier
2015-04-07 12:32 ` leizhen
2015-04-07 13:02 ` Marc Zyngier
2015-04-07 14:54 ` leizhen
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