From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754198AbbFDSzR (ORCPT ); Thu, 4 Jun 2015 14:55:17 -0400 Received: from albert.telenet-ops.be ([195.130.137.90]:57307 "EHLO albert.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754033AbbFDSxr (ORCPT ); Thu, 4 Jun 2015 14:53:47 -0400 From: Geert Uytterhoeven To: Simon Horman , Magnus Damm , "Rafael J. Wysocki" , Kevin Hilman , Ulf Hansson , Lina Iyer , Mark Rutland , Pawel Moll Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-sh@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH/RFC 10/15] ARM: shmobile: r8a7794 dtsi: Add L1 cache information to CPU nodes Date: Thu, 4 Jun 2015 20:53:36 +0200 Message-Id: <1433444021-22167-11-git-send-email-geert+renesas@glider.be> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1433444021-22167-1-git-send-email-geert+renesas@glider.be> References: <1433444021-22167-1-git-send-email-geert+renesas@glider.be> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Describe the L1 instruction and data caches in the CPU nodes: - The L1 instruction caches for the Cortex-A7 CPU cores are organized as 16 KiB x 2 ways, - The L1 data caches for the Cortex-A7 CPU cores are organized as 8 KiB x 4 ways. Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7794.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 0c3ab5febe0a88d8..0ea502a43d553e25 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -28,6 +28,16 @@ compatible = "arm,cortex-a7"; reg = <0>; clock-frequency = <1000000000>; + + i-cache-size = <0x8000>; + i-cache-sets = <512>; + i-cache-block-size = <32>; + i-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <256>; + d-cache-block-size = <32>; + d-cache-line-size = <32>; + next-level-cache = <&L2_CA7>; }; cpu1: cpu@1 { @@ -35,6 +45,16 @@ compatible = "arm,cortex-a7"; reg = <1>; clock-frequency = <1000000000>; + + i-cache-size = <0x8000>; + i-cache-sets = <512>; + i-cache-block-size = <32>; + i-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <256>; + d-cache-block-size = <32>; + d-cache-line-size = <32>; + next-level-cache = <&L2_CA7>; }; }; -- 1.9.1