From: Geert Uytterhoeven <geert+renesas@glider.be>
To: Simon Horman <horms@verge.net.au>,
Magnus Damm <magnus.damm@gmail.com>,
"Rafael J. Wysocki" <rjw@rjwysocki.net>,
Kevin Hilman <khilman@kernel.org>,
Ulf Hansson <ulf.hansson@linaro.org>,
Lina Iyer <lina.iyer@linaro.org>,
Mark Rutland <mark.rutland@arm.com>,
Pawel Moll <pawel.moll@arm.com>
Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org,
linux-sh@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
Geert Uytterhoeven <geert+renesas@glider.be>
Subject: [PATCH/RFC 08/15] ARM: shmobile: r8a7791 dtsi: Add L1 cache information to CPU nodes
Date: Thu, 4 Jun 2015 20:53:34 +0200 [thread overview]
Message-ID: <1433444021-22167-9-git-send-email-geert+renesas@glider.be> (raw)
In-Reply-To: <1433444021-22167-1-git-send-email-geert+renesas@glider.be>
Describe the L1 instruction and data caches in the CPU nodes:
- The L1 caches for the Cortex-A15 CPU cores are organized as 16 KiB x
2 ways.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm/boot/dts/r8a7791.dtsi | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 8013223448b5b464..4e4011a2978bcfce 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -52,6 +52,16 @@
clocks = <&cpg_clocks R8A7791_CLK_Z>;
clock-latency = <300000>; /* 300 us */
+ i-cache-size = <0x8000>;
+ i-cache-sets = <512>;
+ i-cache-block-size = <32>;
+ i-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <512>;
+ d-cache-block-size = <32>;
+ d-cache-line-size = <32>;
+ next-level-cache = <&L2_CA15>;
+
/* kHz - uV - OPPs unknown yet */
operating-points = <1500000 1000000>,
<1312500 1000000>,
@@ -66,6 +76,16 @@
compatible = "arm,cortex-a15";
reg = <1>;
clock-frequency = <1500000000>;
+
+ i-cache-size = <0x8000>;
+ i-cache-sets = <512>;
+ i-cache-block-size = <32>;
+ i-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <512>;
+ d-cache-block-size = <32>;
+ d-cache-line-size = <32>;
+ next-level-cache = <&L2_CA15>;
};
};
--
1.9.1
next prev parent reply other threads:[~2015-06-04 18:54 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-06-04 18:53 [PATCH/RFC 00/15] ARM: shmobile: R-Car: Add SYSC PM Domain DT Support Geert Uytterhoeven
2015-06-04 18:53 ` [PATCH/RFC 01/15] PM / Domains: Add DT bindings for the R-Car System Controller Geert Uytterhoeven
2015-06-04 18:53 ` [PATCH/RFC 02/15] ARM: shmobile: R-Car: Add DT support for PM domains Geert Uytterhoeven
2015-06-24 12:11 ` Geert Uytterhoeven
2015-06-04 18:53 ` [PATCH/RFC 03/15] ARM: shmobile: r8a7790 dtsi: Add L2 cache-controller nodes Geert Uytterhoeven
2015-06-04 18:53 ` [PATCH/RFC 04/15] ARM: shmobile: r8a7791 dtsi: Add L2 cache-controller node Geert Uytterhoeven
2015-06-04 18:53 ` [PATCH/RFC 05/15] ARM: shmobile: r8a7793 " Geert Uytterhoeven
2015-06-04 18:53 ` [PATCH/RFC 06/15] ARM: shmobile: r8a7794 " Geert Uytterhoeven
2015-06-04 18:53 ` [PATCH/RFC 07/15] ARM: shmobile: r8a7790 dtsi: Add L1 cache information to CPU nodes Geert Uytterhoeven
2015-06-04 18:53 ` Geert Uytterhoeven [this message]
2015-06-04 18:53 ` [PATCH/RFC 09/15] ARM: shmobile: r8a7793 dtsi: Add L1 cache information to CPU node Geert Uytterhoeven
2015-06-04 18:53 ` [PATCH/RFC 10/15] ARM: shmobile: r8a7794 dtsi: Add L1 cache information to CPU nodes Geert Uytterhoeven
2015-06-04 18:53 ` [PATCH/RFC 11/15] ARM: shmobile: r8a7779 dtsi: Add SYSC PM domains Geert Uytterhoeven
2015-06-04 18:53 ` [PATCH/RFC 12/15] ARM: shmobile: r8a7790 " Geert Uytterhoeven
2015-06-04 18:53 ` [PATCH/RFC 13/15] ARM: shmobile: r8a7791 " Geert Uytterhoeven
2015-06-04 18:53 ` [PATCH/RFC 14/15] ARM: shmobile: r8a7793 " Geert Uytterhoeven
2015-06-04 18:53 ` [PATCH/RFC 15/15] ARM: shmobile: r8a7794 " Geert Uytterhoeven
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