* [PATCH v2 0/5] Mediatek xHCI support
@ 2015-07-08 9:41 Chunfeng Yun
2015-07-08 9:41 ` [PATCH v2 1/5] dt-bindings: Add usb3.0 phy binding for MT65xx SoCs Chunfeng Yun
` (4 more replies)
0 siblings, 5 replies; 22+ messages in thread
From: Chunfeng Yun @ 2015-07-08 9:41 UTC (permalink / raw)
To: Mathias Nyman
Cc: Rob Herring, Mark Rutland, Matthias Brugger, Felipe Balbi,
Chunfeng Yun, Sascha Hauer, devicetree, linux-kernel,
linux-arm-kernel, Roger Quadros, linux-usb, linux-mediatek
The patch supports MediaTek's xHCI controller.
There are some differences from xHCI spec:
1. The interval is specified in 250 * 8ns increments for Interrupt Moderation
Interval(IMODI) of the Interrupter Moderation(IMOD) register, it is 8 times as
much as that defined in xHCI spec.
2. For the value of TD Size in Normal TRB, MTK's xHCI controller defines a
number of packets that remain to be transferred for a TD after processing all
Max packets in all previous TRBs,that means don't include the current TRB's,
but in xHCI spec it includes the current ones.
3. To minimize the scheduling effort for synchronous endpoints in xHC, the MTK
architecture defines some extra SW scheduling parameters for HW. According to
these parameters provided by SW, the xHC can easily decide whether a
synchronous endpoint should be scheduled in a specific uFrame. The extra SW
scheduling parameters are put into reserved DWs in Slot and Endpoint Context.
And a bandwidth scheduler algorithm is added to support such feature.
A usb3.0 phy driver is also added which used by mt65xx SoCs platform, it
supports two usb2.0 ports and one usb3.0 port.
Change in v2:
1. Rebase to 4.2-rc1
2. Remove probe phy before add usb_hcd patch from this series due to 4.2-rc1
already fix this issue
3. add xhci mac clocks
4. add suspend/resume
5. support remote wakeup
Chunfeng Yun (5):
dt-bindings: Add usb3.0 phy binding for MT65xx SoCs
dt-bindings: Add a binding for Mediatek xHCI host controller
usb: phy: add usb3.0 phy driver for mt65xx SoCs
xhci: mediatek: support MTK xHCI host controller
arm64: dts: mediatek: add xHCI & usb phy for mt8173
.../devicetree/bindings/usb/mt65xx-u3phy.txt | 34 +
.../devicetree/bindings/usb/mt8173-xhci.txt | 27 +
arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 15 +
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 27 +
drivers/usb/host/Kconfig | 9 +
drivers/usb/host/Makefile | 1 +
drivers/usb/host/xhci-mtk.c | 814 ++++++++++++++++++++
drivers/usb/host/xhci-mtk.h | 108 +++
drivers/usb/host/xhci-ring.c | 35 +-
drivers/usb/host/xhci.c | 19 +-
drivers/usb/host/xhci.h | 1 +
drivers/usb/phy/Kconfig | 10 +
drivers/usb/phy/Makefile | 1 +
drivers/usb/phy/phy-mt65xx-usb3.c | 856 +++++++++++++++++++++
14 files changed, 1950 insertions(+), 7 deletions(-)
create mode 100644 Documentation/devicetree/bindings/usb/mt65xx-u3phy.txt
create mode 100644 Documentation/devicetree/bindings/usb/mt8173-xhci.txt
create mode 100644 drivers/usb/host/xhci-mtk.c
create mode 100644 drivers/usb/host/xhci-mtk.h
create mode 100644 drivers/usb/phy/phy-mt65xx-usb3.c
--
1.8.1.1.dirty
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v2 1/5] dt-bindings: Add usb3.0 phy binding for MT65xx SoCs
2015-07-08 9:41 [PATCH v2 0/5] Mediatek xHCI support Chunfeng Yun
@ 2015-07-08 9:41 ` Chunfeng Yun
2015-07-10 5:10 ` Sascha Hauer
2015-07-08 9:41 ` [PATCH v2 2/5] dt-bindings: Add a binding for Mediatek xHCI host controller Chunfeng Yun
` (3 subsequent siblings)
4 siblings, 1 reply; 22+ messages in thread
From: Chunfeng Yun @ 2015-07-08 9:41 UTC (permalink / raw)
To: Mathias Nyman
Cc: Rob Herring, Mark Rutland, Matthias Brugger, Felipe Balbi,
Chunfeng Yun, Sascha Hauer, devicetree, linux-kernel,
linux-arm-kernel, Roger Quadros, linux-usb, linux-mediatek
add a DT binding documentation of usb3.0 phy for MT65xx
SoCs from Mediatek.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
.../devicetree/bindings/usb/mt65xx-u3phy.txt | 34 ++++++++++++++++++++++
1 file changed, 34 insertions(+)
create mode 100644 Documentation/devicetree/bindings/usb/mt65xx-u3phy.txt
diff --git a/Documentation/devicetree/bindings/usb/mt65xx-u3phy.txt b/Documentation/devicetree/bindings/usb/mt65xx-u3phy.txt
new file mode 100644
index 0000000..056b2aa
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/mt65xx-u3phy.txt
@@ -0,0 +1,34 @@
+MT65xx U3PHY
+
+The device node for Mediatek SOC usb3.0 phy
+
+Required properties:
+ - compatible : Should be "mediatek,mt8173-u3phy"
+ - reg : Offset and length of registers, the first is for mac domain,
+ another for phy domain
+ - power-domains: to enable usb's mtcmos
+ - usb-wakeup-ctrl : to access usb wakeup control register
+ - wakeup-src : 1: ip sleep wakeup mode; 2: line state wakeup mode; others
+ means don't enable wakeup source of usb
+ - u2port-num : number of usb2.0 ports to support which should be 1 or 2
+ - clocks : must support all clocks that phy need
+ - clock-names: should be "wakeup_deb_p0", "wakeup_deb_p1" for wakeup
+ debounce control clocks, and "u3phya_ref" for u3phya reference clock.
+
+Example:
+
+u3phy: usb-phy@11271000 {
+ compatible = "mediatek,mt8173-u3phy";
+ reg = <0 0x11271000 0 0x3000>,
+ <0 0x11280000 0 0x20000>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
+ usb-wakeup-ctrl = <&pericfg>;
+ wakeup-src = <1>;
+ u2port-num = <2>;
+ clocks = <&perisys PERI_USB0>,
+ <&perisys PERI_USB1>,
+ <&apmixedsys CLK_APMIXED_REF2USB_TX>;
+ clock-names = "wakeup_deb_p0",
+ "wakeup_deb_p1",
+ "u3phya_ref";
+};
--
1.8.1.1.dirty
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v2 2/5] dt-bindings: Add a binding for Mediatek xHCI host controller
2015-07-08 9:41 [PATCH v2 0/5] Mediatek xHCI support Chunfeng Yun
2015-07-08 9:41 ` [PATCH v2 1/5] dt-bindings: Add usb3.0 phy binding for MT65xx SoCs Chunfeng Yun
@ 2015-07-08 9:41 ` Chunfeng Yun
2015-07-10 8:31 ` Roger Quadros
2015-07-08 9:41 ` [PATCH v2 3/5] usb: phy: add usb3.0 phy driver for mt65xx SoCs Chunfeng Yun
` (2 subsequent siblings)
4 siblings, 1 reply; 22+ messages in thread
From: Chunfeng Yun @ 2015-07-08 9:41 UTC (permalink / raw)
To: Mathias Nyman
Cc: Rob Herring, Mark Rutland, Matthias Brugger, Felipe Balbi,
Chunfeng Yun, Sascha Hauer, devicetree, linux-kernel,
linux-arm-kernel, Roger Quadros, linux-usb, linux-mediatek
add a DT binding documentation of xHCI host controller for the
MT8173 SoC from Mediatek.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
.../devicetree/bindings/usb/mt8173-xhci.txt | 27 ++++++++++++++++++++++
1 file changed, 27 insertions(+)
create mode 100644 Documentation/devicetree/bindings/usb/mt8173-xhci.txt
diff --git a/Documentation/devicetree/bindings/usb/mt8173-xhci.txt b/Documentation/devicetree/bindings/usb/mt8173-xhci.txt
new file mode 100644
index 0000000..94cec94
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/mt8173-xhci.txt
@@ -0,0 +1,27 @@
+MT65XX xhci
+
+The device node for Mediatek SOC usb3.0 host controller
+
+Required properties:
+ - compatible : supports "mediatek,mt8173-xhci"
+ - reg : Offset and length of registers
+ - interrupts : Interrupt mode, number and trigger mode
+ - reg-vusb33-supply: regulator of usb avdd3.3v
+ - reg-vbus-supply : regulator of vbus;
+ - usb-phy : the phy that xhci will bind
+ - usb3-lpm-capable: supports USB3 LPM
+ - clocks : must support all clocks that xhci needs
+ - clock-names: should be "sys_mac" for sys and mac clocks
+
+Example:
+usb: usb30@11270000 {
+ compatible = "mediatek,mt8173-xhci";
+ reg = <0 0x11270000 0 0x1000>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
+ reg-vusb33-supply = <&mt6397_vusb_reg>;
+ reg-vbus-supply = <&usb_p1_vbus>;
+ usb-phy = <&u3phy>;
+ usb3-lpm-capable;
+ clocks = <&topckgen CLK_TOP_USB30_SEL>;
+ clock-names = "sys_mac";
+};
--
1.8.1.1.dirty
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v2 3/5] usb: phy: add usb3.0 phy driver for mt65xx SoCs
2015-07-08 9:41 [PATCH v2 0/5] Mediatek xHCI support Chunfeng Yun
2015-07-08 9:41 ` [PATCH v2 1/5] dt-bindings: Add usb3.0 phy binding for MT65xx SoCs Chunfeng Yun
2015-07-08 9:41 ` [PATCH v2 2/5] dt-bindings: Add a binding for Mediatek xHCI host controller Chunfeng Yun
@ 2015-07-08 9:41 ` Chunfeng Yun
2015-07-10 6:42 ` Sascha Hauer
2015-07-08 9:41 ` [PATCH v2 4/5] xhci: mediatek: support MTK xHCI host controller Chunfeng Yun
2015-07-08 9:41 ` [PATCH v2 5/5] arm64: dts: mediatek: add xHCI & usb phy for mt8173 Chunfeng Yun
4 siblings, 1 reply; 22+ messages in thread
From: Chunfeng Yun @ 2015-07-08 9:41 UTC (permalink / raw)
To: Mathias Nyman
Cc: Rob Herring, Mark Rutland, Matthias Brugger, Felipe Balbi,
Chunfeng Yun, Sascha Hauer, devicetree, linux-kernel,
linux-arm-kernel, Roger Quadros, linux-usb, linux-mediatek
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
drivers/usb/phy/Kconfig | 10 +
drivers/usb/phy/Makefile | 1 +
drivers/usb/phy/phy-mt65xx-usb3.c | 856 ++++++++++++++++++++++++++++++++++++++
3 files changed, 867 insertions(+)
create mode 100644 drivers/usb/phy/phy-mt65xx-usb3.c
diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
index 869c0cfcad..66ded00 100644
--- a/drivers/usb/phy/Kconfig
+++ b/drivers/usb/phy/Kconfig
@@ -152,6 +152,16 @@ config USB_MSM_OTG
This driver is not supported on boards like trout which
has an external PHY.
+config USB_MT65XX_USB3_PHY
+ tristate "Mediatek USB3.0 PHY controller Driver"
+ depends on ARCH_MEDIATEK || COMPILE_TEST
+ select USB_PHY
+ help
+ Say 'Y' here to add support for Mediatek USB3.0 PHY driver
+ for mt65xx SoCs. it supports two usb2.0 ports and
+ one usb3.0 port.
+ To compile this driver as a module, choose M here
+
config USB_MV_OTG
tristate "Marvell USB OTG support"
depends on USB_EHCI_MV && USB_MV_UDC && PM
diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
index e36ab1d..414ef57 100644
--- a/drivers/usb/phy/Makefile
+++ b/drivers/usb/phy/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_USB_EHCI_TEGRA) += phy-tegra-usb.o
obj-$(CONFIG_USB_GPIO_VBUS) += phy-gpio-vbus-usb.o
obj-$(CONFIG_USB_ISP1301) += phy-isp1301.o
obj-$(CONFIG_USB_MSM_OTG) += phy-msm-usb.o
+obj-$(CONFIG_USB_MT65XX_USB3_PHY) += phy-mt65xx-usb3.o
obj-$(CONFIG_USB_MV_OTG) += phy-mv-usb.o
obj-$(CONFIG_USB_MXS_PHY) += phy-mxs-usb.o
obj-$(CONFIG_USB_RCAR_PHY) += phy-rcar-usb.o
diff --git a/drivers/usb/phy/phy-mt65xx-usb3.c b/drivers/usb/phy/phy-mt65xx-usb3.c
new file mode 100644
index 0000000..38ee6f3
--- /dev/null
+++ b/drivers/usb/phy/phy-mt65xx-usb3.c
@@ -0,0 +1,856 @@
+/*
+ * Copyright (c) 2015 MediaTek Inc.
+ * Author: Chunfeng.Yun <chunfeng.yun@mediatek.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/export.h>
+#include <linux/gpio.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/of_gpio.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+#include <linux/regulator/consumer.h>
+#include <linux/resource.h>
+#include <linux/slab.h>
+#include <linux/usb/of.h>
+#include <linux/usb/otg.h>
+#include <linux/usb/phy.h>
+
+/*
+ * relative to MAC base address
+ */
+#define SSUSB_USB3_MAC_CSR_BASE (0x1400)
+#define SSUSB_USB3_SYS_CSR_BASE (0x1400)
+#define SSUSB_USB2_CSR_BASE (0x2400)
+
+/*
+ * for sifslv1 register
+ * relative to USB3_SIF_BASE base address
+ */
+#define SSUSB_SIFSLV_IPPC_BASE (0x700)
+
+/*
+ * for sifslv2 register
+ * relative to USB3_SIF_BASE base address
+ */
+#define SSUSB_SIFSLV_U2PHY_COM_BASE (0x10800)
+#define SSUSB_SIFSLV_U3PHYD_BASE (0x10900)
+#define SSUSB_SIFSLV_U2FREQ_BASE (0x10f00)
+#define SSUSB_USB30_PHYA_SIV_B_BASE (0x10b00)
+#define SSUSB_SIFSLV_U3PHYA_DA_BASE (0x10c00)
+#define SSUSB_SIFSLV_SPLLC (0x10000)
+
+/*port1 refs. +0x800(refer to port0)*/
+#define U3P_PORT_OFFSET (0x800) /*based on port0 */
+#define U3P_PHY_BASE(index) ((U3P_PORT_OFFSET) * (index))
+
+#define U3P_IP_PW_CTRL0 (SSUSB_SIFSLV_IPPC_BASE + 0x0000)
+#define CTRL0_IP_SW_RST (0x1 << 0)
+
+#define U3P_IP_PW_CTRL1 (SSUSB_SIFSLV_IPPC_BASE + 0x0004)
+#define CTRL1_IP_HOST_PDN (0x1 << 0)
+
+#define U3P_IP_PW_CTRL2 (SSUSB_SIFSLV_IPPC_BASE + 0x0008)
+#define CTRL2_IP_DEV_PDN (0x1 << 0)
+
+#define U3P_IP_PW_STS1 (SSUSB_SIFSLV_IPPC_BASE + 0x0010)
+#define STS1_IP_SLEEP_STS (0x1 << 30)
+#define STS1_U3_MAC_RST (0x1 << 16)
+#define STS1_SYS125_RST (0x1 << 10)
+#define STS1_REF_RST (0x1 << 8)
+#define STS1_SYSPLL_STABLE (0x1 << 0)
+
+#define U3P_IP_PW_STS2 (SSUSB_SIFSLV_IPPC_BASE + 0x0014)
+#define STS2_U2_MAC_RST (0x1 << 0)
+
+#define U3P_IP_XHCI_CAP (SSUSB_SIFSLV_IPPC_BASE + 0x0024)
+#define CAP_U3_PORT_NUM(p) ((p) & 0xff)
+#define CAP_U2_PORT_NUM(p) (((p) >> 8) & 0xff)
+
+#define U3P_U3_CTRL_0P (SSUSB_SIFSLV_IPPC_BASE + 0x0030)
+#define CTRL_U3_PORT_HOST_SEL (0x1 << 2)
+#define CTRL_U3_PORT_PDN (0x1 << 1)
+#define CTRL_U3_PORT_DIS (0x1 << 0)
+
+#define U3P_U2_CTRL_0P (SSUSB_SIFSLV_IPPC_BASE + 0x0050)
+#define CTRL_U2_PORT_HOST_SEL (0x1 << 2)
+#define CTRL_U2_PORT_PDN (0x1 << 1)
+#define CTRL_U2_PORT_DIS (0x1 << 0)
+
+#define U3P_U3_CTRL(p) (U3P_U3_CTRL_0P + ((p) * 0x08))
+#define U3P_U2_CTRL(p) (U3P_U2_CTRL_0P + ((p) * 0x08))
+
+#define U3P_USBPHYACR0 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0000)
+#define PA0_RG_U2PLL_FORCE_ON (0x1 << 15)
+
+#define U3P_USBPHYACR2 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0008)
+#define PA2_RG_SIF_U2PLL_FORCE_EN (0x1 << 18)
+
+#define U3P_USBPHYACR5 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0014)
+#define PA5_RG_U2_HSTX_SRCTRL (0x7 << 12)
+#define PA5_RG_U2_HSTX_SRCTRL_VAL(x) ((0x7 & (x)) << 12)
+#define PA5_RG_U2_HS_100U_U3_EN (0x1 << 11)
+
+#define U3P_USBPHYACR6 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0018)
+#define PA6_RG_U2_ISO_EN (0x1 << 31)
+#define PA6_RG_U2_BC11_SW_EN (0x1 << 23)
+#define PA6_RG_U2_OTG_VBUSCMP_EN (0x1 << 20)
+
+#define U3P_U2PHYACR4 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0020)
+#define P2C_RG_USB20_GPIO_CTL (0x1 << 9)
+#define P2C_USB20_GPIO_MODE (0x1 << 8)
+#define P2C_U2_GPIO_CTR_MSK (P2C_RG_USB20_GPIO_CTL | P2C_USB20_GPIO_MODE)
+
+#define U3D_U2PHYDCR0 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0060)
+#define P2C_RG_SIF_U2PLL_FORCE_ON (0x1 << 24)
+
+#define U3P_U2PHYDTM0 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0068)
+#define P2C_FORCE_UART_EN (0x1 << 26)
+#define P2C_FORCE_DATAIN (0x1 << 23)
+#define P2C_FORCE_DM_PULLDOWN (0x1 << 21)
+#define P2C_FORCE_DP_PULLDOWN (0x1 << 20)
+#define P2C_FORCE_XCVRSEL (0x1 << 19)
+#define P2C_FORCE_SUSPENDM (0x1 << 18)
+#define P2C_FORCE_TERMSEL (0x1 << 17)
+#define P2C_RG_DATAIN (0xf << 10)
+#define P2C_RG_DATAIN_VAL(x) ((0xf & (x)) << 10)
+#define P2C_RG_DMPULLDOWN (0x1 << 7)
+#define P2C_RG_DPPULLDOWN (0x1 << 6)
+#define P2C_RG_XCVRSEL (0x3 << 4)
+#define P2C_RG_XCVRSEL_VAL(x) ((0x3 & (x)) << 4)
+#define P2C_RG_SUSPENDM (0x1 << 3)
+#define P2C_RG_TERMSEL (0x1 << 2)
+#define P2C_DTM0_PART_MASK \
+ (P2C_FORCE_DATAIN | P2C_FORCE_DM_PULLDOWN | \
+ P2C_FORCE_DP_PULLDOWN | P2C_FORCE_XCVRSEL | \
+ P2C_FORCE_TERMSEL | P2C_RG_DMPULLDOWN | \
+ P2C_RG_DPPULLDOWN | P2C_RG_TERMSEL)
+
+#define U3P_U2PHYDTM1 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x006C)
+#define P2C_RG_UART_EN (0x1 << 16)
+#define P2C_RG_VBUSVALID (0x1 << 5)
+#define P2C_RG_SESSEND (0x1 << 4)
+#define P2C_RG_AVALID (0x1 << 2)
+
+#define U3P_U3_PHYA_REG0 (SSUSB_USB30_PHYA_SIV_B_BASE + 0x0000)
+#define P3A_RG_U3_VUSB10_ON (1 << 5)
+
+#define U3P_U3_PHYA_REG6 (SSUSB_USB30_PHYA_SIV_B_BASE + 0x0018)
+#define P3A_RG_TX_EIDLE_CM (0xf << 28)
+#define P3A_RG_TX_EIDLE_CM_VAL(x) ((0xf & (x)) << 28)
+
+#define U3P_U3_PHYA_REG9 (SSUSB_USB30_PHYA_SIV_B_BASE + 0x0024)
+#define P3A_RG_RX_DAC_MUX (0x1f << 1)
+#define P3A_RG_RX_DAC_MUX_VAL(x) ((0x1f & (x)) << 1)
+
+#define U3P_U3PHYA_DA_REG0 (SSUSB_SIFSLV_U3PHYA_DA_BASE + 0x0)
+#define P3A_RG_XTAL_EXT_EN_U3 (0x3 << 10)
+#define P3A_RG_XTAL_EXT_EN_U3_VAL(x) ((0x3 & (x)) << 10)
+
+#define U3P_PHYD_CDR1 (SSUSB_SIFSLV_U3PHYD_BASE + 0x5c)
+#define P3D_RG_CDR_BIR_LTD1 (0x1f << 24)
+#define P3D_RG_CDR_BIR_LTD1_VAL(x) ((0x1f & (x)) << 24)
+#define P3D_RG_CDR_BIR_LTD0 (0x1f << 8)
+#define P3D_RG_CDR_BIR_LTD0_VAL(x) ((0x1f & (x)) << 8)
+
+#define U3P_XTALCTL3 (SSUSB_SIFSLV_SPLLC + 0x18)
+#define XC3_RG_U3_XTAL_RX_PWD (0x1 << 9)
+#define XC3_RG_U3_FRC_XTAL_RX_PWD (0x1 << 8)
+
+#define U3P_UX_EXIT_LFPS_PARAM (SSUSB_USB3_MAC_CSR_BASE + 0x00A0)
+#define RX_UX_EXIT_REF (0xff << 8)
+#define RX_UX_EXIT_REF_VAL (0x3 << 8)
+
+#define U3P_REF_CLK_PARAM (SSUSB_USB3_MAC_CSR_BASE + 0x00B0)
+#define REF_CLK_1000NS (0xff << 0)
+#define REF_CLK_VAL_DEF (0xa << 0)
+
+#define U3P_LINK_PM_TIMER (SSUSB_USB3_SYS_CSR_BASE + 0x0208)
+#define PM_LC_TIMEOUT (0xf << 0)
+#define PM_LC_TIMEOUT_VAL (0x3 << 0)
+
+#define U3P_TIMING_PULSE_CTRL (SSUSB_USB3_SYS_CSR_BASE + 0x02B4)
+#define U3T_CNT_1US (0xff << 0)
+#define U3T_CNT_1US_VAL (0x3f << 0) /* 62.5MHz: 63 */
+
+#define U3P_U2_TIMING_PARAM (SSUSB_USB2_CSR_BASE + 0x0040)
+#define U2T_VAL_1US (0xff << 0)
+#define U2T_VAL_1US_VAL (0x3f << 0) /* 62.5MHz: 63 */
+
+
+#define PERI_WK_CTRL0 0x400
+#define UWK_CTL1_1P_LS_E (0x1 << 0)
+#define UWK_CTL1_1P_LS_C(x) (((x) & 0xf) << 1)
+#define UWK_CTR0_0P_LS_NE (0x1 << 7) /* negedge for 0p linestate*/
+#define UWK_CTR0_0P_LS_PE (0x1 << 8) /* posedge */
+
+#define PERI_WK_CTRL1 0x404
+#define UWK_CTL1_IS_P (0x1 << 6) /* polarity for ip sleep */
+#define UWK_CTL1_0P_LS_P (0x1 << 7)
+#define UWK_CTL1_IDDIG_P (0x1 << 9) /* polarity */
+#define UWK_CTL1_IDDIG_E (0x1 << 10) /* enable debounce */
+#define UWK_CTL1_IDDIG_C(x) (((x) & 0xf) << 11) /* cycle debounce */
+#define UWK_CTL1_0P_LS_E (0x1 << 20)
+#define UWK_CTL1_0P_LS_C(x) (((x) & 0xf) << 21)
+#define UWK_CTL1_IS_E (0x1 << 25)
+#define UWK_CTL1_IS_C(x) (((x) & 0xf) << 26)
+
+enum ssusb_wakeup_src {
+ SSUSB_WK_IP_SLEEP = 1,
+ SSUSB_WK_LINE_STATE = 2,
+};
+
+struct mt65xx_u3phy {
+ struct usb_phy phy;
+ struct device *dev;
+ void __iomem *mac_base; /* only device-mac regs, exclude xhci's */
+ void __iomem *sif_base; /* include sif & sif2 */
+ struct regmap *pericfg;
+ struct clk *wk_deb_p0; /* port0's wakeup debounce clock */
+ struct clk *wk_deb_p1;
+ struct clk *u3phya_ref; /* reference clock of usb3 anolog phy */
+ int wakeup_src;
+ int u2port_num;
+};
+
+
+static void u3p_writel(void __iomem *base, u32 offset, u32 data)
+{
+ writel(data, base + offset);
+}
+
+static u32 u3p_readl(void __iomem *base, u32 offset)
+{
+ return readl(base + offset);
+}
+
+static void u3p_setmsk(void __iomem *base, u32 offset, u32 msk)
+{
+ void __iomem *addr = base + offset;
+
+ writel((readl(addr) | msk), addr);
+}
+
+static void u3p_clrmsk(void __iomem *base, u32 offset, u32 msk)
+{
+ void __iomem *addr = base + offset;
+
+ writel((readl(addr) & ~msk), addr);
+}
+
+static void u3p_setval(void __iomem *base, u32 offset,
+ u32 mask, u32 value)
+{
+ void __iomem *addr = base + offset;
+ unsigned int new_value;
+
+ new_value = (readl(addr) & ~mask) | value;
+ writel(new_value, addr);
+}
+
+static void phy_index_power_on(struct mt65xx_u3phy *u3phy, int index)
+{
+ void __iomem *sif_base = u3phy->sif_base + U3P_PHY_BASE(index);
+
+ if (!index) {
+ /* Set RG_SSUSB_VUSB10_ON as 1 after VUSB10 ready */
+ u3p_setmsk(sif_base, U3P_U3_PHYA_REG0, P3A_RG_U3_VUSB10_ON);
+ /* power domain iso disable */
+ u3p_clrmsk(sif_base, U3P_USBPHYACR6, PA6_RG_U2_ISO_EN);
+ }
+
+ /* switch to USB function. (system register, force ip into usb mode) */
+ u3p_clrmsk(sif_base, U3P_U2PHYDTM0, P2C_FORCE_UART_EN);
+ u3p_clrmsk(sif_base, U3P_U2PHYDTM1, P2C_RG_UART_EN);
+ if (!index)
+ u3p_clrmsk(sif_base, U3P_U2PHYACR4, P2C_U2_GPIO_CTR_MSK);
+
+ /* (force_suspendm=0) (let suspendm=1, enable usb 480MHz pll) */
+ u3p_clrmsk(sif_base, U3P_U2PHYDTM0, P2C_FORCE_SUSPENDM);
+ u3p_clrmsk(sif_base, U3P_U2PHYDTM0,
+ P2C_RG_XCVRSEL | P2C_RG_DATAIN | P2C_DTM0_PART_MASK);
+
+ /* DP/DM BC1.1 path Disable */
+ u3p_clrmsk(sif_base, U3P_USBPHYACR6, PA6_RG_U2_BC11_SW_EN);
+ /* OTG Enable */
+ u3p_setmsk(sif_base, U3P_USBPHYACR6, PA6_RG_U2_OTG_VBUSCMP_EN);
+ u3p_setval(sif_base, U3P_U3PHYA_DA_REG0, P3A_RG_XTAL_EXT_EN_U3,
+ P3A_RG_XTAL_EXT_EN_U3_VAL(2));
+ u3p_setval(sif_base, U3P_U3_PHYA_REG9, P3A_RG_RX_DAC_MUX,
+ P3A_RG_RX_DAC_MUX_VAL(4));
+
+ if (!index) {
+ u3p_setmsk(sif_base, U3P_XTALCTL3, XC3_RG_U3_XTAL_RX_PWD);
+ u3p_setmsk(sif_base, U3P_XTALCTL3, XC3_RG_U3_FRC_XTAL_RX_PWD);
+ /* [mt8173]disable Change 100uA current from SSUSB */
+ u3p_clrmsk(sif_base, U3P_USBPHYACR5, PA5_RG_U2_HS_100U_U3_EN);
+ }
+ u3p_setval(sif_base, U3P_U3_PHYA_REG6, P3A_RG_TX_EIDLE_CM,
+ P3A_RG_TX_EIDLE_CM_VAL(0xe));
+ u3p_setval(sif_base, U3P_PHYD_CDR1, P3D_RG_CDR_BIR_LTD0,
+ P3D_RG_CDR_BIR_LTD0_VAL(0xc));
+ u3p_setval(sif_base, U3P_PHYD_CDR1, P3D_RG_CDR_BIR_LTD1,
+ P3D_RG_CDR_BIR_LTD1_VAL(0x3));
+
+ udelay(800);
+ u3p_setmsk(sif_base, U3P_U2PHYDTM1, P2C_RG_VBUSVALID | P2C_RG_AVALID);
+ u3p_clrmsk(sif_base, U3P_U2PHYDTM1, P2C_RG_SESSEND);
+
+ /* USB 2.0 slew rate calibration */
+ u3p_setval(sif_base, U3P_USBPHYACR5, PA5_RG_U2_HSTX_SRCTRL,
+ PA5_RG_U2_HSTX_SRCTRL_VAL(4));
+
+ dev_dbg(u3phy->dev, "%s(%d)\n", __func__, index);
+}
+
+static void phy_index_power_off(struct mt65xx_u3phy *u3phy, int index)
+{
+ void __iomem *sif_base = u3phy->sif_base + U3P_PHY_BASE(index);
+
+ /* switch to USB function. (system register, force ip into usb mode) */
+ u3p_clrmsk(sif_base, U3P_U2PHYDTM0, P2C_FORCE_UART_EN);
+ u3p_clrmsk(sif_base, U3P_U2PHYDTM1, P2C_RG_UART_EN);
+ if (!index)
+ u3p_clrmsk(sif_base, U3P_U2PHYACR4, P2C_U2_GPIO_CTR_MSK);
+
+ u3p_setmsk(sif_base, U3P_U2PHYDTM0, P2C_FORCE_SUSPENDM);
+ u3p_setval(sif_base, U3P_U2PHYDTM0,
+ P2C_RG_XCVRSEL, P2C_RG_XCVRSEL_VAL(1));
+ u3p_setval(sif_base, U3P_U2PHYDTM0,
+ P2C_RG_DATAIN, P2C_RG_DATAIN_VAL(0));
+ u3p_setmsk(sif_base, U3P_U2PHYDTM0, P2C_DTM0_PART_MASK);
+ /* DP/DM BC1.1 path Disable */
+ u3p_clrmsk(sif_base, U3P_USBPHYACR6, PA6_RG_U2_BC11_SW_EN);
+ /* OTG Disable */
+ u3p_clrmsk(sif_base, U3P_USBPHYACR6, PA6_RG_U2_OTG_VBUSCMP_EN);
+ if (!index) {
+ /* Change 100uA current switch to USB2.0 */
+ u3p_clrmsk(sif_base, U3P_USBPHYACR5, PA5_RG_U2_HS_100U_U3_EN);
+ }
+ udelay(800);
+
+ /* let suspendm=0, set utmi into analog power down */
+ u3p_clrmsk(sif_base, U3P_U2PHYDTM0, P2C_RG_SUSPENDM);
+ udelay(1);
+
+ u3p_clrmsk(sif_base, U3P_U2PHYDTM1, P2C_RG_VBUSVALID | P2C_RG_AVALID);
+ u3p_setmsk(sif_base, U3P_U2PHYDTM1, P2C_RG_SESSEND);
+ if (!index) {
+ /* Set RG_SSUSB_VUSB10_ON as 1 after VUSB10 ready */
+ u3p_clrmsk(sif_base, U3P_U3_PHYA_REG0, P3A_RG_U3_VUSB10_ON);
+ }
+ dev_dbg(u3phy->dev, "%s(%d)\n", __func__, index);
+}
+
+static void u3phy_power_on(struct mt65xx_u3phy *u3phy)
+{
+ phy_index_power_on(u3phy, 0);
+ if (u3phy->u2port_num > 1)
+ phy_index_power_on(u3phy, 1);
+}
+
+static void u3phy_power_off(struct mt65xx_u3phy *u3phy)
+{
+ phy_index_power_off(u3phy, 0);
+ if (u3phy->u2port_num > 1)
+ phy_index_power_off(u3phy, 1);
+}
+
+static int check_ip_clk_status(struct mt65xx_u3phy *u3phy)
+{
+ int ret;
+ int u3_port_num;
+ int u2_port_num;
+ u32 xhci_cap;
+ u32 val;
+ void __iomem *sif_base = u3phy->sif_base;
+
+ xhci_cap = u3p_readl(sif_base, U3P_IP_XHCI_CAP);
+ u3_port_num = CAP_U3_PORT_NUM(xhci_cap);
+ u2_port_num = CAP_U2_PORT_NUM(xhci_cap);
+
+ ret = readl_poll_timeout(sif_base + U3P_IP_PW_STS1, val,
+ (val & STS1_SYSPLL_STABLE), 100, 10000);
+ if (ret) {
+ dev_err(u3phy->dev, "sypll is not stable!!!\n");
+ return ret;
+ }
+
+ ret = readl_poll_timeout(sif_base + U3P_IP_PW_STS1, val,
+ (val & STS1_REF_RST), 100, 10000);
+ if (ret) {
+ dev_err(u3phy->dev, "ref_clk is still active!!!\n");
+ return ret;
+ }
+
+ ret = readl_poll_timeout(sif_base + U3P_IP_PW_STS1, val,
+ (val & STS1_SYS125_RST), 100, 10000);
+ if (ret) {
+ dev_err(u3phy->dev, "sys125_ck is still active!!!\n");
+ return ret;
+ }
+
+ if (u3_port_num) {
+ ret = readl_poll_timeout(sif_base + U3P_IP_PW_STS1, val,
+ (val & STS1_U3_MAC_RST), 100, 10000);
+ if (ret) {
+ dev_err(u3phy->dev, "mac3_mac_ck is still active!!!\n");
+ return ret;
+ }
+ }
+
+ if (u2_port_num) {
+ ret = readl_poll_timeout(sif_base + U3P_IP_PW_STS2, val,
+ (val & STS2_U2_MAC_RST), 100, 10000);
+ if (ret) {
+ dev_err(u3phy->dev, "mac2_sys_ck is still active!!!\n");
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static int u3phy_ports_enable(struct mt65xx_u3phy *u3phy)
+{
+ int i;
+ u32 temp;
+ int u3_port_num;
+ int u2_port_num;
+ void __iomem *sif_base = u3phy->sif_base;
+
+ temp = u3p_readl(sif_base, U3P_IP_XHCI_CAP);
+ u3_port_num = CAP_U3_PORT_NUM(temp);
+ u2_port_num = CAP_U2_PORT_NUM(temp);
+ dev_dbg(u3phy->dev, "%s u2p:%d, u3p:%d\n",
+ __func__, u2_port_num, u3_port_num);
+
+ /* power on host ip */
+ u3p_clrmsk(sif_base, U3P_IP_PW_CTRL1, CTRL1_IP_HOST_PDN);
+
+ /* power on and enable all u3 ports */
+ for (i = 0; i < u3_port_num; i++) {
+ temp = u3p_readl(sif_base, U3P_U3_CTRL(i));
+ temp &= ~(CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS);
+ temp |= CTRL_U3_PORT_HOST_SEL;
+ u3p_writel(sif_base, U3P_U3_CTRL(i), temp);
+ }
+
+ /* power on and enable all u2 ports */
+ for (i = 0; i < u2_port_num; i++) {
+ temp = u3p_readl(sif_base, U3P_U2_CTRL(i));
+ temp &= ~(CTRL_U2_PORT_PDN | CTRL_U2_PORT_DIS);
+ temp |= CTRL_U2_PORT_HOST_SEL;
+ u3p_writel(sif_base, U3P_U2_CTRL(i), temp);
+ }
+ return check_ip_clk_status(u3phy);
+}
+
+static int u3phy_ports_disable(struct mt65xx_u3phy *u3phy)
+{
+ int i;
+ u32 temp;
+ int ret;
+ int u3_port_num;
+ int u2_port_num;
+ void __iomem *sif_base = u3phy->sif_base;
+
+ temp = u3p_readl(sif_base, U3P_IP_XHCI_CAP);
+ u3_port_num = CAP_U3_PORT_NUM(temp);
+ u2_port_num = CAP_U2_PORT_NUM(temp);
+ dev_dbg(u3phy->dev, "%s u2p:%d, u3p:%d\n",
+ __func__, u2_port_num, u3_port_num);
+
+ /* power on and enable all u3 ports */
+ for (i = 0; i < u3_port_num; i++) {
+ temp = u3p_readl(sif_base, U3P_U3_CTRL(i));
+ temp |= CTRL_U3_PORT_PDN;
+ u3p_writel(sif_base, U3P_U3_CTRL(i), temp);
+ }
+
+ /* power on and enable all u2 ports */
+ for (i = 0; i < u2_port_num; i++) {
+ temp = u3p_readl(sif_base, U3P_U2_CTRL(i));
+ temp |= CTRL_U2_PORT_PDN;
+ u3p_writel(sif_base, U3P_U2_CTRL(i), temp);
+ }
+
+ /* power off host ip */
+ u3p_setmsk(sif_base, U3P_IP_PW_CTRL1, CTRL1_IP_HOST_PDN);
+ u3p_setmsk(sif_base, U3P_IP_PW_CTRL2, CTRL2_IP_DEV_PDN);
+
+ ret = readl_poll_timeout(sif_base + U3P_IP_PW_STS1, temp,
+ (temp & STS1_IP_SLEEP_STS), 100, 100000);
+ if (ret) {
+ dev_err(u3phy->dev, "ip sleep failed!!!\n");
+ return ret;
+ }
+ return 0;
+}
+
+static void u3phy_timing_init(struct mt65xx_u3phy *u3phy)
+{
+ void __iomem *mbase = u3phy->mac_base;
+ int u3_port_num;
+ u32 temp;
+
+ temp = u3p_readl(u3phy->sif_base, U3P_IP_XHCI_CAP);
+ u3_port_num = CAP_U3_PORT_NUM(temp);
+
+ if (u3_port_num) {
+ /* set MAC reference clock speed */
+ u3p_setval(mbase, U3P_UX_EXIT_LFPS_PARAM,
+ RX_UX_EXIT_REF, RX_UX_EXIT_REF_VAL);
+ /* set REF_CLK */
+ u3p_setval(mbase, U3P_REF_CLK_PARAM,
+ REF_CLK_1000NS, REF_CLK_VAL_DEF);
+ /* set SYS_CLK */
+ u3p_setval(mbase, U3P_TIMING_PULSE_CTRL,
+ U3T_CNT_1US, U3T_CNT_1US_VAL);
+ /* set LINK_PM_TIMER=3 */
+ u3p_setval(mbase, U3P_LINK_PM_TIMER,
+ PM_LC_TIMEOUT, PM_LC_TIMEOUT_VAL);
+ }
+ u3p_setval(mbase, U3P_U2_TIMING_PARAM, U2T_VAL_1US, U2T_VAL_1US_VAL);
+}
+
+static int u3phy_clks_enable(struct mt65xx_u3phy *u3phy)
+{
+ int ret;
+
+ ret = clk_prepare_enable(u3phy->u3phya_ref);
+ if (ret) {
+ dev_err(u3phy->dev, "failed to enable u3phya_ref\n");
+ goto u3phya_ref_err;
+ }
+ ret = clk_prepare_enable(u3phy->wk_deb_p0);
+ if (ret) {
+ dev_err(u3phy->dev, "failed to enable wk_deb_p0\n");
+ goto usb_p0_err;
+ }
+ if (u3phy->u2port_num > 1) {
+ ret = clk_prepare_enable(u3phy->wk_deb_p1);
+ if (ret) {
+ dev_err(u3phy->dev, "failed to enable wk_deb_p1\n");
+ goto usb_p1_err;
+ }
+ }
+ udelay(50);
+
+ return 0;
+
+usb_p1_err:
+ clk_disable_unprepare(u3phy->wk_deb_p0);
+usb_p0_err:
+ clk_disable_unprepare(u3phy->u3phya_ref);
+u3phya_ref_err:
+ return -EINVAL;
+}
+
+static void u3phy_clks_disable(struct mt65xx_u3phy *u3phy)
+{
+ if (u3phy->u2port_num > 1)
+ clk_disable_unprepare(u3phy->wk_deb_p1);
+ clk_disable_unprepare(u3phy->wk_deb_p0);
+ clk_disable_unprepare(u3phy->u3phya_ref);
+}
+
+/* only clocks can be turn off for ip-sleep wakeup mode */
+static void usb_wakeup_ip_sleep_en(struct mt65xx_u3phy *u3phy)
+{
+ u32 tmp;
+ struct regmap *pericfg = u3phy->pericfg;
+
+ regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
+ tmp &= ~UWK_CTL1_IS_P;
+ tmp &= ~(UWK_CTL1_IS_C(0xf));
+ tmp |= UWK_CTL1_IS_C(0x8);
+ regmap_write(pericfg, PERI_WK_CTRL1, tmp);
+ regmap_write(pericfg, PERI_WK_CTRL1, tmp | UWK_CTL1_IS_E);
+
+ regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
+ dev_dbg(u3phy->dev, "%s(): WK_CTRL1[P6,E25,C26:29]=%#x\n", __func__,
+ tmp);
+}
+
+static void usb_wakeup_ip_sleep_dis(struct mt65xx_u3phy *u3phy)
+{
+ u32 tmp;
+
+ regmap_read(u3phy->pericfg, PERI_WK_CTRL1, &tmp);
+ tmp &= ~UWK_CTL1_IS_E;
+ regmap_write(u3phy->pericfg, PERI_WK_CTRL1, tmp);
+}
+
+/*
+* for line-state wakeup mode, phy's power should not power-down
+* and only support cable plug in/out
+*/
+static void usb_wakeup_line_state_en(struct mt65xx_u3phy *u3phy)
+{
+ u32 tmp;
+ struct regmap *pericfg = u3phy->pericfg;
+
+ /* line-state of u2-port0 */
+ regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
+ tmp &= ~UWK_CTL1_0P_LS_P;
+ tmp &= ~(UWK_CTL1_0P_LS_C(0xf));
+ tmp |= UWK_CTL1_0P_LS_C(0x8);
+ regmap_write(pericfg, PERI_WK_CTRL1, tmp);
+ regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
+ regmap_write(pericfg, PERI_WK_CTRL1, tmp | UWK_CTL1_0P_LS_E);
+
+ /* line-state of u2-port1 if support */
+ if (u3phy->u2port_num > 1) {
+ regmap_read(pericfg, PERI_WK_CTRL0, &tmp);
+ tmp &= ~(UWK_CTL1_1P_LS_C(0xf));
+ tmp |= UWK_CTL1_1P_LS_C(0x8);
+ regmap_write(pericfg, PERI_WK_CTRL0, tmp);
+ regmap_write(pericfg, PERI_WK_CTRL0, tmp | UWK_CTL1_1P_LS_E);
+ }
+}
+
+static void usb_wakeup_line_state_dis(struct mt65xx_u3phy *u3phy)
+{
+ u32 tmp;
+ struct regmap *pericfg = u3phy->pericfg;
+
+ regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
+ tmp &= ~UWK_CTL1_0P_LS_E;
+ regmap_write(pericfg, PERI_WK_CTRL1, tmp);
+
+ if (u3phy->u2port_num > 1) {
+ regmap_read(pericfg, PERI_WK_CTRL0, &tmp);
+ tmp &= ~UWK_CTL1_1P_LS_E;
+ regmap_write(pericfg, PERI_WK_CTRL0, tmp);
+ }
+}
+
+static void usb_wakeup_enable(struct mt65xx_u3phy *u3phy)
+{
+ if (u3phy->wakeup_src == SSUSB_WK_IP_SLEEP)
+ usb_wakeup_ip_sleep_en(u3phy);
+ else if (u3phy->wakeup_src == SSUSB_WK_LINE_STATE)
+ usb_wakeup_line_state_en(u3phy);
+}
+
+static void usb_wakeup_disable(struct mt65xx_u3phy *u3phy)
+{
+ if (u3phy->wakeup_src == SSUSB_WK_IP_SLEEP)
+ usb_wakeup_ip_sleep_dis(u3phy);
+ else if (u3phy->wakeup_src == SSUSB_WK_LINE_STATE)
+ usb_wakeup_line_state_dis(u3phy);
+}
+
+static int mt65xx_u3phy_init(struct usb_phy *phy)
+{
+ struct mt65xx_u3phy *u3phy;
+ int ret;
+
+ u3phy = container_of(phy, struct mt65xx_u3phy, phy);
+ dev_dbg(u3phy->dev, "%s+\n", __func__);
+
+ ret = pm_runtime_get_sync(u3phy->dev);
+ if (ret < 0)
+ goto pm_err;
+
+ ret = u3phy_clks_enable(u3phy);
+ if (ret) {
+ dev_err(u3phy->dev, "failed to enable clks\n");
+ goto clks_err;
+ }
+
+ /* reset whole ip */
+ u3p_setmsk(u3phy->sif_base, U3P_IP_PW_CTRL0, CTRL0_IP_SW_RST);
+ u3p_clrmsk(u3phy->sif_base, U3P_IP_PW_CTRL0, CTRL0_IP_SW_RST);
+
+ ret = u3phy_ports_enable(u3phy);
+ if (ret) {
+ dev_err(u3phy->dev, "failed to enable ports\n");
+ goto port_err;
+ }
+ u3phy_timing_init(u3phy);
+ u3phy_power_on(u3phy);
+ msleep(40);
+
+ return 0;
+
+port_err:
+ u3phy_clks_disable(u3phy);
+clks_err:
+ pm_runtime_put_sync(u3phy->dev);
+pm_err:
+ return ret;
+}
+
+
+static void mt65xx_u3phy_shutdown(struct usb_phy *phy)
+{
+ struct mt65xx_u3phy *u3phy;
+
+ u3phy = container_of(phy, struct mt65xx_u3phy, phy);
+ u3phy_power_off(u3phy);
+ u3phy_clks_disable(u3phy);
+ pm_runtime_put_sync(u3phy->dev);
+}
+
+
+static int mt65xx_u3phy_suspend(struct usb_phy *x, int suspend)
+{
+ struct mt65xx_u3phy *u3phy = container_of(x, struct mt65xx_u3phy, phy);
+
+ if (suspend) {
+ u3phy_ports_disable(u3phy);
+ u3phy_power_off(u3phy);
+ u3phy_clks_disable(u3phy);
+ usb_wakeup_enable(u3phy);
+ } else {
+ usb_wakeup_disable(u3phy);
+ u3phy_clks_enable(u3phy);
+ u3phy_power_on(u3phy);
+ u3phy_ports_enable(u3phy);
+ }
+ return 0;
+}
+
+
+static const struct of_device_id mt65xx_u3phy_id_table[] = {
+ { .compatible = "mediatek,mt8173-u3phy",},
+ { },
+};
+MODULE_DEVICE_TABLE(of, mt65xx_u3phy_id_table);
+
+
+static int mt65xx_u3phy_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct resource *mac_res;
+ struct resource *sif_res;
+ struct mt65xx_u3phy *u3phy;
+ int retval = -ENOMEM;
+
+ u3phy = devm_kzalloc(&pdev->dev, sizeof(*u3phy), GFP_KERNEL);
+ if (!u3phy)
+ goto err;
+
+ u3phy->dev = &pdev->dev;
+
+ mac_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ u3phy->mac_base = devm_ioremap_resource(dev, mac_res);
+ if (IS_ERR(u3phy->mac_base)) {
+ dev_err(dev, "failed to remap mac regs\n");
+ retval = PTR_ERR(u3phy->mac_base);
+ goto err;
+ }
+
+ sif_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ u3phy->sif_base = devm_ioremap_resource(dev, sif_res);
+ if (IS_ERR(u3phy->sif_base)) {
+ dev_err(dev, "failed to remap sif regs\n");
+ retval = PTR_ERR(u3phy->sif_base);
+ goto err;
+ }
+
+ of_property_read_u32(np, "u2port-num", &u3phy->u2port_num);
+ of_property_read_u32(np, "wakeup-src", &u3phy->wakeup_src);
+
+ u3phy->u3phya_ref = devm_clk_get(dev, "u3phya_ref");
+ if (IS_ERR(u3phy->u3phya_ref)) {
+ dev_err(dev, "error to get u3phya_ref\n");
+ retval = PTR_ERR(u3phy->u3phya_ref);
+ goto err;
+ }
+
+ u3phy->wk_deb_p0 = devm_clk_get(u3phy->dev, "wakeup_deb_p0");
+ if (IS_ERR(u3phy->wk_deb_p0)) {
+ dev_err(dev, "error to get wakeup_deb_p0\n");
+ retval = PTR_ERR(u3phy->wk_deb_p0);
+ goto err;
+ }
+
+ if (u3phy->u2port_num > 1) {
+ u3phy->wk_deb_p1 = devm_clk_get(u3phy->dev, "wakeup_deb_p1");
+ if (IS_ERR(u3phy->wk_deb_p1)) {
+ dev_err(dev, "error to get wakeup_deb_p1\n");
+ retval = PTR_ERR(u3phy->wk_deb_p1);
+ goto err;
+ }
+ }
+
+ u3phy->pericfg = syscon_regmap_lookup_by_phandle(np, "usb-wakeup-ctrl");
+ if (IS_ERR(u3phy->pericfg)) {
+ dev_err(dev, "cannot get pericfg regs\n");
+ retval = PTR_ERR(u3phy->pericfg);
+ goto err;
+ }
+
+ device_init_wakeup(dev, 1);
+ pm_runtime_enable(dev);
+ u3phy->phy.dev = u3phy->dev;
+ u3phy->phy.label = "mt65xx-usb3phy";
+ u3phy->phy.type = USB_PHY_TYPE_USB3;
+ u3phy->phy.init = mt65xx_u3phy_init;
+ u3phy->phy.shutdown = mt65xx_u3phy_shutdown;
+ u3phy->phy.set_suspend = mt65xx_u3phy_suspend;
+
+ platform_set_drvdata(pdev, u3phy);
+ retval = usb_add_phy_dev(&u3phy->phy);
+ if (retval) {
+ dev_err(dev, "failed to add phy\n");
+ goto add_phy_err;
+ }
+
+ return 0;
+
+add_phy_err:
+ pm_runtime_disable(dev);
+err:
+ return retval;
+}
+
+static int mt65xx_u3phy_remove(struct platform_device *pdev)
+{
+ struct mt65xx_u3phy *u3phy = platform_get_drvdata(pdev);
+
+ mt65xx_u3phy_shutdown(&u3phy->phy);
+ device_init_wakeup(&pdev->dev, 0);
+ pm_runtime_disable(&pdev->dev);
+ usb_remove_phy(&u3phy->phy);
+
+ return 0;
+}
+
+static struct platform_driver mt65xx_u3phy_driver = {
+ .probe = mt65xx_u3phy_probe,
+ .remove = mt65xx_u3phy_remove,
+ .driver = {
+ .name = "mt65xx-u3phy",
+ .of_match_table = mt65xx_u3phy_id_table,
+ },
+};
+
+module_platform_driver(mt65xx_u3phy_driver);
+
+MODULE_DESCRIPTION("Mt65xx USB PHY driver");
+MODULE_LICENSE("GPL v2");
--
1.8.1.1.dirty
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v2 4/5] xhci: mediatek: support MTK xHCI host controller
2015-07-08 9:41 [PATCH v2 0/5] Mediatek xHCI support Chunfeng Yun
` (2 preceding siblings ...)
2015-07-08 9:41 ` [PATCH v2 3/5] usb: phy: add usb3.0 phy driver for mt65xx SoCs Chunfeng Yun
@ 2015-07-08 9:41 ` Chunfeng Yun
2015-07-13 14:52 ` John Crispin
2015-07-08 9:41 ` [PATCH v2 5/5] arm64: dts: mediatek: add xHCI & usb phy for mt8173 Chunfeng Yun
4 siblings, 1 reply; 22+ messages in thread
From: Chunfeng Yun @ 2015-07-08 9:41 UTC (permalink / raw)
To: Mathias Nyman
Cc: Rob Herring, Mark Rutland, Matthias Brugger, Felipe Balbi,
Chunfeng Yun, Sascha Hauer, devicetree, linux-kernel,
linux-arm-kernel, Roger Quadros, linux-usb, linux-mediatek
MTK xhci host controller defines some extra SW scheduling
parameters for HW to minimize the scheduling effort for
synchronous and interrupt endpoints. The parameters are
put into reseved DWs of slot context and endpoint context
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
drivers/usb/host/Kconfig | 9 +
drivers/usb/host/Makefile | 1 +
drivers/usb/host/xhci-mtk.c | 814 +++++++++++++++++++++++++++++++++++++++++++
drivers/usb/host/xhci-mtk.h | 108 ++++++
drivers/usb/host/xhci-ring.c | 35 +-
drivers/usb/host/xhci.c | 19 +-
drivers/usb/host/xhci.h | 1 +
7 files changed, 980 insertions(+), 7 deletions(-)
create mode 100644 drivers/usb/host/xhci-mtk.c
create mode 100644 drivers/usb/host/xhci-mtk.h
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 8afc3c1..2202c68 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -34,6 +34,15 @@ config USB_XHCI_PCI
config USB_XHCI_PLATFORM
tristate
+config USB_XHCI_MTK
+ tristate "xHCI support for Mediatek MT65xx"
+ select USB_XHCI_PLATFORM
+ depends on ARCH_MEDIATEK || COMPILE_TEST
+ ---help---
+ Say 'Y' to enable the support for the xHCI host controller
+ found in Mediatek MT65xx SoCs.
+ If unsure, say N.
+
config USB_XHCI_MVEBU
tristate "xHCI support for Marvell Armada 375/38x"
select USB_XHCI_PLATFORM
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 754efaa..90c6eb2 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -30,6 +30,7 @@ endif
obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
obj-$(CONFIG_USB_XHCI_PLATFORM) += xhci-plat-hcd.o
+obj-$(CONFIG_USB_XHCI_MTK) += xhci-mtk.o
obj-$(CONFIG_USB_EHCI_HCD) += ehci-hcd.o
obj-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c
new file mode 100644
index 0000000..45f0606
--- /dev/null
+++ b/drivers/usb/host/xhci-mtk.c
@@ -0,0 +1,814 @@
+/*
+ * Copyright (c) 2015 MediaTek Inc.
+ * Author:
+ * Zhigang.Wei <zhigang.wei@mediatek.com>
+ * Chunfeng.Yun <chunfeng.yun@mediatek.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/dma-mapping.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/usb/phy.h>
+#include <linux/slab.h>
+#include <linux/usb/xhci_pdriver.h>
+#include <linux/regulator/consumer.h>
+#include <linux/pm_runtime.h>
+
+#include "xhci.h"
+#include "xhci-mtk.h"
+
+
+#define SS_BW_BOUNDARY 51000
+/* table 5-5. High-speed Isoc Transaction Limits in usb_20 spec */
+#define HS_BW_BOUNDARY 6144
+/* usb2 spec section11.18.1: at most 188 FS bytes per microframe */
+#define FS_PAYLOAD_MAX 188
+
+/* mtk scheduler bitmasks */
+#define EP_BPKTS(p) ((p) & 0x3f)
+#define EP_BCSCOUNT(p) (((p) & 0x7) << 8)
+#define EP_BBM(p) ((p) << 11)
+#define EP_BOFFSET(p) ((p) & 0x3fff)
+#define EP_BREPEAT(p) (((p) & 0x7fff) << 16)
+
+
+struct xhci_hcd_mtk {
+ struct device *dev;
+ struct usb_hcd *hcd;
+ struct mu3h_sch_bw_info *sch_array;
+ struct regulator *vusb33;
+ struct regulator *vbus;
+ struct clk *sys_mac; /* sys and mac clock */
+};
+
+
+static int is_fs_or_ls(enum usb_device_speed speed)
+{
+ return speed == USB_SPEED_FULL || speed == USB_SPEED_LOW;
+}
+
+static int get_bw_index(struct xhci_hcd *xhci, struct usb_device *udev,
+ struct usb_host_endpoint *ep)
+{
+ int bw_index;
+ int port_id;
+ struct xhci_virt_device *virt_dev;
+
+ virt_dev = xhci->devs[udev->slot_id];
+ port_id = virt_dev->real_port;
+
+ if (udev->speed == USB_SPEED_SUPER) {
+ if (usb_endpoint_dir_out(&ep->desc))
+ bw_index = (port_id - 1) * 2;
+ else
+ bw_index = (port_id - 1) * 2 + 1;
+ } else {
+ bw_index = port_id + xhci->num_usb3_ports - 1;
+ }
+
+ return bw_index;
+}
+
+
+static void setup_sch_info(struct usb_device *udev,
+ struct xhci_ep_ctx *ep_ctx, struct mu3h_sch_ep_info *sch_ep)
+{
+ u32 ep_type;
+ u32 ep_interval;
+ u32 max_packet_size;
+ u32 max_burst;
+ u32 mult;
+ u32 esit_pkts;
+
+ ep_type = CTX_TO_EP_TYPE(le32_to_cpu(ep_ctx->ep_info2));
+ ep_interval = CTX_TO_EP_INTERVAL(le32_to_cpu(ep_ctx->ep_info));
+ max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
+ max_burst = CTX_TO_MAX_BURST(le32_to_cpu(ep_ctx->ep_info2));
+ mult = CTX_TO_EP_MULT(le32_to_cpu(ep_ctx->ep_info));
+ pr_debug("%s: max_burst = %d, mult = %d\n", __func__, max_burst, mult);
+
+ sch_ep->ep_type = ep_type;
+ sch_ep->max_packet_size = max_packet_size;
+ sch_ep->esit = 1 << ep_interval;
+ sch_ep->offset = 0;
+ sch_ep->burst_mode = 0;
+
+ if (udev->speed == USB_SPEED_HIGH) {
+ sch_ep->cs_count = 0;
+ /*
+ * usb_20 spec section5.9
+ * a single microframe is enough for HS synchromous endpoints
+ * in a interval
+ */
+ sch_ep->num_budget_microframes = 1;
+ sch_ep->repeat = 0;
+ /*
+ * xHCI spec section6.2.3.4
+ * @max_busrt is the number of additional transactions
+ * opportunities per microframe
+ */
+ sch_ep->pkts = max_burst + 1;
+ sch_ep->bw_cost_per_microframe = max_packet_size * sch_ep->pkts;
+ } else if (udev->speed == USB_SPEED_SUPER) {
+ /* usb3_r1 spec section4.4.7 & 4.4.8 */
+ sch_ep->cs_count = 0;
+ esit_pkts = (mult + 1) * (max_burst + 1);
+ if (ep_type == INT_IN_EP || ep_type == INT_OUT_EP) {
+ sch_ep->pkts = esit_pkts;
+ sch_ep->num_budget_microframes = 1;
+ sch_ep->repeat = 0;
+ }
+
+ if (ep_type == ISOC_IN_EP || ep_type == ISOC_OUT_EP) {
+ if (esit_pkts <= sch_ep->esit)
+ sch_ep->pkts = 1;
+ else
+ sch_ep->pkts = roundup_pow_of_two(esit_pkts)
+ / sch_ep->esit;
+
+ sch_ep->num_budget_microframes =
+ DIV_ROUND_UP(esit_pkts, sch_ep->pkts);
+
+ if (sch_ep->num_budget_microframes > 1)
+ sch_ep->repeat = 1;
+ else
+ sch_ep->repeat = 0;
+ }
+ sch_ep->bw_cost_per_microframe = max_packet_size * sch_ep->pkts;
+ } else if (is_fs_or_ls(udev->speed)) {
+ /*
+ * usb_20 spec section11.18.4
+ * assume worst cases
+ */
+ sch_ep->repeat = 0;
+ sch_ep->pkts = 1; /* at most one packet for each microframe */
+ if (ep_type == INT_IN_EP || ep_type == INT_OUT_EP) {
+ sch_ep->cs_count = 3; /* at most need 3 CS*/
+ /* one for SS and one for budgeted transaction */
+ sch_ep->num_budget_microframes = sch_ep->cs_count + 2;
+ sch_ep->bw_cost_per_microframe = max_packet_size;
+ }
+ if (ep_type == ISOC_OUT_EP) {
+ /* must never schedule a cs ISOC OUT ep */
+ sch_ep->cs_count = 0;
+ /*
+ * the best case FS budget assumes that 188 FS bytes
+ * occur in each microframe
+ */
+ sch_ep->num_budget_microframes = DIV_ROUND_UP(
+ sch_ep->max_packet_size, FS_PAYLOAD_MAX);
+ sch_ep->bw_cost_per_microframe = FS_PAYLOAD_MAX;
+ }
+ if (ep_type == ISOC_IN_EP) {
+ /* at most need additional two CS. */
+ sch_ep->cs_count = DIV_ROUND_UP(
+ sch_ep->max_packet_size, FS_PAYLOAD_MAX) + 2;
+ sch_ep->num_budget_microframes = sch_ep->cs_count + 2;
+ sch_ep->bw_cost_per_microframe = FS_PAYLOAD_MAX;
+ }
+ }
+}
+
+/* Get maximum bandwidth when we schedule at offset slot. */
+static u32 get_max_bw(struct mu3h_sch_bw_info *sch_bw,
+ struct mu3h_sch_ep_info *sch_ep, u32 offset)
+{
+ u32 num_esit;
+ u32 max_bw = 0;
+ int i;
+ int j;
+
+ num_esit = XHCI_MTK_MAX_ESIT / sch_ep->esit;
+ for (i = 0; i < num_esit; i++) {
+ u32 base = offset + i * sch_ep->esit;
+
+ for (j = 0; j < sch_ep->num_budget_microframes; j++) {
+ if (sch_bw->bus_bw[base + j] > max_bw)
+ max_bw = sch_bw->bus_bw[base + j];
+ }
+ }
+ return max_bw;
+}
+
+static void update_bus_bw(struct mu3h_sch_bw_info *sch_bw,
+ struct mu3h_sch_ep_info *sch_ep, int bw_cost)
+{
+ u32 num_esit;
+ u32 base;
+ int i;
+ int j;
+
+ num_esit = XHCI_MTK_MAX_ESIT / sch_ep->esit;
+ for (i = 0; i < num_esit; i++) {
+ base = sch_ep->offset + i * sch_ep->esit;
+ for (j = 0; j < sch_ep->num_budget_microframes; j++)
+ sch_bw->bus_bw[base + j] += bw_cost;
+ }
+
+}
+
+static void debug_sch_ep(struct mu3h_sch_ep_info *sch_ep)
+{
+ pr_debug("%s:\n", __func__);
+ pr_debug("sch_ep->ep_type = %d\n", sch_ep->ep_type);
+ pr_debug("sch_ep->max_packet_size = %d\n", sch_ep->max_packet_size);
+ pr_debug("sch_ep->esit = %d\n", sch_ep->esit);
+ pr_debug("sch_ep->num_budget_microframes = %d\n",
+ sch_ep->num_budget_microframes);
+ pr_debug("sch_ep->bw_cost_per_microframe = %d\n",
+ sch_ep->bw_cost_per_microframe);
+ pr_debug("sch_ep->ep = %p\n", sch_ep->ep);
+ pr_debug("sch_ep->offset = %d\n", sch_ep->offset);
+ pr_debug("sch_ep->repeat = %d\n", sch_ep->repeat);
+ pr_debug("sch_ep->pkts = %d\n", sch_ep->pkts);
+ pr_debug("sch_ep->cs_count = %d\n", sch_ep->cs_count);
+}
+
+static int check_sch_bw(struct usb_device *udev,
+ struct mu3h_sch_bw_info *sch_bw, struct mu3h_sch_ep_info *sch_ep)
+{
+ u32 offset;
+ u32 esit;
+ u32 num_budget_microframes;
+ u32 min_bw;
+ u32 min_index;
+ u32 worst_bw;
+ u32 bw_boundary;
+
+ if (sch_ep->esit > XHCI_MTK_MAX_ESIT)
+ sch_ep->esit = XHCI_MTK_MAX_ESIT;
+
+ esit = sch_ep->esit;
+ num_budget_microframes = sch_ep->num_budget_microframes;
+
+ /*
+ * Search through all possible schedule microframes.
+ * and find a microframe where its worst bandwidth is minimum.
+ */
+ min_bw = ~0;
+ min_index = 0;
+ for (offset = 0; offset < esit; offset++) {
+ if ((offset + num_budget_microframes) > sch_ep->esit)
+ break;
+ /*
+ * usb_20 spec section11.18:
+ * must never schedule Start-Split in Y6
+ */
+ if (is_fs_or_ls(udev->speed) && (offset % 8 == 6))
+ continue;
+
+ worst_bw = get_max_bw(sch_bw, sch_ep, offset);
+ if (min_bw > worst_bw) {
+ min_bw = worst_bw;
+ min_index = offset;
+ }
+ if (min_bw == 0)
+ break;
+ }
+ sch_ep->offset = min_index;
+
+ debug_sch_ep(sch_ep);
+
+ bw_boundary = (udev->speed == USB_SPEED_SUPER)
+ ? SS_BW_BOUNDARY : HS_BW_BOUNDARY;
+
+ /* check bandwidth */
+ if (min_bw + sch_ep->bw_cost_per_microframe > bw_boundary)
+ return -1;
+
+ /* update bus bandwidth info */
+ update_bus_bw(sch_bw, sch_ep, sch_ep->bw_cost_per_microframe);
+
+ return 0;
+}
+
+static void debug_sch_bw(struct mu3h_sch_bw_info *sch_bw)
+{
+ int i;
+
+ pr_debug("%s: bus_bw_info\n", __func__);
+ for (i = 0; i < XHCI_MTK_MAX_ESIT; i++)
+ pr_debug("%d ", sch_bw->bus_bw[i]);
+
+ pr_debug("\n");
+}
+
+
+static bool need_bw_sch(struct usb_host_endpoint *ep,
+ enum usb_device_speed speed, int has_tt)
+{
+ /* only for periodic endpoints */
+ if (usb_endpoint_xfer_control(&ep->desc)
+ || usb_endpoint_xfer_bulk(&ep->desc))
+ return false;
+ /*
+ * for LS & FS periodic endpoints which its device don't attach
+ * to TT are also ignored, root-hub will schedule them directly
+ */
+ if (is_fs_or_ls(speed) && !has_tt)
+ return false;
+
+ return true;
+}
+
+static int xhci_mtk_sch_init(struct xhci_hcd *xhci)
+{
+ struct usb_hcd *hcd = xhci_to_hcd(xhci);
+ struct device *dev = hcd->self.controller;
+ struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
+ struct mu3h_sch_bw_info *sch_array;
+ int num_usb_bus;
+ int i;
+
+ /* ss IN and OUT are separated */
+ num_usb_bus = xhci->num_usb3_ports * 2 + xhci->num_usb2_ports;
+
+ sch_array = kcalloc(num_usb_bus, sizeof(*sch_array), GFP_KERNEL);
+ if (sch_array == NULL)
+ return -ENOMEM;
+
+ for (i = 0; i < num_usb_bus; i++)
+ INIT_LIST_HEAD(&sch_array[i].bw_ep_list);
+
+ mtk->sch_array = sch_array;
+
+ return 0;
+}
+
+
+static void xhci_mtk_sch_exit(struct xhci_hcd *xhci)
+{
+ struct usb_hcd *hcd = xhci_to_hcd(xhci);
+ struct device *dev = hcd->self.controller;
+ struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
+
+ kfree(mtk->sch_array);
+}
+
+
+int xhci_mtk_add_ep_quirk(struct usb_hcd *hcd, struct usb_device *udev,
+ struct usb_host_endpoint *ep)
+{
+ struct device *dev = hcd->self.controller;
+ struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
+
+ int ret = 0;
+ int port_id;
+ int bw_index;
+ struct xhci_hcd *xhci;
+ unsigned int ep_index;
+ struct xhci_ep_ctx *ep_ctx;
+ struct xhci_slot_ctx *slot_ctx;
+ struct xhci_virt_device *virt_dev;
+ struct mu3h_sch_bw_info *sch_bw;
+ struct mu3h_sch_ep_info *sch_ep;
+ struct mu3h_sch_bw_info *sch_array;
+
+ xhci = hcd_to_xhci(hcd);
+ virt_dev = xhci->devs[udev->slot_id];
+ ep_index = xhci_get_endpoint_index(&ep->desc);
+ slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
+ ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
+ sch_array = mtk->sch_array;
+
+ port_id = virt_dev->real_port;
+ xhci_dbg(xhci, "%s() xfer_type: %d, speed:%d, ep:%p\n", __func__,
+ usb_endpoint_type(&ep->desc), udev->speed, ep);
+
+ if (!need_bw_sch(ep, udev->speed, slot_ctx->tt_info & TT_SLOT))
+ return 0;
+
+ bw_index = get_bw_index(xhci, udev, ep);
+ sch_bw = &sch_array[bw_index];
+
+ sch_ep = kzalloc(sizeof(struct mu3h_sch_ep_info), GFP_NOIO);
+ if (!sch_ep)
+ return -ENOMEM;
+
+ setup_sch_info(udev, ep_ctx, sch_ep);
+
+ ret = check_sch_bw(udev, sch_bw, sch_ep);
+ if (ret) {
+ xhci_err(xhci, "Not enough bandwidth!\n");
+ kfree(sch_ep);
+ return -ENOSPC;
+ }
+
+ list_add_tail(&sch_ep->endpoint, &sch_bw->bw_ep_list);
+ sch_ep->ep = ep;
+
+ ep_ctx->reserved[0] |= cpu_to_le32(EP_BPKTS(sch_ep->pkts)
+ | EP_BCSCOUNT(sch_ep->cs_count) | EP_BBM(sch_ep->burst_mode));
+ ep_ctx->reserved[1] |= cpu_to_le32(EP_BOFFSET(sch_ep->offset)
+ | EP_BREPEAT(sch_ep->repeat));
+
+ debug_sch_bw(sch_bw);
+ return 0;
+}
+EXPORT_SYMBOL_GPL(xhci_mtk_add_ep_quirk);
+
+
+void xhci_mtk_drop_ep_quirk(struct usb_hcd *hcd, struct usb_device *udev,
+ struct usb_host_endpoint *ep)
+{
+ struct device *dev = hcd->self.controller;
+ struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
+
+ int bw_index;
+ struct xhci_hcd *xhci;
+ struct xhci_slot_ctx *slot_ctx;
+ struct xhci_virt_device *virt_dev;
+ struct mu3h_sch_bw_info *sch_array;
+ struct mu3h_sch_bw_info *sch_bw;
+ struct mu3h_sch_ep_info *sch_ep;
+
+ xhci = hcd_to_xhci(hcd);
+ virt_dev = xhci->devs[udev->slot_id];
+ slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
+ sch_array = mtk->sch_array;
+
+ xhci_dbg(xhci, "%s() xfer_type: %d, speed:%d, ep:%p\n", __func__,
+ usb_endpoint_type(&ep->desc), udev->speed, ep);
+
+ if (!need_bw_sch(ep, udev->speed, slot_ctx->tt_info & TT_SLOT))
+ return;
+
+ bw_index = get_bw_index(xhci, udev, ep);
+ sch_bw = &sch_array[bw_index];
+
+ list_for_each_entry(sch_ep, &sch_bw->bw_ep_list, endpoint) {
+ if (sch_ep->ep == ep) {
+ update_bus_bw(sch_bw, sch_ep,
+ -sch_ep->bw_cost_per_microframe);
+ list_del(&sch_ep->endpoint);
+ kfree(sch_ep);
+ break;
+ }
+ }
+ debug_sch_bw(sch_bw);
+}
+EXPORT_SYMBOL_GPL(xhci_mtk_drop_ep_quirk);
+
+
+/*
+ * The TD size is the number of max packet sized packets remaining in the TD
+ * (including this TRB), right shifted by 10.
+ * It must fit in bits 21:17, so it can't be bigger than 31.
+ */
+u32 xhci_mtk_td_remainder_quirk(unsigned int td_running_total,
+ unsigned trb_buffer_length, struct urb *urb)
+{
+ u32 max = 31;
+ int remainder, td_packet_count, packet_transferred;
+ unsigned int td_transfer_size = urb->transfer_buffer_length;
+ unsigned int maxp;
+
+ maxp = GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc));
+
+ /* 0 for the last TRB */
+ if (td_running_total + trb_buffer_length == td_transfer_size)
+ return 0;
+
+ packet_transferred = td_running_total / maxp;
+ td_packet_count = DIV_ROUND_UP(td_transfer_size, maxp);
+ remainder = td_packet_count - packet_transferred;
+
+ if (remainder > max)
+ return max << 17;
+ else
+ return remainder << 17;
+}
+EXPORT_SYMBOL_GPL(xhci_mtk_td_remainder_quirk);
+
+
+static int xhci_mtk_setup(struct usb_hcd *hcd);
+static const struct xhci_driver_overrides xhci_mtk_overrides __initconst = {
+ .extra_priv_size = sizeof(struct xhci_hcd),
+ .reset = xhci_mtk_setup,
+};
+
+static struct hc_driver __read_mostly xhci_mtk_hc_driver;
+
+
+static int xhci_mtk_ldos_enable(struct xhci_hcd_mtk *mtk)
+{
+ int ret;
+
+ ret = regulator_enable(mtk->vbus);
+ if (ret) {
+ dev_err(mtk->dev, "failed to enable vbus\n");
+ return ret;
+ }
+
+ ret = regulator_enable(mtk->vusb33);
+ if (ret) {
+ dev_err(mtk->dev, "failed to enable vusb33\n");
+ regulator_disable(mtk->vbus);
+ return ret;
+ }
+ return 0;
+}
+
+static void xhci_mtk_ldos_disable(struct xhci_hcd_mtk *mtk)
+{
+ regulator_disable(mtk->vbus);
+ regulator_disable(mtk->vusb33);
+}
+
+static void xhci_mtk_quirks(struct device *dev, struct xhci_hcd *xhci)
+{
+ /*
+ * As of now platform drivers don't provide MSI support so we ensure
+ * here that the generic code does not try to make a pci_dev from our
+ * dev struct in order to setup MSI
+ */
+ xhci->quirks |= XHCI_PLAT;
+ xhci->quirks |= XHCI_MTK_HOST;
+ /*
+ * MTK host controller gives a spurious successful event after a
+ * short transfer. Ignore it.
+ */
+ xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
+}
+
+/* called during probe() after chip reset completes */
+static int xhci_mtk_setup(struct usb_hcd *hcd)
+{
+ struct xhci_hcd *xhci;
+ int ret;
+
+ ret = xhci_gen_setup(hcd, xhci_mtk_quirks);
+ if (ret)
+ return ret;
+
+ if (!usb_hcd_is_primary_hcd(hcd))
+ return 0;
+
+ xhci = hcd_to_xhci(hcd);
+ ret = xhci_mtk_sch_init(xhci);
+ if (ret) {
+ kfree(xhci);
+ return ret;
+ }
+
+ return ret;
+}
+
+
+static int xhci_mtk_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *node = pdev->dev.of_node;
+ struct usb_xhci_pdata *pdata = dev_get_platdata(dev);
+ struct xhci_hcd_mtk *mtk;
+ const struct hc_driver *driver;
+ struct xhci_hcd *xhci;
+ struct resource *res;
+ struct usb_hcd *hcd;
+ int ret = -ENODEV;
+ int irq;
+
+ if (usb_disabled())
+ return -ENODEV;
+
+ driver = &xhci_mtk_hc_driver;
+ mtk = devm_kzalloc(dev, sizeof(*mtk), GFP_KERNEL);
+ if (!mtk)
+ return -ENOMEM;
+ mtk->dev = dev;
+
+ mtk->sys_mac = devm_clk_get(dev, "sys_mac");
+ if (IS_ERR(mtk->sys_mac)) {
+ dev_err(dev, "error to get sys_mac\n");
+ ret = PTR_ERR(mtk->sys_mac);
+ goto err;
+ }
+
+ mtk->vbus = devm_regulator_get(dev, "reg-vbus");
+ if (IS_ERR(mtk->vbus)) {
+ dev_err(dev, "fail to get vbus\n");
+ ret = PTR_ERR(mtk->vbus);
+ goto err;
+ }
+
+ mtk->vusb33 = devm_regulator_get(dev, "reg-vusb33");
+ if (IS_ERR(mtk->vusb33)) {
+ dev_err(dev, "fail to get vusb33\n");
+ ret = PTR_ERR(mtk->vusb33);
+ goto err;
+ }
+ pm_runtime_enable(dev);
+ pm_runtime_get_sync(dev);
+
+ ret = xhci_mtk_ldos_enable(mtk);
+ if (ret)
+ goto disable_pm;
+
+ ret = clk_prepare_enable(mtk->sys_mac);
+ if (ret)
+ goto disable_ldos;
+
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0)
+ goto disable_clk;
+
+ /* Initialize dma_mask and coherent_dma_mask to 32-bits */
+ ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
+ if (ret)
+ goto disable_clk;
+
+ if (!dev->dma_mask)
+ dev->dma_mask = &dev->coherent_dma_mask;
+ else
+ dma_set_mask(dev, DMA_BIT_MASK(32));
+
+ hcd = usb_create_hcd(driver, dev, dev_name(dev));
+ if (!hcd) {
+ ret = -ENOMEM;
+ goto disable_clk;
+ }
+
+ /*
+ * USB 2.0 roothub is stored in the platform_device.
+ * Swap it with mtk HCD.
+ */
+ mtk->hcd = platform_get_drvdata(pdev);
+ platform_set_drvdata(pdev, mtk);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ hcd->regs = devm_ioremap_resource(dev, res);
+ if (IS_ERR(hcd->regs)) {
+ ret = PTR_ERR(hcd->regs);
+ goto put_usb2_hcd;
+ }
+ hcd->rsrc_start = res->start;
+ hcd->rsrc_len = resource_size(res);
+
+ hcd->usb_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
+ if (IS_ERR(hcd->usb_phy)) {
+ ret = PTR_ERR(hcd->usb_phy);
+ if (ret == -EPROBE_DEFER)
+ goto put_usb2_hcd;
+ hcd->usb_phy = NULL;
+ } else {
+ ret = usb_phy_init(hcd->usb_phy);
+ if (ret)
+ goto put_usb2_hcd;
+ }
+
+ device_wakeup_enable(hcd->self.controller);
+
+ xhci = hcd_to_xhci(hcd);
+ xhci->main_hcd = hcd;
+ xhci->shared_hcd = usb_create_shared_hcd(driver, dev,
+ dev_name(dev), hcd);
+ if (!xhci->shared_hcd) {
+ ret = -ENOMEM;
+ goto disable_usb_phy;
+ }
+
+ if ((node && of_property_read_bool(node, "usb3-lpm-capable")) ||
+ (pdata && pdata->usb3_lpm_capable))
+ xhci->quirks |= XHCI_LPM_SUPPORT;
+
+ if (HCC_MAX_PSA(xhci->hcc_params) >= 4)
+ xhci->shared_hcd->can_do_streams = 1;
+
+ ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
+ if (ret)
+ goto put_usb3_hcd;
+
+ ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED);
+ if (ret)
+ goto dealloc_usb2_hcd;
+
+ return 0;
+
+
+dealloc_usb2_hcd:
+ usb_remove_hcd(hcd);
+
+put_usb3_hcd:
+ usb_put_hcd(xhci->shared_hcd);
+
+disable_usb_phy:
+ usb_phy_shutdown(hcd->usb_phy);
+
+put_usb2_hcd:
+ usb_put_hcd(hcd);
+
+disable_clk:
+ clk_disable_unprepare(mtk->sys_mac);
+
+disable_ldos:
+ xhci_mtk_ldos_disable(mtk);
+
+disable_pm:
+ pm_runtime_put_sync(dev);
+ pm_runtime_disable(dev);
+
+err:
+ return ret;
+}
+
+static int xhci_mtk_remove(struct platform_device *dev)
+{
+ struct xhci_hcd_mtk *mtk = platform_get_drvdata(dev);
+ struct usb_hcd *hcd = mtk->hcd;
+ struct xhci_hcd *xhci = hcd_to_xhci(hcd);
+
+ usb_remove_hcd(xhci->shared_hcd);
+ usb_phy_shutdown(hcd->usb_phy);
+
+ usb_remove_hcd(hcd);
+ usb_put_hcd(xhci->shared_hcd);
+ usb_put_hcd(hcd);
+ xhci_mtk_sch_exit(xhci);
+ clk_disable_unprepare(mtk->sys_mac);
+ xhci_mtk_ldos_disable(mtk);
+ pm_runtime_put_sync(&dev->dev);
+ pm_runtime_disable(&dev->dev);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int xhci_mtk_suspend(struct device *dev)
+{
+ struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
+ struct usb_hcd *hcd = mtk->hcd;
+ int ret;
+
+ ret = usb_phy_set_suspend(hcd->usb_phy, 1);
+ /* keep on power of mac to maintain register, and only close clock */
+ clk_disable_unprepare(mtk->sys_mac);
+ return ret;
+}
+
+static int xhci_mtk_resume(struct device *dev)
+{
+ struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
+ struct usb_hcd *hcd = mtk->hcd;
+ int ret;
+
+ clk_prepare_enable(mtk->sys_mac);
+ ret = usb_phy_set_suspend(hcd->usb_phy, 0);
+
+ return ret;
+}
+
+static const struct dev_pm_ops xhci_mtk_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(xhci_mtk_suspend, xhci_mtk_resume)
+};
+#define DEV_PM_OPS (&xhci_mtk_pm_ops)
+#else
+#define DEV_PM_OPS NULL
+#endif /* CONFIG_PM */
+
+#ifdef CONFIG_OF
+static const struct of_device_id mtk_xhci_of_match[] = {
+ { .compatible = "mediatek,mt8173-xhci"},
+ { },
+};
+MODULE_DEVICE_TABLE(of, mtk_xhci_of_match);
+#endif
+
+static struct platform_driver mtk_xhci_driver = {
+ .probe = xhci_mtk_probe,
+ .remove = xhci_mtk_remove,
+ .driver = {
+ .name = "xhci-mtk",
+ .pm = DEV_PM_OPS,
+ .of_match_table = of_match_ptr(mtk_xhci_of_match),
+ },
+};
+
+static int __init xhci_mtk_init(void)
+{
+ xhci_init_driver(&xhci_mtk_hc_driver, &xhci_mtk_overrides);
+ return platform_driver_register(&mtk_xhci_driver);
+}
+module_init(xhci_mtk_init);
+
+static void __exit xhci_mtk_exit(void)
+{
+ platform_driver_unregister(&mtk_xhci_driver);
+}
+module_exit(xhci_mtk_exit);
+
+MODULE_DESCRIPTION("MediaTek xHCI Host Controller Driver");
+MODULE_LICENSE("GPL v2");
+
diff --git a/drivers/usb/host/xhci-mtk.h b/drivers/usb/host/xhci-mtk.h
new file mode 100644
index 0000000..e0fdd19
--- /dev/null
+++ b/drivers/usb/host/xhci-mtk.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2015 MediaTek Inc.
+ * Author:
+ * Zhigang.Wei <zhigang.wei@mediatek.com>
+ * Chunfeng.Yun <chunfeng.yun@mediatek.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _XHCI_MTK_H_
+#define _XHCI_MTK_H_
+
+#include "xhci.h"
+
+/**
+ * To simplify scheduler algorithm, set a upper limit for ESIT,
+ * if a synchromous ep's ESIT is larger than @XHCI_MTK_MAX_ESIT,
+ * round down to the limit value, that means allocating more
+ * bandwidth to it.
+ */
+#define XHCI_MTK_MAX_ESIT 64
+
+/**
+ * struct mu3h_sch_bw_info
+ * @bus_bw: array to keep track of bandwidth already used at each uframes
+ * @bw_ep_list: eps in the bandwidth domain
+ *
+ * treat a HS root port as a bandwidth domain, but treat a SS root port as
+ * two bandwidth domains, one for IN eps and another for OUT eps.
+ */
+struct mu3h_sch_bw_info {
+ u32 bus_bw[XHCI_MTK_MAX_ESIT];
+ struct list_head bw_ep_list;
+};
+
+/**
+ * struct mu3h_sch_ep_info
+ * @esit: unit is 125us, equal to 2 << Interval field in ep-context
+ * @num_budget_microframes: number of continuous uframes
+ * (@repeat==1) scheduled within the interval
+ * @ep: address of usb_host_endpoint
+ * @offset: which uframe of the interval that transfer should be
+ * scheduled first time within the interval
+ * @repeat: the time gap between two uframes that transfers are
+ * scheduled within a interval. in the simple algorithm, only
+ * assign 0 or 1 to it; 0 means using only one uframe in a
+ * interval, and1 means using @num_budget_microframes
+ * continuous uframes
+ * @pkts: number of packets to be transferred in the scheduled uframes
+ * @cs_count: number of CS that host will trigger
+ */
+struct mu3h_sch_ep_info {
+ u32 ep_type;
+ u32 max_packet_size;
+ u32 esit;
+ u32 num_budget_microframes;
+ u32 bw_cost_per_microframe;
+ void *ep;
+ struct list_head endpoint;
+
+ /* mtk xhci scheduling info */
+ u32 offset;
+ u32 repeat;
+ u32 pkts;
+ u32 cs_count;
+ u32 burst_mode;
+};
+
+
+#if IS_ENABLED(CONFIG_USB_XHCI_MTK)
+
+int xhci_mtk_add_ep_quirk(struct usb_hcd *hcd, struct usb_device *udev,
+ struct usb_host_endpoint *ep);
+void xhci_mtk_drop_ep_quirk(struct usb_hcd *hcd, struct usb_device *udev,
+ struct usb_host_endpoint *ep);
+u32 xhci_mtk_td_remainder_quirk(unsigned int td_running_total,
+ unsigned trb_buffer_length, struct urb *urb);
+
+#else
+static inline int xhci_mtk_add_ep_quirk(struct usb_hcd *hcd,
+ struct usb_device *udev, struct usb_host_endpoint *ep)
+{
+ return 0;
+}
+
+static inline void xhci_mtk_drop_ep_quirk(struct usb_hcd *hcd,
+ struct usb_device *udev, struct usb_host_endpoint *ep)
+{
+ return 0;
+}
+
+static inline u32 xhci_mtk_td_remainder_quirk(unsigned int td_running_total,
+ unsigned trb_buffer_length, struct urb *urb)
+{
+ return 0;
+}
+
+#endif
+
+#endif /* _XHCI_MTK_H_ */
diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
index 94416ff..73997a0 100644
--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c
@@ -68,6 +68,7 @@
#include <linux/slab.h>
#include "xhci.h"
#include "xhci-trace.h"
+#include "xhci-mtk.h"
/*
* Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
@@ -3131,9 +3132,14 @@ static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
/* Set the TRB length, TD size, and interrupter fields. */
if (xhci->hci_version < 0x100) {
- remainder = xhci_td_remainder(
+ if (xhci->quirks & XHCI_MTK_HOST) {
+ remainder = xhci_mtk_td_remainder_quirk(
+ running_total, trb_buff_len, urb);
+ } else {
+ remainder = xhci_td_remainder(
urb->transfer_buffer_length -
running_total);
+ }
} else {
remainder = xhci_v1_0_td_remainder(running_total,
trb_buff_len, total_packet_count, urb,
@@ -3286,9 +3292,14 @@ int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
/* Set the TRB length, TD size, and interrupter fields. */
if (xhci->hci_version < 0x100) {
- remainder = xhci_td_remainder(
+ if (xhci->quirks & XHCI_MTK_HOST) {
+ remainder = xhci_mtk_td_remainder_quirk(
+ running_total, trb_buff_len, urb);
+ } else {
+ remainder = xhci_td_remainder(
urb->transfer_buffer_length -
running_total);
+ }
} else {
remainder = xhci_v1_0_td_remainder(running_total,
trb_buff_len, total_packet_count, urb,
@@ -3383,7 +3394,7 @@ int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
field |= 0x1;
/* xHCI 1.0 6.4.1.2.1: Transfer Type field */
- if (xhci->hci_version == 0x100) {
+ if ((xhci->hci_version == 0x100) || (xhci->quirks & XHCI_MTK_HOST)) {
if (urb->transfer_buffer_length > 0) {
if (setup->bRequestType & USB_DIR_IN)
field |= TRB_TX_TYPE(TRB_DATA_IN);
@@ -3407,8 +3418,14 @@ int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
field = TRB_TYPE(TRB_DATA);
length_field = TRB_LEN(urb->transfer_buffer_length) |
- xhci_td_remainder(urb->transfer_buffer_length) |
TRB_INTR_TARGET(0);
+
+ if (xhci->quirks & XHCI_MTK_HOST)
+ length_field |= xhci_mtk_td_remainder_quirk(0,
+ urb->transfer_buffer_length, urb);
+ else
+ length_field |= xhci_td_remainder(urb->transfer_buffer_length);
+
if (urb->transfer_buffer_length > 0) {
if (setup->bRequestType & USB_DIR_IN)
field |= TRB_DIR_IN;
@@ -3632,8 +3649,14 @@ static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
/* Set the TRB length, TD size, & interrupter fields. */
if (xhci->hci_version < 0x100) {
- remainder = xhci_td_remainder(
- td_len - running_total);
+ if (xhci->quirks & XHCI_MTK_HOST) {
+ remainder = xhci_mtk_td_remainder_quirk(
+ running_total, trb_buff_len,
+ urb);
+ } else {
+ remainder = xhci_td_remainder(
+ td_len - running_total);
+ }
} else {
remainder = xhci_v1_0_td_remainder(
running_total, trb_buff_len,
diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
index 7da0d60..209fc8a 100644
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -31,6 +31,7 @@
#include "xhci.h"
#include "xhci-trace.h"
+#include "xhci-mtk.h"
#define DRIVER_AUTHOR "Sarah Sharp"
#define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
@@ -623,7 +624,11 @@ int xhci_run(struct usb_hcd *hcd)
"// Set the interrupt modulation register");
temp = readl(&xhci->ir_set->irq_control);
temp &= ~ER_IRQ_INTERVAL_MASK;
- temp |= (u32) 160;
+ /*
+ * the increment interval is 8 times as much as that defined
+ * in xHCI spec on MTK's controller
+ */
+ temp |= (u32) ((xhci->quirks & XHCI_MTK_HOST) ? 20 : 160);
writel(temp, &xhci->ir_set->irq_control);
/* Set the HCD state before we enable the irqs */
@@ -1688,6 +1693,9 @@ int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
+ if (xhci->quirks & XHCI_MTK_HOST)
+ xhci_mtk_drop_ep_quirk(hcd, udev, ep);
+
xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
(unsigned int) ep->desc.bEndpointAddress,
udev->slot_id,
@@ -1783,6 +1791,15 @@ int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
return -ENOMEM;
}
+ if (xhci->quirks & XHCI_MTK_HOST) {
+ ret = xhci_mtk_add_ep_quirk(hcd, udev, ep);
+ if (ret < 0) {
+ xhci_free_or_cache_endpoint_ring(xhci,
+ virt_dev, ep_index);
+ return ret;
+ }
+ }
+
ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
index 31e46cc..d257ce3 100644
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
@@ -1567,6 +1567,7 @@ struct xhci_hcd {
/* For controllers with a broken beyond repair streams implementation */
#define XHCI_BROKEN_STREAMS (1 << 19)
#define XHCI_PME_STUCK_QUIRK (1 << 20)
+#define XHCI_MTK_HOST (1 << 21)
unsigned int num_active_eps;
unsigned int limit_active_eps;
/* There are two roothubs to keep track of bus suspend info for */
--
1.8.1.1.dirty
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v2 5/5] arm64: dts: mediatek: add xHCI & usb phy for mt8173
2015-07-08 9:41 [PATCH v2 0/5] Mediatek xHCI support Chunfeng Yun
` (3 preceding siblings ...)
2015-07-08 9:41 ` [PATCH v2 4/5] xhci: mediatek: support MTK xHCI host controller Chunfeng Yun
@ 2015-07-08 9:41 ` Chunfeng Yun
2015-07-14 10:12 ` Daniel Kurtz
4 siblings, 1 reply; 22+ messages in thread
From: Chunfeng Yun @ 2015-07-08 9:41 UTC (permalink / raw)
To: Mathias Nyman
Cc: Rob Herring, Mark Rutland, Matthias Brugger, Felipe Balbi,
Chunfeng Yun, Sascha Hauer, devicetree, linux-kernel,
linux-arm-kernel, Roger Quadros, linux-usb, linux-mediatek
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 15 +++++++++++++++
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 27 +++++++++++++++++++++++++++
2 files changed, 42 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
index f433c21..cb63dc3 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
@@ -13,6 +13,7 @@
*/
/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
#include "mt8173.dtsi"
/ {
@@ -32,6 +33,15 @@
};
chosen { };
+
+ usb_p1_vbus: fixedregulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&pio 130 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
};
&pwrap {
@@ -211,3 +221,8 @@
&uart0 {
status = "okay";
};
+
+&usb {
+ reg-vusb33-supply = <&mt6397_vusb_reg>;
+ reg-vbus-supply = <&usb_p1_vbus>;
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 0696f8f..452bd0a 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -15,6 +15,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset-controller/mt8173-resets.h>
+#include <dt-bindings/power/mt8173-power.h>
#include "mt8173-pinfunc.h"
/ {
@@ -393,6 +394,32 @@
#size-cells = <0>;
status = "disabled";
};
+
+ usb: usb30@11270000 {
+ compatible = "mediatek,mt8173-xhci";
+ reg = <0 0x11270000 0 0x1000>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
+ usb-phy = <&u3phy>;
+ usb3-lpm-capable;
+ clocks = <&topckgen CLK_TOP_USB30_SEL>;
+ clock-names = "sys_mac";
+ };
+
+ u3phy: usb-phy@11271000 {
+ compatible = "mediatek,mt8173-u3phy";
+ reg = <0 0x11271000 0 0x3000>,
+ <0 0x11280000 0 0x20000>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
+ usb-wakeup-ctrl = <&pericfg>;
+ wakeup-src = <1>;
+ u2port-num = <2>;
+ clocks = <&pericfg CLK_PERI_USB0>,
+ <&pericfg CLK_PERI_USB1>,
+ <&apmixedsys CLK_APMIXED_REF2USB_TX>;
+ clock-names = "wakeup_deb_p0",
+ "wakeup_deb_p1",
+ "u3phya_ref";
+ };
};
};
--
1.8.1.1.dirty
^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [PATCH v2 1/5] dt-bindings: Add usb3.0 phy binding for MT65xx SoCs
2015-07-08 9:41 ` [PATCH v2 1/5] dt-bindings: Add usb3.0 phy binding for MT65xx SoCs Chunfeng Yun
@ 2015-07-10 5:10 ` Sascha Hauer
2015-07-14 6:19 ` chunfeng yun
0 siblings, 1 reply; 22+ messages in thread
From: Sascha Hauer @ 2015-07-10 5:10 UTC (permalink / raw)
To: Chunfeng Yun
Cc: Mathias Nyman, Rob Herring, Mark Rutland, Matthias Brugger,
Felipe Balbi, devicetree, linux-kernel, linux-arm-kernel,
Roger Quadros, linux-usb, linux-mediatek
On Wed, Jul 08, 2015 at 05:41:03PM +0800, Chunfeng Yun wrote:
> add a DT binding documentation of usb3.0 phy for MT65xx
> SoCs from Mediatek.
>
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> ---
> .../devicetree/bindings/usb/mt65xx-u3phy.txt | 34 ++++++++++++++++++++++
> 1 file changed, 34 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/usb/mt65xx-u3phy.txt
>
> diff --git a/Documentation/devicetree/bindings/usb/mt65xx-u3phy.txt b/Documentation/devicetree/bindings/usb/mt65xx-u3phy.txt
> new file mode 100644
> index 0000000..056b2aa
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/mt65xx-u3phy.txt
> @@ -0,0 +1,34 @@
> +MT65xx U3PHY
> +
> +The device node for Mediatek SOC usb3.0 phy
> +
> +Required properties:
> + - compatible : Should be "mediatek,mt8173-u3phy"
> + - reg : Offset and length of registers, the first is for mac domain,
> + another for phy domain
> + - power-domains: to enable usb's mtcmos
> + - usb-wakeup-ctrl : to access usb wakeup control register
> + - wakeup-src : 1: ip sleep wakeup mode; 2: line state wakeup mode; others
> + means don't enable wakeup source of usb
> + - u2port-num : number of usb2.0 ports to support which should be 1 or 2
> + - clocks : must support all clocks that phy need
> + - clock-names: should be "wakeup_deb_p0", "wakeup_deb_p1" for wakeup
> + debounce control clocks, and "u3phya_ref" for u3phya reference clock.
> +
> +Example:
> +
> +u3phy: usb-phy@11271000 {
> + compatible = "mediatek,mt8173-u3phy";
> + reg = <0 0x11271000 0 0x3000>,
> + <0 0x11280000 0 0x20000>;
0x11271000 is the register space the xhci controller takes. You should
not expose the same register space to two different drivers.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v2 3/5] usb: phy: add usb3.0 phy driver for mt65xx SoCs
2015-07-08 9:41 ` [PATCH v2 3/5] usb: phy: add usb3.0 phy driver for mt65xx SoCs Chunfeng Yun
@ 2015-07-10 6:42 ` Sascha Hauer
2015-07-20 15:41 ` chunfeng yun
0 siblings, 1 reply; 22+ messages in thread
From: Sascha Hauer @ 2015-07-10 6:42 UTC (permalink / raw)
To: Chunfeng Yun
Cc: Mathias Nyman, Rob Herring, Mark Rutland, Matthias Brugger,
Felipe Balbi, devicetree, linux-kernel, linux-arm-kernel,
Roger Quadros, linux-usb, linux-mediatek
On Wed, Jul 08, 2015 at 05:41:05PM +0800, Chunfeng Yun wrote:
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> ---
> drivers/usb/phy/Kconfig | 10 +
> drivers/usb/phy/Makefile | 1 +
> drivers/usb/phy/phy-mt65xx-usb3.c | 856 ++++++++++++++++++++++++++++++++++++++
> 3 files changed, 867 insertions(+)
> create mode 100644 drivers/usb/phy/phy-mt65xx-usb3.c
>
> diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
> index 869c0cfcad..66ded00 100644
> --- a/drivers/usb/phy/Kconfig
> +++ b/drivers/usb/phy/Kconfig
> @@ -152,6 +152,16 @@ config USB_MSM_OTG
> This driver is not supported on boards like trout which
> has an external PHY.
>
> +config USB_MT65XX_USB3_PHY
> + tristate "Mediatek USB3.0 PHY controller Driver"
> + depends on ARCH_MEDIATEK || COMPILE_TEST
> + select USB_PHY
> + help
> + Say 'Y' here to add support for Mediatek USB3.0 PHY driver
> + for mt65xx SoCs. it supports two usb2.0 ports and
> + one usb3.0 port.
> + To compile this driver as a module, choose M here
> +
> config USB_MV_OTG
> tristate "Marvell USB OTG support"
> depends on USB_EHCI_MV && USB_MV_UDC && PM
> diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
> index e36ab1d..414ef57 100644
> --- a/drivers/usb/phy/Makefile
> +++ b/drivers/usb/phy/Makefile
> @@ -20,6 +20,7 @@ obj-$(CONFIG_USB_EHCI_TEGRA) += phy-tegra-usb.o
> obj-$(CONFIG_USB_GPIO_VBUS) += phy-gpio-vbus-usb.o
> obj-$(CONFIG_USB_ISP1301) += phy-isp1301.o
> obj-$(CONFIG_USB_MSM_OTG) += phy-msm-usb.o
> +obj-$(CONFIG_USB_MT65XX_USB3_PHY) += phy-mt65xx-usb3.o
> obj-$(CONFIG_USB_MV_OTG) += phy-mv-usb.o
> obj-$(CONFIG_USB_MXS_PHY) += phy-mxs-usb.o
> obj-$(CONFIG_USB_RCAR_PHY) += phy-rcar-usb.o
> diff --git a/drivers/usb/phy/phy-mt65xx-usb3.c b/drivers/usb/phy/phy-mt65xx-usb3.c
> new file mode 100644
> index 0000000..38ee6f3
> --- /dev/null
> +++ b/drivers/usb/phy/phy-mt65xx-usb3.c
> @@ -0,0 +1,856 @@
> +/*
> + * Copyright (c) 2015 MediaTek Inc.
> + * Author: Chunfeng.Yun <chunfeng.yun@mediatek.com>
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/err.h>
> +#include <linux/export.h>
> +#include <linux/gpio.h>
> +#include <linux/io.h>
> +#include <linux/iopoll.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/of_address.h>
> +#include <linux/of_device.h>
> +#include <linux/of_gpio.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/regmap.h>
> +#include <linux/regulator/consumer.h>
> +#include <linux/resource.h>
> +#include <linux/slab.h>
> +#include <linux/usb/of.h>
> +#include <linux/usb/otg.h>
> +#include <linux/usb/phy.h>
> +
> +/*
> + * relative to MAC base address
> + */
> +#define SSUSB_USB3_MAC_CSR_BASE (0x1400)
> +#define SSUSB_USB3_SYS_CSR_BASE (0x1400)
> +#define SSUSB_USB2_CSR_BASE (0x2400)
Please drop the unnecessary braces.
> +
> +/*
> + * for sifslv1 register
> + * relative to USB3_SIF_BASE base address
> + */
> +#define SSUSB_SIFSLV_IPPC_BASE (0x700)
> +
> +/*
> + * for sifslv2 register
> + * relative to USB3_SIF_BASE base address
> + */
> +#define SSUSB_SIFSLV_U2PHY_COM_BASE (0x10800)
> +#define SSUSB_SIFSLV_U3PHYD_BASE (0x10900)
> +#define SSUSB_SIFSLV_U2FREQ_BASE (0x10f00)
> +#define SSUSB_USB30_PHYA_SIV_B_BASE (0x10b00)
> +#define SSUSB_SIFSLV_U3PHYA_DA_BASE (0x10c00)
> +#define SSUSB_SIFSLV_SPLLC (0x10000)
> +
> +/*port1 refs. +0x800(refer to port0)*/
> +#define U3P_PORT_OFFSET (0x800) /*based on port0 */
> +#define U3P_PHY_BASE(index) ((U3P_PORT_OFFSET) * (index))
According to my datasheet port(idx) base is at:
sif_base + 0x800 + 0x100 * idx
Am I missing something here?
> +
> +#define U3P_IP_PW_CTRL0 (SSUSB_SIFSLV_IPPC_BASE + 0x0000)
> +#define CTRL0_IP_SW_RST (0x1 << 0)
> +
> +#define U3P_IP_PW_CTRL1 (SSUSB_SIFSLV_IPPC_BASE + 0x0004)
> +#define CTRL1_IP_HOST_PDN (0x1 << 0)
> +
> +#define U3P_IP_PW_CTRL2 (SSUSB_SIFSLV_IPPC_BASE + 0x0008)
> +#define CTRL2_IP_DEV_PDN (0x1 << 0)
> +
> +#define U3P_IP_PW_STS1 (SSUSB_SIFSLV_IPPC_BASE + 0x0010)
> +#define STS1_IP_SLEEP_STS (0x1 << 30)
> +#define STS1_U3_MAC_RST (0x1 << 16)
> +#define STS1_SYS125_RST (0x1 << 10)
> +#define STS1_REF_RST (0x1 << 8)
> +#define STS1_SYSPLL_STABLE (0x1 << 0)
> +
> +#define U3P_IP_PW_STS2 (SSUSB_SIFSLV_IPPC_BASE + 0x0014)
> +#define STS2_U2_MAC_RST (0x1 << 0)
> +
> +#define U3P_IP_XHCI_CAP (SSUSB_SIFSLV_IPPC_BASE + 0x0024)
> +#define CAP_U3_PORT_NUM(p) ((p) & 0xff)
> +#define CAP_U2_PORT_NUM(p) (((p) >> 8) & 0xff)
> +
> +#define U3P_U3_CTRL_0P (SSUSB_SIFSLV_IPPC_BASE + 0x0030)
> +#define CTRL_U3_PORT_HOST_SEL (0x1 << 2)
> +#define CTRL_U3_PORT_PDN (0x1 << 1)
> +#define CTRL_U3_PORT_DIS (0x1 << 0)
> +
> +#define U3P_U2_CTRL_0P (SSUSB_SIFSLV_IPPC_BASE + 0x0050)
> +#define CTRL_U2_PORT_HOST_SEL (0x1 << 2)
> +#define CTRL_U2_PORT_PDN (0x1 << 1)
> +#define CTRL_U2_PORT_DIS (0x1 << 0)
> +
> +#define U3P_U3_CTRL(p) (U3P_U3_CTRL_0P + ((p) * 0x08))
> +#define U3P_U2_CTRL(p) (U3P_U2_CTRL_0P + ((p) * 0x08))
> +
> +#define U3P_USBPHYACR0 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0000)
> +#define PA0_RG_U2PLL_FORCE_ON (0x1 << 15)
> +
> +#define U3P_USBPHYACR2 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0008)
> +#define PA2_RG_SIF_U2PLL_FORCE_EN (0x1 << 18)
> +
> +#define U3P_USBPHYACR5 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0014)
> +#define PA5_RG_U2_HSTX_SRCTRL (0x7 << 12)
> +#define PA5_RG_U2_HSTX_SRCTRL_VAL(x) ((0x7 & (x)) << 12)
> +#define PA5_RG_U2_HS_100U_U3_EN (0x1 << 11)
> +
> +#define U3P_USBPHYACR6 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0018)
> +#define PA6_RG_U2_ISO_EN (0x1 << 31)
> +#define PA6_RG_U2_BC11_SW_EN (0x1 << 23)
> +#define PA6_RG_U2_OTG_VBUSCMP_EN (0x1 << 20)
> +
> +#define U3P_U2PHYACR4 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0020)
> +#define P2C_RG_USB20_GPIO_CTL (0x1 << 9)
> +#define P2C_USB20_GPIO_MODE (0x1 << 8)
> +#define P2C_U2_GPIO_CTR_MSK (P2C_RG_USB20_GPIO_CTL | P2C_USB20_GPIO_MODE)
> +
> +#define U3D_U2PHYDCR0 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0060)
> +#define P2C_RG_SIF_U2PLL_FORCE_ON (0x1 << 24)
> +
> +#define U3P_U2PHYDTM0 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0068)
> +#define P2C_FORCE_UART_EN (0x1 << 26)
> +#define P2C_FORCE_DATAIN (0x1 << 23)
> +#define P2C_FORCE_DM_PULLDOWN (0x1 << 21)
> +#define P2C_FORCE_DP_PULLDOWN (0x1 << 20)
> +#define P2C_FORCE_XCVRSEL (0x1 << 19)
> +#define P2C_FORCE_SUSPENDM (0x1 << 18)
> +#define P2C_FORCE_TERMSEL (0x1 << 17)
> +#define P2C_RG_DATAIN (0xf << 10)
> +#define P2C_RG_DATAIN_VAL(x) ((0xf & (x)) << 10)
> +#define P2C_RG_DMPULLDOWN (0x1 << 7)
> +#define P2C_RG_DPPULLDOWN (0x1 << 6)
> +#define P2C_RG_XCVRSEL (0x3 << 4)
> +#define P2C_RG_XCVRSEL_VAL(x) ((0x3 & (x)) << 4)
> +#define P2C_RG_SUSPENDM (0x1 << 3)
> +#define P2C_RG_TERMSEL (0x1 << 2)
> +#define P2C_DTM0_PART_MASK \
> + (P2C_FORCE_DATAIN | P2C_FORCE_DM_PULLDOWN | \
> + P2C_FORCE_DP_PULLDOWN | P2C_FORCE_XCVRSEL | \
> + P2C_FORCE_TERMSEL | P2C_RG_DMPULLDOWN | \
> + P2C_RG_DPPULLDOWN | P2C_RG_TERMSEL)
> +
> +#define U3P_U2PHYDTM1 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x006C)
> +#define P2C_RG_UART_EN (0x1 << 16)
> +#define P2C_RG_VBUSVALID (0x1 << 5)
> +#define P2C_RG_SESSEND (0x1 << 4)
> +#define P2C_RG_AVALID (0x1 << 2)
> +
> +#define U3P_U3_PHYA_REG0 (SSUSB_USB30_PHYA_SIV_B_BASE + 0x0000)
> +#define P3A_RG_U3_VUSB10_ON (1 << 5)
> +
> +#define U3P_U3_PHYA_REG6 (SSUSB_USB30_PHYA_SIV_B_BASE + 0x0018)
> +#define P3A_RG_TX_EIDLE_CM (0xf << 28)
> +#define P3A_RG_TX_EIDLE_CM_VAL(x) ((0xf & (x)) << 28)
> +
> +#define U3P_U3_PHYA_REG9 (SSUSB_USB30_PHYA_SIV_B_BASE + 0x0024)
> +#define P3A_RG_RX_DAC_MUX (0x1f << 1)
> +#define P3A_RG_RX_DAC_MUX_VAL(x) ((0x1f & (x)) << 1)
> +
> +#define U3P_U3PHYA_DA_REG0 (SSUSB_SIFSLV_U3PHYA_DA_BASE + 0x0)
> +#define P3A_RG_XTAL_EXT_EN_U3 (0x3 << 10)
> +#define P3A_RG_XTAL_EXT_EN_U3_VAL(x) ((0x3 & (x)) << 10)
> +
> +#define U3P_PHYD_CDR1 (SSUSB_SIFSLV_U3PHYD_BASE + 0x5c)
> +#define P3D_RG_CDR_BIR_LTD1 (0x1f << 24)
> +#define P3D_RG_CDR_BIR_LTD1_VAL(x) ((0x1f & (x)) << 24)
> +#define P3D_RG_CDR_BIR_LTD0 (0x1f << 8)
> +#define P3D_RG_CDR_BIR_LTD0_VAL(x) ((0x1f & (x)) << 8)
> +
> +#define U3P_XTALCTL3 (SSUSB_SIFSLV_SPLLC + 0x18)
> +#define XC3_RG_U3_XTAL_RX_PWD (0x1 << 9)
> +#define XC3_RG_U3_FRC_XTAL_RX_PWD (0x1 << 8)
> +
> +#define U3P_UX_EXIT_LFPS_PARAM (SSUSB_USB3_MAC_CSR_BASE + 0x00A0)
> +#define RX_UX_EXIT_REF (0xff << 8)
> +#define RX_UX_EXIT_REF_VAL (0x3 << 8)
> +
> +#define U3P_REF_CLK_PARAM (SSUSB_USB3_MAC_CSR_BASE + 0x00B0)
> +#define REF_CLK_1000NS (0xff << 0)
> +#define REF_CLK_VAL_DEF (0xa << 0)
> +
> +#define U3P_LINK_PM_TIMER (SSUSB_USB3_SYS_CSR_BASE + 0x0208)
> +#define PM_LC_TIMEOUT (0xf << 0)
> +#define PM_LC_TIMEOUT_VAL (0x3 << 0)
> +
> +#define U3P_TIMING_PULSE_CTRL (SSUSB_USB3_SYS_CSR_BASE + 0x02B4)
> +#define U3T_CNT_1US (0xff << 0)
> +#define U3T_CNT_1US_VAL (0x3f << 0) /* 62.5MHz: 63 */
> +
> +#define U3P_U2_TIMING_PARAM (SSUSB_USB2_CSR_BASE + 0x0040)
> +#define U2T_VAL_1US (0xff << 0)
> +#define U2T_VAL_1US_VAL (0x3f << 0) /* 62.5MHz: 63 */
> +
> +
> +#define PERI_WK_CTRL0 0x400
> +#define UWK_CTL1_1P_LS_E (0x1 << 0)
> +#define UWK_CTL1_1P_LS_C(x) (((x) & 0xf) << 1)
> +#define UWK_CTR0_0P_LS_NE (0x1 << 7) /* negedge for 0p linestate*/
> +#define UWK_CTR0_0P_LS_PE (0x1 << 8) /* posedge */
> +
> +#define PERI_WK_CTRL1 0x404
> +#define UWK_CTL1_IS_P (0x1 << 6) /* polarity for ip sleep */
> +#define UWK_CTL1_0P_LS_P (0x1 << 7)
> +#define UWK_CTL1_IDDIG_P (0x1 << 9) /* polarity */
> +#define UWK_CTL1_IDDIG_E (0x1 << 10) /* enable debounce */
> +#define UWK_CTL1_IDDIG_C(x) (((x) & 0xf) << 11) /* cycle debounce */
> +#define UWK_CTL1_0P_LS_E (0x1 << 20)
> +#define UWK_CTL1_0P_LS_C(x) (((x) & 0xf) << 21)
> +#define UWK_CTL1_IS_E (0x1 << 25)
> +#define UWK_CTL1_IS_C(x) (((x) & 0xf) << 26)
> +
> +enum ssusb_wakeup_src {
> + SSUSB_WK_IP_SLEEP = 1,
> + SSUSB_WK_LINE_STATE = 2,
> +};
> +
> +struct mt65xx_u3phy {
> + struct usb_phy phy;
> + struct device *dev;
> + void __iomem *mac_base; /* only device-mac regs, exclude xhci's */
> + void __iomem *sif_base; /* include sif & sif2 */
> + struct regmap *pericfg;
> + struct clk *wk_deb_p0; /* port0's wakeup debounce clock */
> + struct clk *wk_deb_p1;
> + struct clk *u3phya_ref; /* reference clock of usb3 anolog phy */
> + int wakeup_src;
> + int u2port_num;
> +};
> +
> +
> +static void u3p_writel(void __iomem *base, u32 offset, u32 data)
> +{
> + writel(data, base + offset);
> +}
Never ever name a function 'writel' that has the arguments reversed to
the original writel function.
> +
> +static u32 u3p_readl(void __iomem *base, u32 offset)
> +{
> + return readl(base + offset);
> +}
> +
> +static void u3p_setmsk(void __iomem *base, u32 offset, u32 msk)
> +{
> + void __iomem *addr = base + offset;
> +
> + writel((readl(addr) | msk), addr);
> +}
> +
> +static void u3p_clrmsk(void __iomem *base, u32 offset, u32 msk)
> +{
> + void __iomem *addr = base + offset;
> +
> + writel((readl(addr) & ~msk), addr);
> +}
> +
> +static void u3p_setval(void __iomem *base, u32 offset,
> + u32 mask, u32 value)
> +{
> + void __iomem *addr = base + offset;
> + unsigned int new_value;
> +
> + new_value = (readl(addr) & ~mask) | value;
> + writel(new_value, addr);
> +}
> +
> +static void phy_index_power_on(struct mt65xx_u3phy *u3phy, int index)
> +{
> + void __iomem *sif_base = u3phy->sif_base + U3P_PHY_BASE(index);
> +
> + if (!index) {
> + /* Set RG_SSUSB_VUSB10_ON as 1 after VUSB10 ready */
> + u3p_setmsk(sif_base, U3P_U3_PHYA_REG0, P3A_RG_U3_VUSB10_ON);
> + /* power domain iso disable */
> + u3p_clrmsk(sif_base, U3P_USBPHYACR6, PA6_RG_U2_ISO_EN);
> + }
> +
> + /* switch to USB function. (system register, force ip into usb mode) */
> + u3p_clrmsk(sif_base, U3P_U2PHYDTM0, P2C_FORCE_UART_EN);
> + u3p_clrmsk(sif_base, U3P_U2PHYDTM1, P2C_RG_UART_EN);
> + if (!index)
> + u3p_clrmsk(sif_base, U3P_U2PHYACR4, P2C_U2_GPIO_CTR_MSK);
> +
> + /* (force_suspendm=0) (let suspendm=1, enable usb 480MHz pll) */
> + u3p_clrmsk(sif_base, U3P_U2PHYDTM0, P2C_FORCE_SUSPENDM);
> + u3p_clrmsk(sif_base, U3P_U2PHYDTM0,
> + P2C_RG_XCVRSEL | P2C_RG_DATAIN | P2C_DTM0_PART_MASK);
> +
> + /* DP/DM BC1.1 path Disable */
> + u3p_clrmsk(sif_base, U3P_USBPHYACR6, PA6_RG_U2_BC11_SW_EN);
> + /* OTG Enable */
> + u3p_setmsk(sif_base, U3P_USBPHYACR6, PA6_RG_U2_OTG_VBUSCMP_EN);
> + u3p_setval(sif_base, U3P_U3PHYA_DA_REG0, P3A_RG_XTAL_EXT_EN_U3,
> + P3A_RG_XTAL_EXT_EN_U3_VAL(2));
> + u3p_setval(sif_base, U3P_U3_PHYA_REG9, P3A_RG_RX_DAC_MUX,
> + P3A_RG_RX_DAC_MUX_VAL(4));
> +
> + if (!index) {
> + u3p_setmsk(sif_base, U3P_XTALCTL3, XC3_RG_U3_XTAL_RX_PWD);
> + u3p_setmsk(sif_base, U3P_XTALCTL3, XC3_RG_U3_FRC_XTAL_RX_PWD);
> + /* [mt8173]disable Change 100uA current from SSUSB */
> + u3p_clrmsk(sif_base, U3P_USBPHYACR5, PA5_RG_U2_HS_100U_U3_EN);
> + }
> + u3p_setval(sif_base, U3P_U3_PHYA_REG6, P3A_RG_TX_EIDLE_CM,
> + P3A_RG_TX_EIDLE_CM_VAL(0xe));
> + u3p_setval(sif_base, U3P_PHYD_CDR1, P3D_RG_CDR_BIR_LTD0,
> + P3D_RG_CDR_BIR_LTD0_VAL(0xc));
> + u3p_setval(sif_base, U3P_PHYD_CDR1, P3D_RG_CDR_BIR_LTD1,
> + P3D_RG_CDR_BIR_LTD1_VAL(0x3));
> +
> + udelay(800);
> + u3p_setmsk(sif_base, U3P_U2PHYDTM1, P2C_RG_VBUSVALID | P2C_RG_AVALID);
> + u3p_clrmsk(sif_base, U3P_U2PHYDTM1, P2C_RG_SESSEND);
> +
> + /* USB 2.0 slew rate calibration */
> + u3p_setval(sif_base, U3P_USBPHYACR5, PA5_RG_U2_HSTX_SRCTRL,
> + PA5_RG_U2_HSTX_SRCTRL_VAL(4));
> +
> + dev_dbg(u3phy->dev, "%s(%d)\n", __func__, index);
> +}
> +
> +static void phy_index_power_off(struct mt65xx_u3phy *u3phy, int index)
> +{
> + void __iomem *sif_base = u3phy->sif_base + U3P_PHY_BASE(index);
> +
> + /* switch to USB function. (system register, force ip into usb mode) */
> + u3p_clrmsk(sif_base, U3P_U2PHYDTM0, P2C_FORCE_UART_EN);
> + u3p_clrmsk(sif_base, U3P_U2PHYDTM1, P2C_RG_UART_EN);
That's the same register sequence as above in power_on. Do you really
need to do this twice or is this more something that should be done
during initialization once?
> + if (!index)
> + u3p_clrmsk(sif_base, U3P_U2PHYACR4, P2C_U2_GPIO_CTR_MSK);
> +
> + u3p_setmsk(sif_base, U3P_U2PHYDTM0, P2C_FORCE_SUSPENDM);
> + u3p_setval(sif_base, U3P_U2PHYDTM0,
> + P2C_RG_XCVRSEL, P2C_RG_XCVRSEL_VAL(1));
> + u3p_setval(sif_base, U3P_U2PHYDTM0,
> + P2C_RG_DATAIN, P2C_RG_DATAIN_VAL(0));
> + u3p_setmsk(sif_base, U3P_U2PHYDTM0, P2C_DTM0_PART_MASK);
That's four read/write accesses in a row which is really hard to read.
This should really be something like:
val = readl(sif_base + U3P_U2PHYDTM0);
val &= ~(P2C_RG_XCVRSEL | P2C_RG_DATAIN)
val |= P2C_FORCE_SUSPENDM | P2C_RG_XCVRSEL_VAL(1);
writel(val, sif_base + U3P_U2PHYDTM0);
Those read/modify/write access functions often have the tendency to lead
to inefficient code.
Generally review your register accesses. There are several bits that are
cleared multiple times but never set, like:
U3P_U2PHYDTM0, P2C_FORCE_UART_EN -> cleared multiple times, never set
U3P_USBPHYACR6, PA6_RG_U2_BC11_SW_EN -> cleared mutliple times, never set
U3P_U2PHYDTM1, P2C_RG_UART_EN -> cleared mutliple times, never set
This probably belongs to some init code executed once.
> + /* DP/DM BC1.1 path Disable */
> + u3p_clrmsk(sif_base, U3P_USBPHYACR6, PA6_RG_U2_BC11_SW_EN);
> + /* OTG Disable */
> + u3p_clrmsk(sif_base, U3P_USBPHYACR6, PA6_RG_U2_OTG_VBUSCMP_EN);
> + if (!index) {
> + /* Change 100uA current switch to USB2.0 */
> + u3p_clrmsk(sif_base, U3P_USBPHYACR5, PA5_RG_U2_HS_100U_U3_EN);
> + }
> + udelay(800);
> +
> + /* let suspendm=0, set utmi into analog power down */
> + u3p_clrmsk(sif_base, U3P_U2PHYDTM0, P2C_RG_SUSPENDM);
> + udelay(1);
> +
> + u3p_clrmsk(sif_base, U3P_U2PHYDTM1, P2C_RG_VBUSVALID | P2C_RG_AVALID);
> + u3p_setmsk(sif_base, U3P_U2PHYDTM1, P2C_RG_SESSEND);
> + if (!index) {
> + /* Set RG_SSUSB_VUSB10_ON as 1 after VUSB10 ready */
> + u3p_clrmsk(sif_base, U3P_U3_PHYA_REG0, P3A_RG_U3_VUSB10_ON);
> + }
> + dev_dbg(u3phy->dev, "%s(%d)\n", __func__, index);
> +}
> +
> +static void u3phy_power_on(struct mt65xx_u3phy *u3phy)
> +{
> + phy_index_power_on(u3phy, 0);
> + if (u3phy->u2port_num > 1)
> + phy_index_power_on(u3phy, 1);
> +}
> +
> +static void u3phy_power_off(struct mt65xx_u3phy *u3phy)
> +{
> + phy_index_power_off(u3phy, 0);
> + if (u3phy->u2port_num > 1)
> + phy_index_power_off(u3phy, 1);
> +}
> +
> +static int check_ip_clk_status(struct mt65xx_u3phy *u3phy)
> +{
> + int ret;
> + int u3_port_num;
> + int u2_port_num;
> + u32 xhci_cap;
> + u32 val;
> + void __iomem *sif_base = u3phy->sif_base;
> +
> + xhci_cap = u3p_readl(sif_base, U3P_IP_XHCI_CAP);
> + u3_port_num = CAP_U3_PORT_NUM(xhci_cap);
> + u2_port_num = CAP_U2_PORT_NUM(xhci_cap);
> +
> + ret = readl_poll_timeout(sif_base + U3P_IP_PW_STS1, val,
> + (val & STS1_SYSPLL_STABLE), 100, 10000);
> + if (ret) {
> + dev_err(u3phy->dev, "sypll is not stable!!!\n");
> + return ret;
> + }
> +
> + ret = eadl_poll_timeout(sif_base + U3P_IP_PW_STS1, val,
> + (val & STS1_REF_RST), 100, 10000);
> + if (ret) {
> + dev_err(u3phy->dev, "ref_clk is still active!!!\n");
> + return ret;
> + }
> +
> + ret = readl_poll_timeout(sif_base + U3P_IP_PW_STS1, val,
> + (val & STS1_SYS125_RST), 100, 10000);
> + if (ret) {
> + dev_err(u3phy->dev, "sys125_ck is still active!!!\n");
> + return ret;
> + }
> +
> + if (u3_port_num) {
> + ret = readl_poll_timeout(sif_base + U3P_IP_PW_STS1, val,
> + (val & STS1_U3_MAC_RST), 100, 10000);
> + if (ret) {
> + dev_err(u3phy->dev, "mac3_mac_ck is still active!!!\n");
> + return ret;
> + }
> + }
> +
> + if (u2_port_num) {
> + ret = readl_poll_timeout(sif_base + U3P_IP_PW_STS2, val,
> + (val & STS2_U2_MAC_RST), 100, 10000);
> + if (ret) {
> + dev_err(u3phy->dev, "mac2_sys_ck is still active!!!\n");
> + return ret;
> + }
> + }
> +
> + return 0;
> +}
> +
> +static int u3phy_ports_enable(struct mt65xx_u3phy *u3phy)
> +{
> + int i;
> + u32 temp;
> + int u3_port_num;
> + int u2_port_num;
> + void __iomem *sif_base = u3phy->sif_base;
> +
> + temp = u3p_readl(sif_base, U3P_IP_XHCI_CAP);
> + u3_port_num = CAP_U3_PORT_NUM(temp);
> + u2_port_num = CAP_U2_PORT_NUM(temp);
> + dev_dbg(u3phy->dev, "%s u2p:%d, u3p:%d\n",
> + __func__, u2_port_num, u3_port_num);
> +
> + /* power on host ip */
> + u3p_clrmsk(sif_base, U3P_IP_PW_CTRL1, CTRL1_IP_HOST_PDN);
> +
> + /* power on and enable all u3 ports */
> + for (i = 0; i < u3_port_num; i++) {
> + temp = u3p_readl(sif_base, U3P_U3_CTRL(i));
> + temp &= ~(CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS);
> + temp |= CTRL_U3_PORT_HOST_SEL;
> + u3p_writel(sif_base, U3P_U3_CTRL(i), temp);
> + }
> +
> + /* power on and enable all u2 ports */
> + for (i = 0; i < u2_port_num; i++) {
> + temp = u3p_readl(sif_base, U3P_U2_CTRL(i));
> + temp &= ~(CTRL_U2_PORT_PDN | CTRL_U2_PORT_DIS);
> + temp |= CTRL_U2_PORT_HOST_SEL;
> + u3p_writel(sif_base, U3P_U2_CTRL(i), temp);
> + }
> + return check_ip_clk_status(u3phy);
> +}
> +
> +static int u3phy_ports_disable(struct mt65xx_u3phy *u3phy)
> +{
> + int i;
> + u32 temp;
> + int ret;
> + int u3_port_num;
> + int u2_port_num;
> + void __iomem *sif_base = u3phy->sif_base;
> +
> + temp = u3p_readl(sif_base, U3P_IP_XHCI_CAP);
> + u3_port_num = CAP_U3_PORT_NUM(temp);
> + u2_port_num = CAP_U2_PORT_NUM(temp);
> + dev_dbg(u3phy->dev, "%s u2p:%d, u3p:%d\n",
> + __func__, u2_port_num, u3_port_num);
> +
> + /* power on and enable all u3 ports */
This comment seems wrong.
> + for (i = 0; i < u3_port_num; i++) {
> + temp = u3p_readl(sif_base, U3P_U3_CTRL(i));
> + temp |= CTRL_U3_PORT_PDN;
> + u3p_writel(sif_base, U3P_U3_CTRL(i), temp);
> + }
> +
> + /* power on and enable all u2 ports */
ditto
> + for (i = 0; i < u2_port_num; i++) {
> + temp = u3p_readl(sif_base, U3P_U2_CTRL(i));
> + temp |= CTRL_U2_PORT_PDN;
> + u3p_writel(sif_base, U3P_U2_CTRL(i), temp);
> + }
> +
> + /* power off host ip */
> + u3p_setmsk(sif_base, U3P_IP_PW_CTRL1, CTRL1_IP_HOST_PDN);
> + u3p_setmsk(sif_base, U3P_IP_PW_CTRL2, CTRL2_IP_DEV_PDN);
> +
> + ret = readl_poll_timeout(sif_base + U3P_IP_PW_STS1, temp,
> + (temp & STS1_IP_SLEEP_STS), 100, 100000);
> + if (ret) {
> + dev_err(u3phy->dev, "ip sleep failed!!!\n");
> + return ret;
> + }
> + return 0;
> +}
> +
> +static void u3phy_timing_init(struct mt65xx_u3phy *u3phy)
> +{
> + void __iomem *mbase = u3phy->mac_base;
> + int u3_port_num;
> + u32 temp;
> +
> + temp = u3p_readl(u3phy->sif_base, U3P_IP_XHCI_CAP);
> + u3_port_num = CAP_U3_PORT_NUM(temp);
> +
> + if (u3_port_num) {
> + /* set MAC reference clock speed */
> + u3p_setval(mbase, U3P_UX_EXIT_LFPS_PARAM,
> + RX_UX_EXIT_REF, RX_UX_EXIT_REF_VAL);
> + /* set REF_CLK */
> + u3p_setval(mbase, U3P_REF_CLK_PARAM,
> + REF_CLK_1000NS, REF_CLK_VAL_DEF);
> + /* set SYS_CLK */
> + u3p_setval(mbase, U3P_TIMING_PULSE_CTRL,
> + U3T_CNT_1US, U3T_CNT_1US_VAL);
> + /* set LINK_PM_TIMER=3 */
> + u3p_setval(mbase, U3P_LINK_PM_TIMER,
> + PM_LC_TIMEOUT, PM_LC_TIMEOUT_VAL);
This fiddles in the register space of the xhci controller. Should be
done in the xhci driver, not here in the phy driver.
> + }
> + u3p_setval(mbase, U3P_U2_TIMING_PARAM, U2T_VAL_1US, U2T_VAL_1US_VAL);
> +}
> +
> +static int u3phy_clks_enable(struct mt65xx_u3phy *u3phy)
> +{
> + int ret;
> +
> + ret = clk_prepare_enable(u3phy->u3phya_ref);
> + if (ret) {
> + dev_err(u3phy->dev, "failed to enable u3phya_ref\n");
> + goto u3phya_ref_err;
> + }
> + ret = clk_prepare_enable(u3phy->wk_deb_p0);
> + if (ret) {
> + dev_err(u3phy->dev, "failed to enable wk_deb_p0\n");
> + goto usb_p0_err;
> + }
> + if (u3phy->u2port_num > 1) {
> + ret = clk_prepare_enable(u3phy->wk_deb_p1);
> + if (ret) {
> + dev_err(u3phy->dev, "failed to enable wk_deb_p1\n");
> + goto usb_p1_err;
> + }
> + }
> + udelay(50);
> +
> + return 0;
> +
> +usb_p1_err:
> + clk_disable_unprepare(u3phy->wk_deb_p0);
> +usb_p0_err:
> + clk_disable_unprepare(u3phy->u3phya_ref);
> +u3phya_ref_err:
> + return -EINVAL;
> +}
> +
> +static void u3phy_clks_disable(struct mt65xx_u3phy *u3phy)
> +{
> + if (u3phy->u2port_num > 1)
> + clk_disable_unprepare(u3phy->wk_deb_p1);
> + clk_disable_unprepare(u3phy->wk_deb_p0);
> + clk_disable_unprepare(u3phy->u3phya_ref);
> +}
> +
> +/* only clocks can be turn off for ip-sleep wakeup mode */
> +static void usb_wakeup_ip_sleep_en(struct mt65xx_u3phy *u3phy)
> +{
> + u32 tmp;
> + struct regmap *pericfg = u3phy->pericfg;
> +
> + regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
> + tmp &= ~UWK_CTL1_IS_P;
> + tmp &= ~(UWK_CTL1_IS_C(0xf));
> + tmp |= UWK_CTL1_IS_C(0x8);
> + regmap_write(pericfg, PERI_WK_CTRL1, tmp);
> + regmap_write(pericfg, PERI_WK_CTRL1, tmp | UWK_CTL1_IS_E);
> +
> + regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
> + dev_dbg(u3phy->dev, "%s(): WK_CTRL1[P6,E25,C26:29]=%#x\n", __func__,
> + tmp);
> +}
> +
> +static void usb_wakeup_ip_sleep_dis(struct mt65xx_u3phy *u3phy)
> +{
> + u32 tmp;
> +
> + regmap_read(u3phy->pericfg, PERI_WK_CTRL1, &tmp);
> + tmp &= ~UWK_CTL1_IS_E;
> + regmap_write(u3phy->pericfg, PERI_WK_CTRL1, tmp);
> +}
> +
> +/*
> +* for line-state wakeup mode, phy's power should not power-down
> +* and only support cable plug in/out
> +*/
> +static void usb_wakeup_line_state_en(struct mt65xx_u3phy *u3phy)
> +{
> + u32 tmp;
> + struct regmap *pericfg = u3phy->pericfg;
> +
> + /* line-state of u2-port0 */
> + regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
> + tmp &= ~UWK_CTL1_0P_LS_P;
> + tmp &= ~(UWK_CTL1_0P_LS_C(0xf));
> + tmp |= UWK_CTL1_0P_LS_C(0x8);
> + regmap_write(pericfg, PERI_WK_CTRL1, tmp);
> + regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
> + regmap_write(pericfg, PERI_WK_CTRL1, tmp | UWK_CTL1_0P_LS_E);
> +
> + /* line-state of u2-port1 if support */
> + if (u3phy->u2port_num > 1) {
> + regmap_read(pericfg, PERI_WK_CTRL0, &tmp);
> + tmp &= ~(UWK_CTL1_1P_LS_C(0xf));
> + tmp |= UWK_CTL1_1P_LS_C(0x8);
> + regmap_write(pericfg, PERI_WK_CTRL0, tmp);
> + regmap_write(pericfg, PERI_WK_CTRL0, tmp | UWK_CTL1_1P_LS_E);
> + }
> +}
> +
> +static void usb_wakeup_line_state_dis(struct mt65xx_u3phy *u3phy)
> +{
> + u32 tmp;
> + struct regmap *pericfg = u3phy->pericfg;
> +
> + regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
> + tmp &= ~UWK_CTL1_0P_LS_E;
> + regmap_write(pericfg, PERI_WK_CTRL1, tmp);
> +
> + if (u3phy->u2port_num > 1) {
> + regmap_read(pericfg, PERI_WK_CTRL0, &tmp);
> + tmp &= ~UWK_CTL1_1P_LS_E;
> + regmap_write(pericfg, PERI_WK_CTRL0, tmp);
> + }
> +}
> +
> +static void usb_wakeup_enable(struct mt65xx_u3phy *u3phy)
> +{
> + if (u3phy->wakeup_src == SSUSB_WK_IP_SLEEP)
> + usb_wakeup_ip_sleep_en(u3phy);
> + else if (u3phy->wakeup_src == SSUSB_WK_LINE_STATE)
> + usb_wakeup_line_state_en(u3phy);
> +}
> +
> +static void usb_wakeup_disable(struct mt65xx_u3phy *u3phy)
> +{
> + if (u3phy->wakeup_src == SSUSB_WK_IP_SLEEP)
> + usb_wakeup_ip_sleep_dis(u3phy);
> + else if (u3phy->wakeup_src == SSUSB_WK_LINE_STATE)
> + usb_wakeup_line_state_dis(u3phy);
> +}
> +
> +static int mt65xx_u3phy_init(struct usb_phy *phy)
> +{
> + struct mt65xx_u3phy *u3phy;
> + int ret;
> +
> + u3phy = container_of(phy, struct mt65xx_u3phy, phy);
> + dev_dbg(u3phy->dev, "%s+\n", __func__);
> +
> + ret = pm_runtime_get_sync(u3phy->dev);
> + if (ret < 0)
> + goto pm_err;
> +
> + ret = u3phy_clks_enable(u3phy);
> + if (ret) {
> + dev_err(u3phy->dev, "failed to enable clks\n");
> + goto clks_err;
> + }
> +
> + /* reset whole ip */
> + u3p_setmsk(u3phy->sif_base, U3P_IP_PW_CTRL0, CTRL0_IP_SW_RST);
> + u3p_clrmsk(u3phy->sif_base, U3P_IP_PW_CTRL0, CTRL0_IP_SW_RST);
> +
> + ret = u3phy_ports_enable(u3phy);
> + if (ret) {
> + dev_err(u3phy->dev, "failed to enable ports\n");
> + goto port_err;
> + }
> + u3phy_timing_init(u3phy);
> + u3phy_power_on(u3phy);
> + msleep(40);
> +
> + return 0;
> +
> +port_err:
> + u3phy_clks_disable(u3phy);
> +clks_err:
> + pm_runtime_put_sync(u3phy->dev);
> +pm_err:
> + return ret;
> +}
> +
> +
> +static void mt65xx_u3phy_shutdown(struct usb_phy *phy)
> +{
> + struct mt65xx_u3phy *u3phy;
> +
> + u3phy = container_of(phy, struct mt65xx_u3phy, phy);
> + u3phy_power_off(u3phy);
> + u3phy_clks_disable(u3phy);
> + pm_runtime_put_sync(u3phy->dev);
> +}
> +
> +
> +static int mt65xx_u3phy_suspend(struct usb_phy *x, int suspend)
> +{
> + struct mt65xx_u3phy *u3phy = container_of(x, struct mt65xx_u3phy, phy);
> +
> + if (suspend) {
> + u3phy_ports_disable(u3phy);
> + u3phy_power_off(u3phy);
> + u3phy_clks_disable(u3phy);
> + usb_wakeup_enable(u3phy);
> + } else {
> + usb_wakeup_disable(u3phy);
> + u3phy_clks_enable(u3phy);
> + u3phy_power_on(u3phy);
> + u3phy_ports_enable(u3phy);
> + }
> + return 0;
> +}
> +
> +
> +static const struct of_device_id mt65xx_u3phy_id_table[] = {
> + { .compatible = "mediatek,mt8173-u3phy",},
> + { },
> +};
> +MODULE_DEVICE_TABLE(of, mt65xx_u3phy_id_table);
> +
> +
> +static int mt65xx_u3phy_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct device_node *np = dev->of_node;
> + struct resource *mac_res;
> + struct resource *sif_res;
> + struct mt65xx_u3phy *u3phy;
> + int retval = -ENOMEM;
> +
> + u3phy = devm_kzalloc(&pdev->dev, sizeof(*u3phy), GFP_KERNEL);
> + if (!u3phy)
> + goto err;
No need for goto if all you do there is to return. return here.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v2 2/5] dt-bindings: Add a binding for Mediatek xHCI host controller
2015-07-08 9:41 ` [PATCH v2 2/5] dt-bindings: Add a binding for Mediatek xHCI host controller Chunfeng Yun
@ 2015-07-10 8:31 ` Roger Quadros
2015-07-14 2:36 ` chunfeng yun
` (2 more replies)
0 siblings, 3 replies; 22+ messages in thread
From: Roger Quadros @ 2015-07-10 8:31 UTC (permalink / raw)
To: Chunfeng Yun, Mathias Nyman
Cc: Rob Herring, Mark Rutland, Matthias Brugger, Felipe Balbi,
Sascha Hauer, devicetree, linux-kernel, linux-arm-kernel,
linux-usb, linux-mediatek
Hi,
On 08/07/15 12:41, Chunfeng Yun wrote:
> add a DT binding documentation of xHCI host controller for the
> MT8173 SoC from Mediatek.
>
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> ---
> .../devicetree/bindings/usb/mt8173-xhci.txt | 27 ++++++++++++++++++++++
> 1 file changed, 27 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/usb/mt8173-xhci.txt
>
> diff --git a/Documentation/devicetree/bindings/usb/mt8173-xhci.txt b/Documentation/devicetree/bindings/usb/mt8173-xhci.txt
> new file mode 100644
> index 0000000..94cec94
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/mt8173-xhci.txt
> @@ -0,0 +1,27 @@
> +MT65XX xhci
> +
> +The device node for Mediatek SOC usb3.0 host controller
> +
> +Required properties:
> + - compatible : supports "mediatek,mt8173-xhci"
> + - reg : Offset and length of registers
> + - interrupts : Interrupt mode, number and trigger mode
> + - reg-vusb33-supply: regulator of usb avdd3.3v
> + - reg-vbus-supply : regulator of vbus;
General trend is to use <supply-name>-supply.
We already know it is a regulator so no need to add "reg-"
So those two can be
vusb33-supply:
vbus-supply:
> + - usb-phy : the phy that xhci will bind
> + - usb3-lpm-capable: supports USB3 LPM
> + - clocks : must support all clocks that xhci needs
> + - clock-names: should be "sys_mac" for sys and mac clocks
> +
> +Example:
> +usb: usb30@11270000 {
> + compatible = "mediatek,mt8173-xhci";
> + reg = <0 0x11270000 0 0x1000>;
> + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
> + reg-vusb33-supply = <&mt6397_vusb_reg>;
> + reg-vbus-supply = <&usb_p1_vbus>;
> + usb-phy = <&u3phy>;
> + usb3-lpm-capable;
> + clocks = <&topckgen CLK_TOP_USB30_SEL>;
> + clock-names = "sys_mac";
> +};
>
cheers,
-roger
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v2 4/5] xhci: mediatek: support MTK xHCI host controller
2015-07-08 9:41 ` [PATCH v2 4/5] xhci: mediatek: support MTK xHCI host controller Chunfeng Yun
@ 2015-07-13 14:52 ` John Crispin
2015-07-20 14:51 ` chunfeng yun
0 siblings, 1 reply; 22+ messages in thread
From: John Crispin @ 2015-07-13 14:52 UTC (permalink / raw)
To: Chunfeng Yun, Mathias Nyman
Cc: Mark Rutland, devicetree, Sascha Hauer, linux-usb, linux-kernel,
Felipe Balbi, Rob Herring, linux-mediatek, Matthias Brugger,
linux-arm-kernel, Roger Quadros
Hi
there is a cross dependency between the modules. xhci-mtk.ko requires
xhci.ko to be loaded. however this will look for xhci_mtk_add_ep_quirk()
which is part of xhci-mtk. the modules will build but are not run time
loadable.
John
On 08/07/2015 11:41, Chunfeng Yun wrote:
> MTK xhci host controller defines some extra SW scheduling
> parameters for HW to minimize the scheduling effort for
> synchronous and interrupt endpoints. The parameters are
> put into reseved DWs of slot context and endpoint context
>
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> ---
> drivers/usb/host/Kconfig | 9 +
> drivers/usb/host/Makefile | 1 +
> drivers/usb/host/xhci-mtk.c | 814 +++++++++++++++++++++++++++++++++++++++++++
> drivers/usb/host/xhci-mtk.h | 108 ++++++
> drivers/usb/host/xhci-ring.c | 35 +-
> drivers/usb/host/xhci.c | 19 +-
> drivers/usb/host/xhci.h | 1 +
> 7 files changed, 980 insertions(+), 7 deletions(-)
> create mode 100644 drivers/usb/host/xhci-mtk.c
> create mode 100644 drivers/usb/host/xhci-mtk.h
>
> diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
> index 8afc3c1..2202c68 100644
> --- a/drivers/usb/host/Kconfig
> +++ b/drivers/usb/host/Kconfig
> @@ -34,6 +34,15 @@ config USB_XHCI_PCI
> config USB_XHCI_PLATFORM
> tristate
>
> +config USB_XHCI_MTK
> + tristate "xHCI support for Mediatek MT65xx"
> + select USB_XHCI_PLATFORM
> + depends on ARCH_MEDIATEK || COMPILE_TEST
> + ---help---
> + Say 'Y' to enable the support for the xHCI host controller
> + found in Mediatek MT65xx SoCs.
> + If unsure, say N.
> +
> config USB_XHCI_MVEBU
> tristate "xHCI support for Marvell Armada 375/38x"
> select USB_XHCI_PLATFORM
> diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
> index 754efaa..90c6eb2 100644
> --- a/drivers/usb/host/Makefile
> +++ b/drivers/usb/host/Makefile
> @@ -30,6 +30,7 @@ endif
>
> obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
> obj-$(CONFIG_USB_XHCI_PLATFORM) += xhci-plat-hcd.o
> +obj-$(CONFIG_USB_XHCI_MTK) += xhci-mtk.o
>
> obj-$(CONFIG_USB_EHCI_HCD) += ehci-hcd.o
> obj-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
> diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c
> new file mode 100644
> index 0000000..45f0606
> --- /dev/null
> +++ b/drivers/usb/host/xhci-mtk.c
> @@ -0,0 +1,814 @@
> +/*
> + * Copyright (c) 2015 MediaTek Inc.
> + * Author:
> + * Zhigang.Wei <zhigang.wei@mediatek.com>
> + * Chunfeng.Yun <chunfeng.yun@mediatek.com>
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/clk.h>
> +#include <linux/dma-mapping.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/usb/phy.h>
> +#include <linux/slab.h>
> +#include <linux/usb/xhci_pdriver.h>
> +#include <linux/regulator/consumer.h>
> +#include <linux/pm_runtime.h>
> +
> +#include "xhci.h"
> +#include "xhci-mtk.h"
> +
> +
> +#define SS_BW_BOUNDARY 51000
> +/* table 5-5. High-speed Isoc Transaction Limits in usb_20 spec */
> +#define HS_BW_BOUNDARY 6144
> +/* usb2 spec section11.18.1: at most 188 FS bytes per microframe */
> +#define FS_PAYLOAD_MAX 188
> +
> +/* mtk scheduler bitmasks */
> +#define EP_BPKTS(p) ((p) & 0x3f)
> +#define EP_BCSCOUNT(p) (((p) & 0x7) << 8)
> +#define EP_BBM(p) ((p) << 11)
> +#define EP_BOFFSET(p) ((p) & 0x3fff)
> +#define EP_BREPEAT(p) (((p) & 0x7fff) << 16)
> +
> +
> +struct xhci_hcd_mtk {
> + struct device *dev;
> + struct usb_hcd *hcd;
> + struct mu3h_sch_bw_info *sch_array;
> + struct regulator *vusb33;
> + struct regulator *vbus;
> + struct clk *sys_mac; /* sys and mac clock */
> +};
> +
> +
> +static int is_fs_or_ls(enum usb_device_speed speed)
> +{
> + return speed == USB_SPEED_FULL || speed == USB_SPEED_LOW;
> +}
> +
> +static int get_bw_index(struct xhci_hcd *xhci, struct usb_device *udev,
> + struct usb_host_endpoint *ep)
> +{
> + int bw_index;
> + int port_id;
> + struct xhci_virt_device *virt_dev;
> +
> + virt_dev = xhci->devs[udev->slot_id];
> + port_id = virt_dev->real_port;
> +
> + if (udev->speed == USB_SPEED_SUPER) {
> + if (usb_endpoint_dir_out(&ep->desc))
> + bw_index = (port_id - 1) * 2;
> + else
> + bw_index = (port_id - 1) * 2 + 1;
> + } else {
> + bw_index = port_id + xhci->num_usb3_ports - 1;
> + }
> +
> + return bw_index;
> +}
> +
> +
> +static void setup_sch_info(struct usb_device *udev,
> + struct xhci_ep_ctx *ep_ctx, struct mu3h_sch_ep_info *sch_ep)
> +{
> + u32 ep_type;
> + u32 ep_interval;
> + u32 max_packet_size;
> + u32 max_burst;
> + u32 mult;
> + u32 esit_pkts;
> +
> + ep_type = CTX_TO_EP_TYPE(le32_to_cpu(ep_ctx->ep_info2));
> + ep_interval = CTX_TO_EP_INTERVAL(le32_to_cpu(ep_ctx->ep_info));
> + max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
> + max_burst = CTX_TO_MAX_BURST(le32_to_cpu(ep_ctx->ep_info2));
> + mult = CTX_TO_EP_MULT(le32_to_cpu(ep_ctx->ep_info));
> + pr_debug("%s: max_burst = %d, mult = %d\n", __func__, max_burst, mult);
> +
> + sch_ep->ep_type = ep_type;
> + sch_ep->max_packet_size = max_packet_size;
> + sch_ep->esit = 1 << ep_interval;
> + sch_ep->offset = 0;
> + sch_ep->burst_mode = 0;
> +
> + if (udev->speed == USB_SPEED_HIGH) {
> + sch_ep->cs_count = 0;
> + /*
> + * usb_20 spec section5.9
> + * a single microframe is enough for HS synchromous endpoints
> + * in a interval
> + */
> + sch_ep->num_budget_microframes = 1;
> + sch_ep->repeat = 0;
> + /*
> + * xHCI spec section6.2.3.4
> + * @max_busrt is the number of additional transactions
> + * opportunities per microframe
> + */
> + sch_ep->pkts = max_burst + 1;
> + sch_ep->bw_cost_per_microframe = max_packet_size * sch_ep->pkts;
> + } else if (udev->speed == USB_SPEED_SUPER) {
> + /* usb3_r1 spec section4.4.7 & 4.4.8 */
> + sch_ep->cs_count = 0;
> + esit_pkts = (mult + 1) * (max_burst + 1);
> + if (ep_type == INT_IN_EP || ep_type == INT_OUT_EP) {
> + sch_ep->pkts = esit_pkts;
> + sch_ep->num_budget_microframes = 1;
> + sch_ep->repeat = 0;
> + }
> +
> + if (ep_type == ISOC_IN_EP || ep_type == ISOC_OUT_EP) {
> + if (esit_pkts <= sch_ep->esit)
> + sch_ep->pkts = 1;
> + else
> + sch_ep->pkts = roundup_pow_of_two(esit_pkts)
> + / sch_ep->esit;
> +
> + sch_ep->num_budget_microframes =
> + DIV_ROUND_UP(esit_pkts, sch_ep->pkts);
> +
> + if (sch_ep->num_budget_microframes > 1)
> + sch_ep->repeat = 1;
> + else
> + sch_ep->repeat = 0;
> + }
> + sch_ep->bw_cost_per_microframe = max_packet_size * sch_ep->pkts;
> + } else if (is_fs_or_ls(udev->speed)) {
> + /*
> + * usb_20 spec section11.18.4
> + * assume worst cases
> + */
> + sch_ep->repeat = 0;
> + sch_ep->pkts = 1; /* at most one packet for each microframe */
> + if (ep_type == INT_IN_EP || ep_type == INT_OUT_EP) {
> + sch_ep->cs_count = 3; /* at most need 3 CS*/
> + /* one for SS and one for budgeted transaction */
> + sch_ep->num_budget_microframes = sch_ep->cs_count + 2;
> + sch_ep->bw_cost_per_microframe = max_packet_size;
> + }
> + if (ep_type == ISOC_OUT_EP) {
> + /* must never schedule a cs ISOC OUT ep */
> + sch_ep->cs_count = 0;
> + /*
> + * the best case FS budget assumes that 188 FS bytes
> + * occur in each microframe
> + */
> + sch_ep->num_budget_microframes = DIV_ROUND_UP(
> + sch_ep->max_packet_size, FS_PAYLOAD_MAX);
> + sch_ep->bw_cost_per_microframe = FS_PAYLOAD_MAX;
> + }
> + if (ep_type == ISOC_IN_EP) {
> + /* at most need additional two CS. */
> + sch_ep->cs_count = DIV_ROUND_UP(
> + sch_ep->max_packet_size, FS_PAYLOAD_MAX) + 2;
> + sch_ep->num_budget_microframes = sch_ep->cs_count + 2;
> + sch_ep->bw_cost_per_microframe = FS_PAYLOAD_MAX;
> + }
> + }
> +}
> +
> +/* Get maximum bandwidth when we schedule at offset slot. */
> +static u32 get_max_bw(struct mu3h_sch_bw_info *sch_bw,
> + struct mu3h_sch_ep_info *sch_ep, u32 offset)
> +{
> + u32 num_esit;
> + u32 max_bw = 0;
> + int i;
> + int j;
> +
> + num_esit = XHCI_MTK_MAX_ESIT / sch_ep->esit;
> + for (i = 0; i < num_esit; i++) {
> + u32 base = offset + i * sch_ep->esit;
> +
> + for (j = 0; j < sch_ep->num_budget_microframes; j++) {
> + if (sch_bw->bus_bw[base + j] > max_bw)
> + max_bw = sch_bw->bus_bw[base + j];
> + }
> + }
> + return max_bw;
> +}
> +
> +static void update_bus_bw(struct mu3h_sch_bw_info *sch_bw,
> + struct mu3h_sch_ep_info *sch_ep, int bw_cost)
> +{
> + u32 num_esit;
> + u32 base;
> + int i;
> + int j;
> +
> + num_esit = XHCI_MTK_MAX_ESIT / sch_ep->esit;
> + for (i = 0; i < num_esit; i++) {
> + base = sch_ep->offset + i * sch_ep->esit;
> + for (j = 0; j < sch_ep->num_budget_microframes; j++)
> + sch_bw->bus_bw[base + j] += bw_cost;
> + }
> +
> +}
> +
> +static void debug_sch_ep(struct mu3h_sch_ep_info *sch_ep)
> +{
> + pr_debug("%s:\n", __func__);
> + pr_debug("sch_ep->ep_type = %d\n", sch_ep->ep_type);
> + pr_debug("sch_ep->max_packet_size = %d\n", sch_ep->max_packet_size);
> + pr_debug("sch_ep->esit = %d\n", sch_ep->esit);
> + pr_debug("sch_ep->num_budget_microframes = %d\n",
> + sch_ep->num_budget_microframes);
> + pr_debug("sch_ep->bw_cost_per_microframe = %d\n",
> + sch_ep->bw_cost_per_microframe);
> + pr_debug("sch_ep->ep = %p\n", sch_ep->ep);
> + pr_debug("sch_ep->offset = %d\n", sch_ep->offset);
> + pr_debug("sch_ep->repeat = %d\n", sch_ep->repeat);
> + pr_debug("sch_ep->pkts = %d\n", sch_ep->pkts);
> + pr_debug("sch_ep->cs_count = %d\n", sch_ep->cs_count);
> +}
> +
> +static int check_sch_bw(struct usb_device *udev,
> + struct mu3h_sch_bw_info *sch_bw, struct mu3h_sch_ep_info *sch_ep)
> +{
> + u32 offset;
> + u32 esit;
> + u32 num_budget_microframes;
> + u32 min_bw;
> + u32 min_index;
> + u32 worst_bw;
> + u32 bw_boundary;
> +
> + if (sch_ep->esit > XHCI_MTK_MAX_ESIT)
> + sch_ep->esit = XHCI_MTK_MAX_ESIT;
> +
> + esit = sch_ep->esit;
> + num_budget_microframes = sch_ep->num_budget_microframes;
> +
> + /*
> + * Search through all possible schedule microframes.
> + * and find a microframe where its worst bandwidth is minimum.
> + */
> + min_bw = ~0;
> + min_index = 0;
> + for (offset = 0; offset < esit; offset++) {
> + if ((offset + num_budget_microframes) > sch_ep->esit)
> + break;
> + /*
> + * usb_20 spec section11.18:
> + * must never schedule Start-Split in Y6
> + */
> + if (is_fs_or_ls(udev->speed) && (offset % 8 == 6))
> + continue;
> +
> + worst_bw = get_max_bw(sch_bw, sch_ep, offset);
> + if (min_bw > worst_bw) {
> + min_bw = worst_bw;
> + min_index = offset;
> + }
> + if (min_bw == 0)
> + break;
> + }
> + sch_ep->offset = min_index;
> +
> + debug_sch_ep(sch_ep);
> +
> + bw_boundary = (udev->speed == USB_SPEED_SUPER)
> + ? SS_BW_BOUNDARY : HS_BW_BOUNDARY;
> +
> + /* check bandwidth */
> + if (min_bw + sch_ep->bw_cost_per_microframe > bw_boundary)
> + return -1;
> +
> + /* update bus bandwidth info */
> + update_bus_bw(sch_bw, sch_ep, sch_ep->bw_cost_per_microframe);
> +
> + return 0;
> +}
> +
> +static void debug_sch_bw(struct mu3h_sch_bw_info *sch_bw)
> +{
> + int i;
> +
> + pr_debug("%s: bus_bw_info\n", __func__);
> + for (i = 0; i < XHCI_MTK_MAX_ESIT; i++)
> + pr_debug("%d ", sch_bw->bus_bw[i]);
> +
> + pr_debug("\n");
> +}
> +
> +
> +static bool need_bw_sch(struct usb_host_endpoint *ep,
> + enum usb_device_speed speed, int has_tt)
> +{
> + /* only for periodic endpoints */
> + if (usb_endpoint_xfer_control(&ep->desc)
> + || usb_endpoint_xfer_bulk(&ep->desc))
> + return false;
> + /*
> + * for LS & FS periodic endpoints which its device don't attach
> + * to TT are also ignored, root-hub will schedule them directly
> + */
> + if (is_fs_or_ls(speed) && !has_tt)
> + return false;
> +
> + return true;
> +}
> +
> +static int xhci_mtk_sch_init(struct xhci_hcd *xhci)
> +{
> + struct usb_hcd *hcd = xhci_to_hcd(xhci);
> + struct device *dev = hcd->self.controller;
> + struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
> + struct mu3h_sch_bw_info *sch_array;
> + int num_usb_bus;
> + int i;
> +
> + /* ss IN and OUT are separated */
> + num_usb_bus = xhci->num_usb3_ports * 2 + xhci->num_usb2_ports;
> +
> + sch_array = kcalloc(num_usb_bus, sizeof(*sch_array), GFP_KERNEL);
> + if (sch_array == NULL)
> + return -ENOMEM;
> +
> + for (i = 0; i < num_usb_bus; i++)
> + INIT_LIST_HEAD(&sch_array[i].bw_ep_list);
> +
> + mtk->sch_array = sch_array;
> +
> + return 0;
> +}
> +
> +
> +static void xhci_mtk_sch_exit(struct xhci_hcd *xhci)
> +{
> + struct usb_hcd *hcd = xhci_to_hcd(xhci);
> + struct device *dev = hcd->self.controller;
> + struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
> +
> + kfree(mtk->sch_array);
> +}
> +
> +
> +int xhci_mtk_add_ep_quirk(struct usb_hcd *hcd, struct usb_device *udev,
> + struct usb_host_endpoint *ep)
> +{
> + struct device *dev = hcd->self.controller;
> + struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
> +
> + int ret = 0;
> + int port_id;
> + int bw_index;
> + struct xhci_hcd *xhci;
> + unsigned int ep_index;
> + struct xhci_ep_ctx *ep_ctx;
> + struct xhci_slot_ctx *slot_ctx;
> + struct xhci_virt_device *virt_dev;
> + struct mu3h_sch_bw_info *sch_bw;
> + struct mu3h_sch_ep_info *sch_ep;
> + struct mu3h_sch_bw_info *sch_array;
> +
> + xhci = hcd_to_xhci(hcd);
> + virt_dev = xhci->devs[udev->slot_id];
> + ep_index = xhci_get_endpoint_index(&ep->desc);
> + slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
> + ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
> + sch_array = mtk->sch_array;
> +
> + port_id = virt_dev->real_port;
> + xhci_dbg(xhci, "%s() xfer_type: %d, speed:%d, ep:%p\n", __func__,
> + usb_endpoint_type(&ep->desc), udev->speed, ep);
> +
> + if (!need_bw_sch(ep, udev->speed, slot_ctx->tt_info & TT_SLOT))
> + return 0;
> +
> + bw_index = get_bw_index(xhci, udev, ep);
> + sch_bw = &sch_array[bw_index];
> +
> + sch_ep = kzalloc(sizeof(struct mu3h_sch_ep_info), GFP_NOIO);
> + if (!sch_ep)
> + return -ENOMEM;
> +
> + setup_sch_info(udev, ep_ctx, sch_ep);
> +
> + ret = check_sch_bw(udev, sch_bw, sch_ep);
> + if (ret) {
> + xhci_err(xhci, "Not enough bandwidth!\n");
> + kfree(sch_ep);
> + return -ENOSPC;
> + }
> +
> + list_add_tail(&sch_ep->endpoint, &sch_bw->bw_ep_list);
> + sch_ep->ep = ep;
> +
> + ep_ctx->reserved[0] |= cpu_to_le32(EP_BPKTS(sch_ep->pkts)
> + | EP_BCSCOUNT(sch_ep->cs_count) | EP_BBM(sch_ep->burst_mode));
> + ep_ctx->reserved[1] |= cpu_to_le32(EP_BOFFSET(sch_ep->offset)
> + | EP_BREPEAT(sch_ep->repeat));
> +
> + debug_sch_bw(sch_bw);
> + return 0;
> +}
> +EXPORT_SYMBOL_GPL(xhci_mtk_add_ep_quirk);
> +
> +
> +void xhci_mtk_drop_ep_quirk(struct usb_hcd *hcd, struct usb_device *udev,
> + struct usb_host_endpoint *ep)
> +{
> + struct device *dev = hcd->self.controller;
> + struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
> +
> + int bw_index;
> + struct xhci_hcd *xhci;
> + struct xhci_slot_ctx *slot_ctx;
> + struct xhci_virt_device *virt_dev;
> + struct mu3h_sch_bw_info *sch_array;
> + struct mu3h_sch_bw_info *sch_bw;
> + struct mu3h_sch_ep_info *sch_ep;
> +
> + xhci = hcd_to_xhci(hcd);
> + virt_dev = xhci->devs[udev->slot_id];
> + slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
> + sch_array = mtk->sch_array;
> +
> + xhci_dbg(xhci, "%s() xfer_type: %d, speed:%d, ep:%p\n", __func__,
> + usb_endpoint_type(&ep->desc), udev->speed, ep);
> +
> + if (!need_bw_sch(ep, udev->speed, slot_ctx->tt_info & TT_SLOT))
> + return;
> +
> + bw_index = get_bw_index(xhci, udev, ep);
> + sch_bw = &sch_array[bw_index];
> +
> + list_for_each_entry(sch_ep, &sch_bw->bw_ep_list, endpoint) {
> + if (sch_ep->ep == ep) {
> + update_bus_bw(sch_bw, sch_ep,
> + -sch_ep->bw_cost_per_microframe);
> + list_del(&sch_ep->endpoint);
> + kfree(sch_ep);
> + break;
> + }
> + }
> + debug_sch_bw(sch_bw);
> +}
> +EXPORT_SYMBOL_GPL(xhci_mtk_drop_ep_quirk);
> +
> +
> +/*
> + * The TD size is the number of max packet sized packets remaining in the TD
> + * (including this TRB), right shifted by 10.
> + * It must fit in bits 21:17, so it can't be bigger than 31.
> + */
> +u32 xhci_mtk_td_remainder_quirk(unsigned int td_running_total,
> + unsigned trb_buffer_length, struct urb *urb)
> +{
> + u32 max = 31;
> + int remainder, td_packet_count, packet_transferred;
> + unsigned int td_transfer_size = urb->transfer_buffer_length;
> + unsigned int maxp;
> +
> + maxp = GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc));
> +
> + /* 0 for the last TRB */
> + if (td_running_total + trb_buffer_length == td_transfer_size)
> + return 0;
> +
> + packet_transferred = td_running_total / maxp;
> + td_packet_count = DIV_ROUND_UP(td_transfer_size, maxp);
> + remainder = td_packet_count - packet_transferred;
> +
> + if (remainder > max)
> + return max << 17;
> + else
> + return remainder << 17;
> +}
> +EXPORT_SYMBOL_GPL(xhci_mtk_td_remainder_quirk);
> +
> +
> +static int xhci_mtk_setup(struct usb_hcd *hcd);
> +static const struct xhci_driver_overrides xhci_mtk_overrides __initconst = {
> + .extra_priv_size = sizeof(struct xhci_hcd),
> + .reset = xhci_mtk_setup,
> +};
> +
> +static struct hc_driver __read_mostly xhci_mtk_hc_driver;
> +
> +
> +static int xhci_mtk_ldos_enable(struct xhci_hcd_mtk *mtk)
> +{
> + int ret;
> +
> + ret = regulator_enable(mtk->vbus);
> + if (ret) {
> + dev_err(mtk->dev, "failed to enable vbus\n");
> + return ret;
> + }
> +
> + ret = regulator_enable(mtk->vusb33);
> + if (ret) {
> + dev_err(mtk->dev, "failed to enable vusb33\n");
> + regulator_disable(mtk->vbus);
> + return ret;
> + }
> + return 0;
> +}
> +
> +static void xhci_mtk_ldos_disable(struct xhci_hcd_mtk *mtk)
> +{
> + regulator_disable(mtk->vbus);
> + regulator_disable(mtk->vusb33);
> +}
> +
> +static void xhci_mtk_quirks(struct device *dev, struct xhci_hcd *xhci)
> +{
> + /*
> + * As of now platform drivers don't provide MSI support so we ensure
> + * here that the generic code does not try to make a pci_dev from our
> + * dev struct in order to setup MSI
> + */
> + xhci->quirks |= XHCI_PLAT;
> + xhci->quirks |= XHCI_MTK_HOST;
> + /*
> + * MTK host controller gives a spurious successful event after a
> + * short transfer. Ignore it.
> + */
> + xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
> +}
> +
> +/* called during probe() after chip reset completes */
> +static int xhci_mtk_setup(struct usb_hcd *hcd)
> +{
> + struct xhci_hcd *xhci;
> + int ret;
> +
> + ret = xhci_gen_setup(hcd, xhci_mtk_quirks);
> + if (ret)
> + return ret;
> +
> + if (!usb_hcd_is_primary_hcd(hcd))
> + return 0;
> +
> + xhci = hcd_to_xhci(hcd);
> + ret = xhci_mtk_sch_init(xhci);
> + if (ret) {
> + kfree(xhci);
> + return ret;
> + }
> +
> + return ret;
> +}
> +
> +
> +static int xhci_mtk_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct device_node *node = pdev->dev.of_node;
> + struct usb_xhci_pdata *pdata = dev_get_platdata(dev);
> + struct xhci_hcd_mtk *mtk;
> + const struct hc_driver *driver;
> + struct xhci_hcd *xhci;
> + struct resource *res;
> + struct usb_hcd *hcd;
> + int ret = -ENODEV;
> + int irq;
> +
> + if (usb_disabled())
> + return -ENODEV;
> +
> + driver = &xhci_mtk_hc_driver;
> + mtk = devm_kzalloc(dev, sizeof(*mtk), GFP_KERNEL);
> + if (!mtk)
> + return -ENOMEM;
> + mtk->dev = dev;
> +
> + mtk->sys_mac = devm_clk_get(dev, "sys_mac");
> + if (IS_ERR(mtk->sys_mac)) {
> + dev_err(dev, "error to get sys_mac\n");
> + ret = PTR_ERR(mtk->sys_mac);
> + goto err;
> + }
> +
> + mtk->vbus = devm_regulator_get(dev, "reg-vbus");
> + if (IS_ERR(mtk->vbus)) {
> + dev_err(dev, "fail to get vbus\n");
> + ret = PTR_ERR(mtk->vbus);
> + goto err;
> + }
> +
> + mtk->vusb33 = devm_regulator_get(dev, "reg-vusb33");
> + if (IS_ERR(mtk->vusb33)) {
> + dev_err(dev, "fail to get vusb33\n");
> + ret = PTR_ERR(mtk->vusb33);
> + goto err;
> + }
> + pm_runtime_enable(dev);
> + pm_runtime_get_sync(dev);
> +
> + ret = xhci_mtk_ldos_enable(mtk);
> + if (ret)
> + goto disable_pm;
> +
> + ret = clk_prepare_enable(mtk->sys_mac);
> + if (ret)
> + goto disable_ldos;
> +
> + irq = platform_get_irq(pdev, 0);
> + if (irq < 0)
> + goto disable_clk;
> +
> + /* Initialize dma_mask and coherent_dma_mask to 32-bits */
> + ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
> + if (ret)
> + goto disable_clk;
> +
> + if (!dev->dma_mask)
> + dev->dma_mask = &dev->coherent_dma_mask;
> + else
> + dma_set_mask(dev, DMA_BIT_MASK(32));
> +
> + hcd = usb_create_hcd(driver, dev, dev_name(dev));
> + if (!hcd) {
> + ret = -ENOMEM;
> + goto disable_clk;
> + }
> +
> + /*
> + * USB 2.0 roothub is stored in the platform_device.
> + * Swap it with mtk HCD.
> + */
> + mtk->hcd = platform_get_drvdata(pdev);
> + platform_set_drvdata(pdev, mtk);
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + hcd->regs = devm_ioremap_resource(dev, res);
> + if (IS_ERR(hcd->regs)) {
> + ret = PTR_ERR(hcd->regs);
> + goto put_usb2_hcd;
> + }
> + hcd->rsrc_start = res->start;
> + hcd->rsrc_len = resource_size(res);
> +
> + hcd->usb_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
> + if (IS_ERR(hcd->usb_phy)) {
> + ret = PTR_ERR(hcd->usb_phy);
> + if (ret == -EPROBE_DEFER)
> + goto put_usb2_hcd;
> + hcd->usb_phy = NULL;
> + } else {
> + ret = usb_phy_init(hcd->usb_phy);
> + if (ret)
> + goto put_usb2_hcd;
> + }
> +
> + device_wakeup_enable(hcd->self.controller);
> +
> + xhci = hcd_to_xhci(hcd);
> + xhci->main_hcd = hcd;
> + xhci->shared_hcd = usb_create_shared_hcd(driver, dev,
> + dev_name(dev), hcd);
> + if (!xhci->shared_hcd) {
> + ret = -ENOMEM;
> + goto disable_usb_phy;
> + }
> +
> + if ((node && of_property_read_bool(node, "usb3-lpm-capable")) ||
> + (pdata && pdata->usb3_lpm_capable))
> + xhci->quirks |= XHCI_LPM_SUPPORT;
> +
> + if (HCC_MAX_PSA(xhci->hcc_params) >= 4)
> + xhci->shared_hcd->can_do_streams = 1;
> +
> + ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
> + if (ret)
> + goto put_usb3_hcd;
> +
> + ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED);
> + if (ret)
> + goto dealloc_usb2_hcd;
> +
> + return 0;
> +
> +
> +dealloc_usb2_hcd:
> + usb_remove_hcd(hcd);
> +
> +put_usb3_hcd:
> + usb_put_hcd(xhci->shared_hcd);
> +
> +disable_usb_phy:
> + usb_phy_shutdown(hcd->usb_phy);
> +
> +put_usb2_hcd:
> + usb_put_hcd(hcd);
> +
> +disable_clk:
> + clk_disable_unprepare(mtk->sys_mac);
> +
> +disable_ldos:
> + xhci_mtk_ldos_disable(mtk);
> +
> +disable_pm:
> + pm_runtime_put_sync(dev);
> + pm_runtime_disable(dev);
> +
> +err:
> + return ret;
> +}
> +
> +static int xhci_mtk_remove(struct platform_device *dev)
> +{
> + struct xhci_hcd_mtk *mtk = platform_get_drvdata(dev);
> + struct usb_hcd *hcd = mtk->hcd;
> + struct xhci_hcd *xhci = hcd_to_xhci(hcd);
> +
> + usb_remove_hcd(xhci->shared_hcd);
> + usb_phy_shutdown(hcd->usb_phy);
> +
> + usb_remove_hcd(hcd);
> + usb_put_hcd(xhci->shared_hcd);
> + usb_put_hcd(hcd);
> + xhci_mtk_sch_exit(xhci);
> + clk_disable_unprepare(mtk->sys_mac);
> + xhci_mtk_ldos_disable(mtk);
> + pm_runtime_put_sync(&dev->dev);
> + pm_runtime_disable(&dev->dev);
> +
> + return 0;
> +}
> +
> +#ifdef CONFIG_PM_SLEEP
> +static int xhci_mtk_suspend(struct device *dev)
> +{
> + struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
> + struct usb_hcd *hcd = mtk->hcd;
> + int ret;
> +
> + ret = usb_phy_set_suspend(hcd->usb_phy, 1);
> + /* keep on power of mac to maintain register, and only close clock */
> + clk_disable_unprepare(mtk->sys_mac);
> + return ret;
> +}
> +
> +static int xhci_mtk_resume(struct device *dev)
> +{
> + struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
> + struct usb_hcd *hcd = mtk->hcd;
> + int ret;
> +
> + clk_prepare_enable(mtk->sys_mac);
> + ret = usb_phy_set_suspend(hcd->usb_phy, 0);
> +
> + return ret;
> +}
> +
> +static const struct dev_pm_ops xhci_mtk_pm_ops = {
> + SET_SYSTEM_SLEEP_PM_OPS(xhci_mtk_suspend, xhci_mtk_resume)
> +};
> +#define DEV_PM_OPS (&xhci_mtk_pm_ops)
> +#else
> +#define DEV_PM_OPS NULL
> +#endif /* CONFIG_PM */
> +
> +#ifdef CONFIG_OF
> +static const struct of_device_id mtk_xhci_of_match[] = {
> + { .compatible = "mediatek,mt8173-xhci"},
> + { },
> +};
> +MODULE_DEVICE_TABLE(of, mtk_xhci_of_match);
> +#endif
> +
> +static struct platform_driver mtk_xhci_driver = {
> + .probe = xhci_mtk_probe,
> + .remove = xhci_mtk_remove,
> + .driver = {
> + .name = "xhci-mtk",
> + .pm = DEV_PM_OPS,
> + .of_match_table = of_match_ptr(mtk_xhci_of_match),
> + },
> +};
> +
> +static int __init xhci_mtk_init(void)
> +{
> + xhci_init_driver(&xhci_mtk_hc_driver, &xhci_mtk_overrides);
> + return platform_driver_register(&mtk_xhci_driver);
> +}
> +module_init(xhci_mtk_init);
> +
> +static void __exit xhci_mtk_exit(void)
> +{
> + platform_driver_unregister(&mtk_xhci_driver);
> +}
> +module_exit(xhci_mtk_exit);
> +
> +MODULE_DESCRIPTION("MediaTek xHCI Host Controller Driver");
> +MODULE_LICENSE("GPL v2");
> +
> diff --git a/drivers/usb/host/xhci-mtk.h b/drivers/usb/host/xhci-mtk.h
> new file mode 100644
> index 0000000..e0fdd19
> --- /dev/null
> +++ b/drivers/usb/host/xhci-mtk.h
> @@ -0,0 +1,108 @@
> +/*
> + * Copyright (c) 2015 MediaTek Inc.
> + * Author:
> + * Zhigang.Wei <zhigang.wei@mediatek.com>
> + * Chunfeng.Yun <chunfeng.yun@mediatek.com>
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + */
> +
> +#ifndef _XHCI_MTK_H_
> +#define _XHCI_MTK_H_
> +
> +#include "xhci.h"
> +
> +/**
> + * To simplify scheduler algorithm, set a upper limit for ESIT,
> + * if a synchromous ep's ESIT is larger than @XHCI_MTK_MAX_ESIT,
> + * round down to the limit value, that means allocating more
> + * bandwidth to it.
> + */
> +#define XHCI_MTK_MAX_ESIT 64
> +
> +/**
> + * struct mu3h_sch_bw_info
> + * @bus_bw: array to keep track of bandwidth already used at each uframes
> + * @bw_ep_list: eps in the bandwidth domain
> + *
> + * treat a HS root port as a bandwidth domain, but treat a SS root port as
> + * two bandwidth domains, one for IN eps and another for OUT eps.
> + */
> +struct mu3h_sch_bw_info {
> + u32 bus_bw[XHCI_MTK_MAX_ESIT];
> + struct list_head bw_ep_list;
> +};
> +
> +/**
> + * struct mu3h_sch_ep_info
> + * @esit: unit is 125us, equal to 2 << Interval field in ep-context
> + * @num_budget_microframes: number of continuous uframes
> + * (@repeat==1) scheduled within the interval
> + * @ep: address of usb_host_endpoint
> + * @offset: which uframe of the interval that transfer should be
> + * scheduled first time within the interval
> + * @repeat: the time gap between two uframes that transfers are
> + * scheduled within a interval. in the simple algorithm, only
> + * assign 0 or 1 to it; 0 means using only one uframe in a
> + * interval, and1 means using @num_budget_microframes
> + * continuous uframes
> + * @pkts: number of packets to be transferred in the scheduled uframes
> + * @cs_count: number of CS that host will trigger
> + */
> +struct mu3h_sch_ep_info {
> + u32 ep_type;
> + u32 max_packet_size;
> + u32 esit;
> + u32 num_budget_microframes;
> + u32 bw_cost_per_microframe;
> + void *ep;
> + struct list_head endpoint;
> +
> + /* mtk xhci scheduling info */
> + u32 offset;
> + u32 repeat;
> + u32 pkts;
> + u32 cs_count;
> + u32 burst_mode;
> +};
> +
> +
> +#if IS_ENABLED(CONFIG_USB_XHCI_MTK)
> +
> +int xhci_mtk_add_ep_quirk(struct usb_hcd *hcd, struct usb_device *udev,
> + struct usb_host_endpoint *ep);
> +void xhci_mtk_drop_ep_quirk(struct usb_hcd *hcd, struct usb_device *udev,
> + struct usb_host_endpoint *ep);
> +u32 xhci_mtk_td_remainder_quirk(unsigned int td_running_total,
> + unsigned trb_buffer_length, struct urb *urb);
> +
> +#else
> +static inline int xhci_mtk_add_ep_quirk(struct usb_hcd *hcd,
> + struct usb_device *udev, struct usb_host_endpoint *ep)
> +{
> + return 0;
> +}
> +
> +static inline void xhci_mtk_drop_ep_quirk(struct usb_hcd *hcd,
> + struct usb_device *udev, struct usb_host_endpoint *ep)
> +{
> + return 0;
> +}
> +
> +static inline u32 xhci_mtk_td_remainder_quirk(unsigned int td_running_total,
> + unsigned trb_buffer_length, struct urb *urb)
> +{
> + return 0;
> +}
> +
> +#endif
> +
> +#endif /* _XHCI_MTK_H_ */
> diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
> index 94416ff..73997a0 100644
> --- a/drivers/usb/host/xhci-ring.c
> +++ b/drivers/usb/host/xhci-ring.c
> @@ -68,6 +68,7 @@
> #include <linux/slab.h>
> #include "xhci.h"
> #include "xhci-trace.h"
> +#include "xhci-mtk.h"
>
> /*
> * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
> @@ -3131,9 +3132,14 @@ static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
>
> /* Set the TRB length, TD size, and interrupter fields. */
> if (xhci->hci_version < 0x100) {
> - remainder = xhci_td_remainder(
> + if (xhci->quirks & XHCI_MTK_HOST) {
> + remainder = xhci_mtk_td_remainder_quirk(
> + running_total, trb_buff_len, urb);
> + } else {
> + remainder = xhci_td_remainder(
> urb->transfer_buffer_length -
> running_total);
> + }
> } else {
> remainder = xhci_v1_0_td_remainder(running_total,
> trb_buff_len, total_packet_count, urb,
> @@ -3286,9 +3292,14 @@ int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
>
> /* Set the TRB length, TD size, and interrupter fields. */
> if (xhci->hci_version < 0x100) {
> - remainder = xhci_td_remainder(
> + if (xhci->quirks & XHCI_MTK_HOST) {
> + remainder = xhci_mtk_td_remainder_quirk(
> + running_total, trb_buff_len, urb);
> + } else {
> + remainder = xhci_td_remainder(
> urb->transfer_buffer_length -
> running_total);
> + }
> } else {
> remainder = xhci_v1_0_td_remainder(running_total,
> trb_buff_len, total_packet_count, urb,
> @@ -3383,7 +3394,7 @@ int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
> field |= 0x1;
>
> /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
> - if (xhci->hci_version == 0x100) {
> + if ((xhci->hci_version == 0x100) || (xhci->quirks & XHCI_MTK_HOST)) {
> if (urb->transfer_buffer_length > 0) {
> if (setup->bRequestType & USB_DIR_IN)
> field |= TRB_TX_TYPE(TRB_DATA_IN);
> @@ -3407,8 +3418,14 @@ int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
> field = TRB_TYPE(TRB_DATA);
>
> length_field = TRB_LEN(urb->transfer_buffer_length) |
> - xhci_td_remainder(urb->transfer_buffer_length) |
> TRB_INTR_TARGET(0);
> +
> + if (xhci->quirks & XHCI_MTK_HOST)
> + length_field |= xhci_mtk_td_remainder_quirk(0,
> + urb->transfer_buffer_length, urb);
> + else
> + length_field |= xhci_td_remainder(urb->transfer_buffer_length);
> +
> if (urb->transfer_buffer_length > 0) {
> if (setup->bRequestType & USB_DIR_IN)
> field |= TRB_DIR_IN;
> @@ -3632,8 +3649,14 @@ static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
>
> /* Set the TRB length, TD size, & interrupter fields. */
> if (xhci->hci_version < 0x100) {
> - remainder = xhci_td_remainder(
> - td_len - running_total);
> + if (xhci->quirks & XHCI_MTK_HOST) {
> + remainder = xhci_mtk_td_remainder_quirk(
> + running_total, trb_buff_len,
> + urb);
> + } else {
> + remainder = xhci_td_remainder(
> + td_len - running_total);
> + }
> } else {
> remainder = xhci_v1_0_td_remainder(
> running_total, trb_buff_len,
> diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
> index 7da0d60..209fc8a 100644
> --- a/drivers/usb/host/xhci.c
> +++ b/drivers/usb/host/xhci.c
> @@ -31,6 +31,7 @@
>
> #include "xhci.h"
> #include "xhci-trace.h"
> +#include "xhci-mtk.h"
>
> #define DRIVER_AUTHOR "Sarah Sharp"
> #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
> @@ -623,7 +624,11 @@ int xhci_run(struct usb_hcd *hcd)
> "// Set the interrupt modulation register");
> temp = readl(&xhci->ir_set->irq_control);
> temp &= ~ER_IRQ_INTERVAL_MASK;
> - temp |= (u32) 160;
> + /*
> + * the increment interval is 8 times as much as that defined
> + * in xHCI spec on MTK's controller
> + */
> + temp |= (u32) ((xhci->quirks & XHCI_MTK_HOST) ? 20 : 160);
> writel(temp, &xhci->ir_set->irq_control);
>
> /* Set the HCD state before we enable the irqs */
> @@ -1688,6 +1693,9 @@ int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
>
> xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
>
> + if (xhci->quirks & XHCI_MTK_HOST)
> + xhci_mtk_drop_ep_quirk(hcd, udev, ep);
> +
> xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
> (unsigned int) ep->desc.bEndpointAddress,
> udev->slot_id,
> @@ -1783,6 +1791,15 @@ int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
> return -ENOMEM;
> }
>
> + if (xhci->quirks & XHCI_MTK_HOST) {
> + ret = xhci_mtk_add_ep_quirk(hcd, udev, ep);
> + if (ret < 0) {
> + xhci_free_or_cache_endpoint_ring(xhci,
> + virt_dev, ep_index);
> + return ret;
> + }
> + }
> +
> ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
> new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
>
> diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
> index 31e46cc..d257ce3 100644
> --- a/drivers/usb/host/xhci.h
> +++ b/drivers/usb/host/xhci.h
> @@ -1567,6 +1567,7 @@ struct xhci_hcd {
> /* For controllers with a broken beyond repair streams implementation */
> #define XHCI_BROKEN_STREAMS (1 << 19)
> #define XHCI_PME_STUCK_QUIRK (1 << 20)
> +#define XHCI_MTK_HOST (1 << 21)
> unsigned int num_active_eps;
> unsigned int limit_active_eps;
> /* There are two roothubs to keep track of bus suspend info for */
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v2 2/5] dt-bindings: Add a binding for Mediatek xHCI host controller
2015-07-10 8:31 ` Roger Quadros
@ 2015-07-14 2:36 ` chunfeng yun
2015-07-14 2:50 ` chunfeng yun
2015-07-20 14:24 ` chunfeng yun
2 siblings, 0 replies; 22+ messages in thread
From: chunfeng yun @ 2015-07-14 2:36 UTC (permalink / raw)
To: Roger Quadros
Cc: Mathias Nyman, Rob Herring, Mark Rutland, Matthias Brugger,
Felipe Balbi, Sascha Hauer, devicetree, linux-kernel,
linux-arm-kernel, linux-usb, linux-mediatek
hi Roger,
On Fri, 2015-07-10 at 11:31 +0300, Roger Quadros wrote:
> Hi,
>
> On 08/07/15 12:41, Chunfeng Yun wrote:
> > add a DT binding documentation of xHCI host controller for the
> > MT8173 SoC from Mediatek.
> >
> > Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> > ---
> > .../devicetree/bindings/usb/mt8173-xhci.txt | 27 ++++++++++++++++++++++
> > 1 file changed, 27 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/usb/mt8173-xhci.txt
> >
> > diff --git a/Documentation/devicetree/bindings/usb/mt8173-xhci.txt b/Documentation/devicetree/bindings/usb/mt8173-xhci.txt
> > new file mode 100644
> > index 0000000..94cec94
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/usb/mt8173-xhci.txt
> > @@ -0,0 +1,27 @@
> > +MT65XX xhci
> > +
> > +The device node for Mediatek SOC usb3.0 host controller
> > +
> > +Required properties:
> > + - compatible : supports "mediatek,mt8173-xhci"
> > + - reg : Offset and length of registers
> > + - interrupts : Interrupt mode, number and trigger mode
> > + - reg-vusb33-supply: regulator of usb avdd3.3v
> > + - reg-vbus-supply : regulator of vbus;
>
> General trend is to use <supply-name>-supply.
> We already know it is a regulator so no need to add "reg-"
>
> So those two can be
>
> vusb33-supply:
> vbus-supply:
>
I will adjust it later, thanks a lot
>
> > + - usb-phy : the phy that xhci will bind
> > + - usb3-lpm-capable: supports USB3 LPM
> > + - clocks : must support all clocks that xhci needs
> > + - clock-names: should be "sys_mac" for sys and mac clocks
> > +
> > +Example:
> > +usb: usb30@11270000 {
> > + compatible = "mediatek,mt8173-xhci";
> > + reg = <0 0x11270000 0 0x1000>;
> > + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
> > + reg-vusb33-supply = <&mt6397_vusb_reg>;
> > + reg-vbus-supply = <&usb_p1_vbus>;
> > + usb-phy = <&u3phy>;
> > + usb3-lpm-capable;
> > + clocks = <&topckgen CLK_TOP_USB30_SEL>;
> > + clock-names = "sys_mac";
> > +};
> >
>
> cheers,
> -roger
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v2 2/5] dt-bindings: Add a binding for Mediatek xHCI host controller
2015-07-10 8:31 ` Roger Quadros
2015-07-14 2:36 ` chunfeng yun
@ 2015-07-14 2:50 ` chunfeng yun
2015-07-20 14:24 ` chunfeng yun
2 siblings, 0 replies; 22+ messages in thread
From: chunfeng yun @ 2015-07-14 2:50 UTC (permalink / raw)
To: Roger Quadros
Cc: Mathias Nyman, Rob Herring, Mark Rutland, Matthias Brugger,
Felipe Balbi, Sascha Hauer, devicetree, linux-kernel,
linux-arm-kernel, linux-usb, linux-mediatek
hi Roger,
On Fri, 2015-07-10 at 11:31 +0300, Roger Quadros wrote:
> Hi,
>
> On 08/07/15 12:41, Chunfeng Yun wrote:
> > add a DT binding documentation of xHCI host controller for the
> > MT8173 SoC from Mediatek.
> >
> > Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> > ---
> > .../devicetree/bindings/usb/mt8173-xhci.txt | 27 ++++++++++++++++++++++
> > 1 file changed, 27 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/usb/mt8173-xhci.txt
> >
> > diff --git a/Documentation/devicetree/bindings/usb/mt8173-xhci.txt b/Documentation/devicetree/bindings/usb/mt8173-xhci.txt
> > new file mode 100644
> > index 0000000..94cec94
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/usb/mt8173-xhci.txt
> > @@ -0,0 +1,27 @@
> > +MT65XX xhci
> > +
> > +The device node for Mediatek SOC usb3.0 host controller
> > +
> > +Required properties:
> > + - compatible : supports "mediatek,mt8173-xhci"
> > + - reg : Offset and length of registers
> > + - interrupts : Interrupt mode, number and trigger mode
> > + - reg-vusb33-supply: regulator of usb avdd3.3v
> > + - reg-vbus-supply : regulator of vbus;
>
> General trend is to use <supply-name>-supply.
> We already know it is a regulator so no need to add "reg-"
>
> So those two can be
>
> vusb33-supply:
> vbus-supply:
>
I will adjust it later, thanks a lot
>
> > + - usb-phy : the phy that xhci will bind
> > + - usb3-lpm-capable: supports USB3 LPM
> > + - clocks : must support all clocks that xhci needs
> > + - clock-names: should be "sys_mac" for sys and mac clocks
> > +
> > +Example:
> > +usb: usb30@11270000 {
> > + compatible = "mediatek,mt8173-xhci";
> > + reg = <0 0x11270000 0 0x1000>;
> > + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
> > + reg-vusb33-supply = <&mt6397_vusb_reg>;
> > + reg-vbus-supply = <&usb_p1_vbus>;
> > + usb-phy = <&u3phy>;
> > + usb3-lpm-capable;
> > + clocks = <&topckgen CLK_TOP_USB30_SEL>;
> > + clock-names = "sys_mac";
> > +};
> >
>
> cheers,
> -roger
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v2 1/5] dt-bindings: Add usb3.0 phy binding for MT65xx SoCs
2015-07-10 5:10 ` Sascha Hauer
@ 2015-07-14 6:19 ` chunfeng yun
2015-07-14 7:45 ` Sascha Hauer
0 siblings, 1 reply; 22+ messages in thread
From: chunfeng yun @ 2015-07-14 6:19 UTC (permalink / raw)
To: Sascha Hauer
Cc: Mathias Nyman, Rob Herring, Mark Rutland, Matthias Brugger,
Felipe Balbi, devicetree, linux-kernel, linux-arm-kernel,
Roger Quadros, linux-usb, linux-mediatek
hi,
On Fri, 2015-07-10 at 07:10 +0200, Sascha Hauer wrote:
> On Wed, Jul 08, 2015 at 05:41:03PM +0800, Chunfeng Yun wrote:
> > add a DT binding documentation of usb3.0 phy for MT65xx
> > SoCs from Mediatek.
> >
> > Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> > ---
> > .../devicetree/bindings/usb/mt65xx-u3phy.txt | 34 ++++++++++++++++++++++
> > 1 file changed, 34 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/usb/mt65xx-u3phy.txt
> >
> > diff --git a/Documentation/devicetree/bindings/usb/mt65xx-u3phy.txt b/Documentation/devicetree/bindings/usb/mt65xx-u3phy.txt
> > new file mode 100644
> > index 0000000..056b2aa
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/usb/mt65xx-u3phy.txt
> > @@ -0,0 +1,34 @@
> > +MT65xx U3PHY
> > +
> > +The device node for Mediatek SOC usb3.0 phy
> > +
> > +Required properties:
> > + - compatible : Should be "mediatek,mt8173-u3phy"
> > + - reg : Offset and length of registers, the first is for mac domain,
> > + another for phy domain
> > + - power-domains: to enable usb's mtcmos
> > + - usb-wakeup-ctrl : to access usb wakeup control register
> > + - wakeup-src : 1: ip sleep wakeup mode; 2: line state wakeup mode; others
> > + means don't enable wakeup source of usb
> > + - u2port-num : number of usb2.0 ports to support which should be 1 or 2
> > + - clocks : must support all clocks that phy need
> > + - clock-names: should be "wakeup_deb_p0", "wakeup_deb_p1" for wakeup
> > + debounce control clocks, and "u3phya_ref" for u3phya reference clock.
> > +
> > +Example:
> > +
> > +u3phy: usb-phy@11271000 {
> > + compatible = "mediatek,mt8173-u3phy";
> > + reg = <0 0x11271000 0 0x3000>,
> > + <0 0x11280000 0 0x20000>;
>
> 0x11271000 is the register space the xhci controller takes. You should
> not expose the same register space to two different drivers.
>
usb: usb30@11270000 {
compatible = "mediatek,mt8173-xhci";
reg = <0 0x11270000 0 0x1000>;
the size of xhci register space is 0x1000, and the range is
[0x11270000, 0x11271000 - 1], so the address of 0x11271000 is not
included.
> Sascha
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v2 1/5] dt-bindings: Add usb3.0 phy binding for MT65xx SoCs
2015-07-14 6:19 ` chunfeng yun
@ 2015-07-14 7:45 ` Sascha Hauer
2015-07-15 12:33 ` chunfeng yun
0 siblings, 1 reply; 22+ messages in thread
From: Sascha Hauer @ 2015-07-14 7:45 UTC (permalink / raw)
To: chunfeng yun
Cc: Mathias Nyman, Rob Herring, Mark Rutland, Matthias Brugger,
Felipe Balbi, devicetree, linux-kernel, linux-arm-kernel,
Roger Quadros, linux-usb, linux-mediatek
On Tue, Jul 14, 2015 at 02:19:51PM +0800, chunfeng yun wrote:
> hi,
> On Fri, 2015-07-10 at 07:10 +0200, Sascha Hauer wrote:
> > On Wed, Jul 08, 2015 at 05:41:03PM +0800, Chunfeng Yun wrote:
> > > add a DT binding documentation of usb3.0 phy for MT65xx
> > > SoCs from Mediatek.
> > >
> > > Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> > > ---
> > > .../devicetree/bindings/usb/mt65xx-u3phy.txt | 34 ++++++++++++++++++++++
> > > 1 file changed, 34 insertions(+)
> > > create mode 100644 Documentation/devicetree/bindings/usb/mt65xx-u3phy.txt
> > >
> > > diff --git a/Documentation/devicetree/bindings/usb/mt65xx-u3phy.txt b/Documentation/devicetree/bindings/usb/mt65xx-u3phy.txt
> > > new file mode 100644
> > > index 0000000..056b2aa
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/usb/mt65xx-u3phy.txt
> > > @@ -0,0 +1,34 @@
> > > +MT65xx U3PHY
> > > +
> > > +The device node for Mediatek SOC usb3.0 phy
> > > +
> > > +Required properties:
> > > + - compatible : Should be "mediatek,mt8173-u3phy"
> > > + - reg : Offset and length of registers, the first is for mac domain,
> > > + another for phy domain
> > > + - power-domains: to enable usb's mtcmos
> > > + - usb-wakeup-ctrl : to access usb wakeup control register
> > > + - wakeup-src : 1: ip sleep wakeup mode; 2: line state wakeup mode; others
> > > + means don't enable wakeup source of usb
> > > + - u2port-num : number of usb2.0 ports to support which should be 1 or 2
> > > + - clocks : must support all clocks that phy need
> > > + - clock-names: should be "wakeup_deb_p0", "wakeup_deb_p1" for wakeup
> > > + debounce control clocks, and "u3phya_ref" for u3phya reference clock.
> > > +
> > > +Example:
> > > +
> > > +u3phy: usb-phy@11271000 {
> > > + compatible = "mediatek,mt8173-u3phy";
> > > + reg = <0 0x11271000 0 0x3000>,
> > > + <0 0x11280000 0 0x20000>;
> >
> > 0x11271000 is the register space the xhci controller takes. You should
> > not expose the same register space to two different drivers.
> >
>
> usb: usb30@11270000 {
> compatible = "mediatek,mt8173-xhci";
> reg = <0 0x11270000 0 0x1000>;
>
> the size of xhci register space is 0x1000, and the range is
> [0x11270000, 0x11271000 - 1], so the address of 0x11271000 is not
> included.
Indeed, you are right. Nevertheless my datasheet lists these resources:
0x11270000 - 0x1127ffff: SSUSB CSR
0x11280000 - 0x1128ffff: SSUSB SIF
0x11290000 - 0x1129ffff: SSUSB
It seems that with the current binding you are not modelling the
hardware but something that reflects your current implementation. This
is not a good sign. Normally I would expect device nodes that match the
above resources, but your USB phy spans most of the SSUSB CSR register
space and both the SSUSB SIF and SSUSB regster space. I think it would
be good if you could give an overview over the USB hardware and explain
why you have to violate the above resources.
Also something to consider: Is your binding suitable for adding OTG
support later? You don't have to add OTG support to the Kernel now,
but your binding should be suitable to add it later.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v2 5/5] arm64: dts: mediatek: add xHCI & usb phy for mt8173
2015-07-08 9:41 ` [PATCH v2 5/5] arm64: dts: mediatek: add xHCI & usb phy for mt8173 Chunfeng Yun
@ 2015-07-14 10:12 ` Daniel Kurtz
2015-07-20 14:39 ` chunfeng yun
0 siblings, 1 reply; 22+ messages in thread
From: Daniel Kurtz @ 2015-07-14 10:12 UTC (permalink / raw)
To: Chunfeng Yun
Cc: Mathias Nyman, Mark Rutland, open list:OPEN FIRMWARE AND...,
Sascha Hauer, linux-usb, linux-kernel, Felipe Balbi, Rob Herring,
linux-mediatek, Matthias Brugger, linux-arm-kernel,
Roger Quadros
Hi Chunfeng,
On Wed, Jul 8, 2015 at 5:41 PM, Chunfeng Yun <chunfeng.yun@mediatek.com> wrote:
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 15 +++++++++++++++
> arch/arm64/boot/dts/mediatek/mt8173.dtsi | 27 +++++++++++++++++++++++++++
> 2 files changed, 42 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
> index f433c21..cb63dc3 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
> +++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
> @@ -13,6 +13,7 @@
> */
>
> /dts-v1/;
> +#include <dt-bindings/gpio/gpio.h>
> #include "mt8173.dtsi"
>
> / {
> @@ -32,6 +33,15 @@
> };
>
> chosen { };
> +
> + usb_p1_vbus: fixedregulator@0 {
Why @0 ?
> + compatible = "regulator-fixed";
> + regulator-name = "usb_vbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + gpio = <&pio 130 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> };
>
> &pwrap {
> @@ -211,3 +221,8 @@
> &uart0 {
> status = "okay";
> };
> +
> +&usb {
> + reg-vusb33-supply = <&mt6397_vusb_reg>;
> + reg-vbus-supply = <&usb_p1_vbus>;
> +};
> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> index 0696f8f..452bd0a 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> @@ -15,6 +15,7 @@
> #include <dt-bindings/interrupt-controller/irq.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/reset-controller/mt8173-resets.h>
> +#include <dt-bindings/power/mt8173-power.h>
Sort alphabetically, so:
power before reset
> #include "mt8173-pinfunc.h"
>
> / {
> @@ -393,6 +394,32 @@
> #size-cells = <0>;
> status = "disabled";
> };
> +
> + usb: usb30@11270000 {
> + compatible = "mediatek,mt8173-xhci";
> + reg = <0 0x11270000 0 0x1000>;
> + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
> + usb-phy = <&u3phy>;
> + usb3-lpm-capable;
> + clocks = <&topckgen CLK_TOP_USB30_SEL>;
> + clock-names = "sys_mac";
> + };
> +
> + u3phy: usb-phy@11271000 {
> + compatible = "mediatek,mt8173-u3phy";
> + reg = <0 0x11271000 0 0x3000>,
> + <0 0x11280000 0 0x20000>;
> + power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
> + usb-wakeup-ctrl = <&pericfg>;
> + wakeup-src = <1>;
> + u2port-num = <2>;
Mediatek specific properties should be prefixed with "mediatek,".
I also find it nicer if you put the standard properties first:
(compatible, reg, clocks, clock-names, power-domains)
then device specific properties:
(usb-wakeup-ctrl, wakeup-src, u2port-num)
and then the final:
status="disabled";
This last is currently missing, so please add it, too.
Also, is there some pinctrl settings that must be set for USB?
Lastly, I could not quite figure out which patch this set was based on.
Patch [0] mentions v4.2-rc1, however, the .dts changes in this patch
did not apply cleanly.
Perhaps it was based on a particular patch of Matthias tree?
Thanks!
-Dan
> + clocks = <&pericfg CLK_PERI_USB0>,
> + <&pericfg CLK_PERI_USB1>,
> + <&apmixedsys CLK_APMIXED_REF2USB_TX>;
> + clock-names = "wakeup_deb_p0",
> + "wakeup_deb_p1",
> + "u3phya_ref";
> + };
> };
> };
>
> --
> 1.8.1.1.dirty
>
>
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v2 1/5] dt-bindings: Add usb3.0 phy binding for MT65xx SoCs
2015-07-14 7:45 ` Sascha Hauer
@ 2015-07-15 12:33 ` chunfeng yun
0 siblings, 0 replies; 22+ messages in thread
From: chunfeng yun @ 2015-07-15 12:33 UTC (permalink / raw)
To: Sascha Hauer
Cc: Mathias Nyman, Rob Herring, Mark Rutland, Matthias Brugger,
Felipe Balbi, devicetree, linux-kernel, linux-arm-kernel,
Roger Quadros, linux-usb, linux-mediatek
On Tue, 2015-07-14 at 09:45 +0200, Sascha Hauer wrote:
> On Tue, Jul 14, 2015 at 02:19:51PM +0800, chunfeng yun wrote:
> > hi,
> > On Fri, 2015-07-10 at 07:10 +0200, Sascha Hauer wrote:
> > > On Wed, Jul 08, 2015 at 05:41:03PM +0800, Chunfeng Yun wrote:
> > > > add a DT binding documentation of usb3.0 phy for MT65xx
> > > > SoCs from Mediatek.
> > > >
> > > > Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> > > > ---
> > > > .../devicetree/bindings/usb/mt65xx-u3phy.txt | 34 ++++++++++++++++++++++
> > > > 1 file changed, 34 insertions(+)
> > > > create mode 100644 Documentation/devicetree/bindings/usb/mt65xx-u3phy.txt
> > > >
> > > > diff --git a/Documentation/devicetree/bindings/usb/mt65xx-u3phy.txt b/Documentation/devicetree/bindings/usb/mt65xx-u3phy.txt
> > > > new file mode 100644
> > > > index 0000000..056b2aa
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/usb/mt65xx-u3phy.txt
> > > > @@ -0,0 +1,34 @@
> > > > +MT65xx U3PHY
> > > > +
> > > > +The device node for Mediatek SOC usb3.0 phy
> > > > +
> > > > +Required properties:
> > > > + - compatible : Should be "mediatek,mt8173-u3phy"
> > > > + - reg : Offset and length of registers, the first is for mac domain,
> > > > + another for phy domain
> > > > + - power-domains: to enable usb's mtcmos
> > > > + - usb-wakeup-ctrl : to access usb wakeup control register
> > > > + - wakeup-src : 1: ip sleep wakeup mode; 2: line state wakeup mode; others
> > > > + means don't enable wakeup source of usb
> > > > + - u2port-num : number of usb2.0 ports to support which should be 1 or 2
> > > > + - clocks : must support all clocks that phy need
> > > > + - clock-names: should be "wakeup_deb_p0", "wakeup_deb_p1" for wakeup
> > > > + debounce control clocks, and "u3phya_ref" for u3phya reference clock.
> > > > +
> > > > +Example:
> > > > +
> > > > +u3phy: usb-phy@11271000 {
> > > > + compatible = "mediatek,mt8173-u3phy";
> > > > + reg = <0 0x11271000 0 0x3000>,
> > > > + <0 0x11280000 0 0x20000>;
> > >
> > > 0x11271000 is the register space the xhci controller takes. You should
> > > not expose the same register space to two different drivers.
> > >
> >
> > usb: usb30@11270000 {
> > compatible = "mediatek,mt8173-xhci";
> > reg = <0 0x11270000 0 0x1000>;
> >
> > the size of xhci register space is 0x1000, and the range is
> > [0x11270000, 0x11271000 - 1], so the address of 0x11271000 is not
> > included.
>
> Indeed, you are right. Nevertheless my datasheet lists these resources:
>
> 0x11270000 - 0x1127ffff: SSUSB CSR
> 0x11280000 - 0x1128ffff: SSUSB SIF
> 0x11290000 - 0x1129ffff: SSUSB
>
> It seems that with the current binding you are not modelling the
> hardware but something that reflects your current implementation. This
> is not a good sign. Normally I would expect device nodes that match the
> above resources, but your USB phy spans most of the SSUSB CSR register
> space and both the SSUSB SIF and SSUSB regster space. I think it would
> be good if you could give an overview over the USB hardware and explain
> why you have to violate the above resources.
>
> Also something to consider: Is your binding suitable for adding OTG
> support later? You don't have to add OTG support to the Kernel now,
> but your binding should be suitable to add it later.
>
> Sascha
>
I agree with you, but timing parameter settings of super speed port are
put in [0x11272400 - 0x11272800], which is not included by xhci register
space. SSUSB SIF includes some control and status registers of each
ports and also OTG etc. It is better to put them into the node of gadget
device node which is not supported now, so put them into phy device
node.
Do you have any good idea to deal with the special case?
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v2 2/5] dt-bindings: Add a binding for Mediatek xHCI host controller
2015-07-10 8:31 ` Roger Quadros
2015-07-14 2:36 ` chunfeng yun
2015-07-14 2:50 ` chunfeng yun
@ 2015-07-20 14:24 ` chunfeng yun
2 siblings, 0 replies; 22+ messages in thread
From: chunfeng yun @ 2015-07-20 14:24 UTC (permalink / raw)
To: Roger Quadros
Cc: Mathias Nyman, Rob Herring, Mark Rutland, Matthias Brugger,
Felipe Balbi, Sascha Hauer, devicetree, linux-kernel,
linux-arm-kernel, linux-usb, linux-mediatek
On Fri, 2015-07-10 at 11:31 +0300, Roger Quadros wrote:
> Hi,
>
> On 08/07/15 12:41, Chunfeng Yun wrote:
> > add a DT binding documentation of xHCI host controller for the
> > MT8173 SoC from Mediatek.
> >
> > Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> > ---
> > .../devicetree/bindings/usb/mt8173-xhci.txt | 27 ++++++++++++++++++++++
> > 1 file changed, 27 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/usb/mt8173-xhci.txt
> >
> > diff --git a/Documentation/devicetree/bindings/usb/mt8173-xhci.txt b/Documentation/devicetree/bindings/usb/mt8173-xhci.txt
> > new file mode 100644
> > index 0000000..94cec94
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/usb/mt8173-xhci.txt
> > @@ -0,0 +1,27 @@
> > +MT65XX xhci
> > +
> > +The device node for Mediatek SOC usb3.0 host controller
> > +
> > +Required properties:
> > + - compatible : supports "mediatek,mt8173-xhci"
> > + - reg : Offset and length of registers
> > + - interrupts : Interrupt mode, number and trigger mode
> > + - reg-vusb33-supply: regulator of usb avdd3.3v
> > + - reg-vbus-supply : regulator of vbus;
>
> General trend is to use <supply-name>-supply.
> We already know it is a regulator so no need to add "reg-"
>
> So those two can be
>
> vusb33-supply:
> vbus-supply:
>
Ok, thanks
>
> > + - usb-phy : the phy that xhci will bind
> > + - usb3-lpm-capable: supports USB3 LPM
> > + - clocks : must support all clocks that xhci needs
> > + - clock-names: should be "sys_mac" for sys and mac clocks
> > +
> > +Example:
> > +usb: usb30@11270000 {
> > + compatible = "mediatek,mt8173-xhci";
> > + reg = <0 0x11270000 0 0x1000>;
> > + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
> > + reg-vusb33-supply = <&mt6397_vusb_reg>;
> > + reg-vbus-supply = <&usb_p1_vbus>;
> > + usb-phy = <&u3phy>;
> > + usb3-lpm-capable;
> > + clocks = <&topckgen CLK_TOP_USB30_SEL>;
> > + clock-names = "sys_mac";
> > +};
> >
>
> cheers,
> -roger
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v2 5/5] arm64: dts: mediatek: add xHCI & usb phy for mt8173
2015-07-14 10:12 ` Daniel Kurtz
@ 2015-07-20 14:39 ` chunfeng yun
2015-07-20 14:51 ` Yingjoe Chen
0 siblings, 1 reply; 22+ messages in thread
From: chunfeng yun @ 2015-07-20 14:39 UTC (permalink / raw)
To: Daniel Kurtz
Cc: Mathias Nyman, Mark Rutland, open list:OPEN FIRMWARE AND...,
Sascha Hauer, linux-usb, linux-kernel, Felipe Balbi, Rob Herring,
linux-mediatek, Matthias Brugger, linux-arm-kernel,
Roger Quadros
Hi,
On Tue, 2015-07-14 at 18:12 +0800, Daniel Kurtz wrote:
> Hi Chunfeng,
>
> On Wed, Jul 8, 2015 at 5:41 PM, Chunfeng Yun <chunfeng.yun@mediatek.com> wrote:
> > Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 15 +++++++++++++++
> > arch/arm64/boot/dts/mediatek/mt8173.dtsi | 27 +++++++++++++++++++++++++++
> > 2 files changed, 42 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
> > index f433c21..cb63dc3 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
> > +++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
> > @@ -13,6 +13,7 @@
> > */
> >
> > /dts-v1/;
> > +#include <dt-bindings/gpio/gpio.h>
> > #include "mt8173.dtsi"
> >
> > / {
> > @@ -32,6 +33,15 @@
> > };
> >
> > chosen { };
> > +
> > + usb_p1_vbus: fixedregulator@0 {
>
> Why @0 ?
It is the first fixed regulator, so set it to 0 as a index.
I will remove it later
>
> > + compatible = "regulator-fixed";
> > + regulator-name = "usb_vbus";
> > + regulator-min-microvolt = <5000000>;
> > + regulator-max-microvolt = <5000000>;
> > + gpio = <&pio 130 GPIO_ACTIVE_HIGH>;
> > + enable-active-high;
> > + };
> > };
> >
> > &pwrap {
> > @@ -211,3 +221,8 @@
> > &uart0 {
> > status = "okay";
> > };
> > +
> > +&usb {
> > + reg-vusb33-supply = <&mt6397_vusb_reg>;
> > + reg-vbus-supply = <&usb_p1_vbus>;
> > +};
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > index 0696f8f..452bd0a 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > @@ -15,6 +15,7 @@
> > #include <dt-bindings/interrupt-controller/irq.h>
> > #include <dt-bindings/interrupt-controller/arm-gic.h>
> > #include <dt-bindings/reset-controller/mt8173-resets.h>
> > +#include <dt-bindings/power/mt8173-power.h>
>
> Sort alphabetically, so:
> power before reset
>
Ok
> > #include "mt8173-pinfunc.h"
> >
> > / {
> > @@ -393,6 +394,32 @@
> > #size-cells = <0>;
> > status = "disabled";
> > };
> > +
> > + usb: usb30@11270000 {
> > + compatible = "mediatek,mt8173-xhci";
> > + reg = <0 0x11270000 0 0x1000>;
> > + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
> > + usb-phy = <&u3phy>;
> > + usb3-lpm-capable;
> > + clocks = <&topckgen CLK_TOP_USB30_SEL>;
> > + clock-names = "sys_mac";
> > + };
> > +
> > + u3phy: usb-phy@11271000 {
> > + compatible = "mediatek,mt8173-u3phy";
> > + reg = <0 0x11271000 0 0x3000>,
> > + <0 0x11280000 0 0x20000>;
> > + power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
> > + usb-wakeup-ctrl = <&pericfg>;
> > + wakeup-src = <1>;
> > + u2port-num = <2>;
>
> Mediatek specific properties should be prefixed with "mediatek,".
> I also find it nicer if you put the standard properties first:
> (compatible, reg, clocks, clock-names, power-domains)
> then device specific properties:
> (usb-wakeup-ctrl, wakeup-src, u2port-num)
> and then the final:
> status="disabled";
>
> This last is currently missing, so please add it, too.
>
I will revise it. Thanks a lot.
> Also, is there some pinctrl settings that must be set for USB?
>
There is no special pinctrl setting for USB on EVB board on which driver
is tested.
> Lastly, I could not quite figure out which patch this set was based on.
> Patch [0] mentions v4.2-rc1, however, the .dts changes in this patch
> did not apply cleanly.
> Perhaps it was based on a particular patch of Matthias tree?
>
Yes, it is.
> Thanks!
> -Dan
>
> > + clocks = <&pericfg CLK_PERI_USB0>,
> > + <&pericfg CLK_PERI_USB1>,
> > + <&apmixedsys CLK_APMIXED_REF2USB_TX>;
> > + clock-names = "wakeup_deb_p0",
> > + "wakeup_deb_p1",
> > + "u3phya_ref";
> > + };
> > };
> > };
> >
> > --
> > 1.8.1.1.dirty
> >
> >
> > _______________________________________________
> > Linux-mediatek mailing list
> > Linux-mediatek@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v2 5/5] arm64: dts: mediatek: add xHCI & usb phy for mt8173
2015-07-20 14:39 ` chunfeng yun
@ 2015-07-20 14:51 ` Yingjoe Chen
2015-07-20 14:59 ` Daniel Kurtz
0 siblings, 1 reply; 22+ messages in thread
From: Yingjoe Chen @ 2015-07-20 14:51 UTC (permalink / raw)
To: chunfeng yun
Cc: Daniel Kurtz, Mark Rutland, open list:OPEN FIRMWARE AND...,
Mathias Nyman, Sascha Hauer, linux-usb, linux-kernel,
Felipe Balbi, Rob Herring, linux-mediatek, Matthias Brugger,
linux-arm-kernel, Roger Quadros
Hi Daniel, Chunfeng,
On Mon, 2015-07-20 at 22:39 +0800, chunfeng yun wrote:
> Hi,
>
> On Tue, 2015-07-14 at 18:12 +0800, Daniel Kurtz wrote:
<...>
> > > +
> > > + usb_p1_vbus: fixedregulator@0 {
> >
> > Why @0 ?
> It is the first fixed regulator, so set it to 0 as a index.
> I will remove it later
Since this name should be unique, I think we should use gpio number as
address for fixedregulator in case we need other fixedregulators. So
this could be:
usb_p1_vbus: fixedregulator@130 {
Also, we should sort according to the address(gpio number) for these
nodes. Does this make sense?
Joe.C
> >
> > > + compatible = "regulator-fixed";
> > > + regulator-name = "usb_vbus";
> > > + regulator-min-microvolt = <5000000>;
> > > + regulator-max-microvolt = <5000000>;
> > > + gpio = <&pio 130 GPIO_ACTIVE_HIGH>;
> > > + enable-active-high;
> > > + };
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v2 4/5] xhci: mediatek: support MTK xHCI host controller
2015-07-13 14:52 ` John Crispin
@ 2015-07-20 14:51 ` chunfeng yun
0 siblings, 0 replies; 22+ messages in thread
From: chunfeng yun @ 2015-07-20 14:51 UTC (permalink / raw)
To: John Crispin
Cc: Mathias Nyman, Mark Rutland, devicetree, Sascha Hauer, linux-usb,
linux-kernel, Felipe Balbi, Rob Herring, linux-mediatek,
Matthias Brugger, linux-arm-kernel, Roger Quadros
On Mon, 2015-07-13 at 16:52 +0200, John Crispin wrote:
> Hi
>
> there is a cross dependency between the modules. xhci-mtk.ko requires
> xhci.ko to be loaded. however this will look for xhci_mtk_add_ep_quirk()
> which is part of xhci-mtk. the modules will build but are not run time
> loadable.
>
> John
>
I seperate the quirk functions called by xhci_hcd.ko from xhci-mtk.c
into another C file to fix up the issue.
Thanks
> On 08/07/2015 11:41, Chunfeng Yun wrote:
> > MTK xhci host controller defines some extra SW scheduling
> > parameters for HW to minimize the scheduling effort for
> > synchronous and interrupt endpoints. The parameters are
> > put into reseved DWs of slot context and endpoint context
> >
> > Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> > ---
> > drivers/usb/host/Kconfig | 9 +
> > drivers/usb/host/Makefile | 1 +
> > drivers/usb/host/xhci-mtk.c | 814 +++++++++++++++++++++++++++++++++++++++++++
> > drivers/usb/host/xhci-mtk.h | 108 ++++++
> > drivers/usb/host/xhci-ring.c | 35 +-
> > drivers/usb/host/xhci.c | 19 +-
> > drivers/usb/host/xhci.h | 1 +
> > 7 files changed, 980 insertions(+), 7 deletions(-)
> > create mode 100644 drivers/usb/host/xhci-mtk.c
> > create mode 100644 drivers/usb/host/xhci-mtk.h
> >
> > diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
> > index 8afc3c1..2202c68 100644
> > --- a/drivers/usb/host/Kconfig
> > +++ b/drivers/usb/host/Kconfig
> > @@ -34,6 +34,15 @@ config USB_XHCI_PCI
> > config USB_XHCI_PLATFORM
> > tristate
> >
> > +config USB_XHCI_MTK
> > + tristate "xHCI support for Mediatek MT65xx"
> > + select USB_XHCI_PLATFORM
> > + depends on ARCH_MEDIATEK || COMPILE_TEST
> > + ---help---
> > + Say 'Y' to enable the support for the xHCI host controller
> > + found in Mediatek MT65xx SoCs.
> > + If unsure, say N.
> > +
> > config USB_XHCI_MVEBU
> > tristate "xHCI support for Marvell Armada 375/38x"
> > select USB_XHCI_PLATFORM
> > diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
> > index 754efaa..90c6eb2 100644
> > --- a/drivers/usb/host/Makefile
> > +++ b/drivers/usb/host/Makefile
> > @@ -30,6 +30,7 @@ endif
> >
> > obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
> > obj-$(CONFIG_USB_XHCI_PLATFORM) += xhci-plat-hcd.o
> > +obj-$(CONFIG_USB_XHCI_MTK) += xhci-mtk.o
> >
> > obj-$(CONFIG_USB_EHCI_HCD) += ehci-hcd.o
> > obj-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
> > diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c
> > new file mode 100644
> > index 0000000..45f0606
> > --- /dev/null
> > +++ b/drivers/usb/host/xhci-mtk.c
> > @@ -0,0 +1,814 @@
> > +/*
> > + * Copyright (c) 2015 MediaTek Inc.
> > + * Author:
> > + * Zhigang.Wei <zhigang.wei@mediatek.com>
> > + * Chunfeng.Yun <chunfeng.yun@mediatek.com>
> > + *
> > + * This software is licensed under the terms of the GNU General Public
> > + * License version 2, as published by the Free Software Foundation, and
> > + * may be copied, distributed, and modified under those terms.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + *
> > + */
> > +
> > +#include <linux/kernel.h>
> > +#include <linux/clk.h>
> > +#include <linux/dma-mapping.h>
> > +#include <linux/module.h>
> > +#include <linux/of.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/usb/phy.h>
> > +#include <linux/slab.h>
> > +#include <linux/usb/xhci_pdriver.h>
> > +#include <linux/regulator/consumer.h>
> > +#include <linux/pm_runtime.h>
> > +
> > +#include "xhci.h"
> > +#include "xhci-mtk.h"
> > +
> > +
> > +#define SS_BW_BOUNDARY 51000
> > +/* table 5-5. High-speed Isoc Transaction Limits in usb_20 spec */
> > +#define HS_BW_BOUNDARY 6144
> > +/* usb2 spec section11.18.1: at most 188 FS bytes per microframe */
> > +#define FS_PAYLOAD_MAX 188
> > +
> > +/* mtk scheduler bitmasks */
> > +#define EP_BPKTS(p) ((p) & 0x3f)
> > +#define EP_BCSCOUNT(p) (((p) & 0x7) << 8)
> > +#define EP_BBM(p) ((p) << 11)
> > +#define EP_BOFFSET(p) ((p) & 0x3fff)
> > +#define EP_BREPEAT(p) (((p) & 0x7fff) << 16)
> > +
> > +
> > +struct xhci_hcd_mtk {
> > + struct device *dev;
> > + struct usb_hcd *hcd;
> > + struct mu3h_sch_bw_info *sch_array;
> > + struct regulator *vusb33;
> > + struct regulator *vbus;
> > + struct clk *sys_mac; /* sys and mac clock */
> > +};
> > +
> > +
> > +static int is_fs_or_ls(enum usb_device_speed speed)
> > +{
> > + return speed == USB_SPEED_FULL || speed == USB_SPEED_LOW;
> > +}
> > +
> > +static int get_bw_index(struct xhci_hcd *xhci, struct usb_device *udev,
> > + struct usb_host_endpoint *ep)
> > +{
> > + int bw_index;
> > + int port_id;
> > + struct xhci_virt_device *virt_dev;
> > +
> > + virt_dev = xhci->devs[udev->slot_id];
> > + port_id = virt_dev->real_port;
> > +
> > + if (udev->speed == USB_SPEED_SUPER) {
> > + if (usb_endpoint_dir_out(&ep->desc))
> > + bw_index = (port_id - 1) * 2;
> > + else
> > + bw_index = (port_id - 1) * 2 + 1;
> > + } else {
> > + bw_index = port_id + xhci->num_usb3_ports - 1;
> > + }
> > +
> > + return bw_index;
> > +}
> > +
> > +
> > +static void setup_sch_info(struct usb_device *udev,
> > + struct xhci_ep_ctx *ep_ctx, struct mu3h_sch_ep_info *sch_ep)
> > +{
> > + u32 ep_type;
> > + u32 ep_interval;
> > + u32 max_packet_size;
> > + u32 max_burst;
> > + u32 mult;
> > + u32 esit_pkts;
> > +
> > + ep_type = CTX_TO_EP_TYPE(le32_to_cpu(ep_ctx->ep_info2));
> > + ep_interval = CTX_TO_EP_INTERVAL(le32_to_cpu(ep_ctx->ep_info));
> > + max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
> > + max_burst = CTX_TO_MAX_BURST(le32_to_cpu(ep_ctx->ep_info2));
> > + mult = CTX_TO_EP_MULT(le32_to_cpu(ep_ctx->ep_info));
> > + pr_debug("%s: max_burst = %d, mult = %d\n", __func__, max_burst, mult);
> > +
> > + sch_ep->ep_type = ep_type;
> > + sch_ep->max_packet_size = max_packet_size;
> > + sch_ep->esit = 1 << ep_interval;
> > + sch_ep->offset = 0;
> > + sch_ep->burst_mode = 0;
> > +
> > + if (udev->speed == USB_SPEED_HIGH) {
> > + sch_ep->cs_count = 0;
> > + /*
> > + * usb_20 spec section5.9
> > + * a single microframe is enough for HS synchromous endpoints
> > + * in a interval
> > + */
> > + sch_ep->num_budget_microframes = 1;
> > + sch_ep->repeat = 0;
> > + /*
> > + * xHCI spec section6.2.3.4
> > + * @max_busrt is the number of additional transactions
> > + * opportunities per microframe
> > + */
> > + sch_ep->pkts = max_burst + 1;
> > + sch_ep->bw_cost_per_microframe = max_packet_size * sch_ep->pkts;
> > + } else if (udev->speed == USB_SPEED_SUPER) {
> > + /* usb3_r1 spec section4.4.7 & 4.4.8 */
> > + sch_ep->cs_count = 0;
> > + esit_pkts = (mult + 1) * (max_burst + 1);
> > + if (ep_type == INT_IN_EP || ep_type == INT_OUT_EP) {
> > + sch_ep->pkts = esit_pkts;
> > + sch_ep->num_budget_microframes = 1;
> > + sch_ep->repeat = 0;
> > + }
> > +
> > + if (ep_type == ISOC_IN_EP || ep_type == ISOC_OUT_EP) {
> > + if (esit_pkts <= sch_ep->esit)
> > + sch_ep->pkts = 1;
> > + else
> > + sch_ep->pkts = roundup_pow_of_two(esit_pkts)
> > + / sch_ep->esit;
> > +
> > + sch_ep->num_budget_microframes =
> > + DIV_ROUND_UP(esit_pkts, sch_ep->pkts);
> > +
> > + if (sch_ep->num_budget_microframes > 1)
> > + sch_ep->repeat = 1;
> > + else
> > + sch_ep->repeat = 0;
> > + }
> > + sch_ep->bw_cost_per_microframe = max_packet_size * sch_ep->pkts;
> > + } else if (is_fs_or_ls(udev->speed)) {
> > + /*
> > + * usb_20 spec section11.18.4
> > + * assume worst cases
> > + */
> > + sch_ep->repeat = 0;
> > + sch_ep->pkts = 1; /* at most one packet for each microframe */
> > + if (ep_type == INT_IN_EP || ep_type == INT_OUT_EP) {
> > + sch_ep->cs_count = 3; /* at most need 3 CS*/
> > + /* one for SS and one for budgeted transaction */
> > + sch_ep->num_budget_microframes = sch_ep->cs_count + 2;
> > + sch_ep->bw_cost_per_microframe = max_packet_size;
> > + }
> > + if (ep_type == ISOC_OUT_EP) {
> > + /* must never schedule a cs ISOC OUT ep */
> > + sch_ep->cs_count = 0;
> > + /*
> > + * the best case FS budget assumes that 188 FS bytes
> > + * occur in each microframe
> > + */
> > + sch_ep->num_budget_microframes = DIV_ROUND_UP(
> > + sch_ep->max_packet_size, FS_PAYLOAD_MAX);
> > + sch_ep->bw_cost_per_microframe = FS_PAYLOAD_MAX;
> > + }
> > + if (ep_type == ISOC_IN_EP) {
> > + /* at most need additional two CS. */
> > + sch_ep->cs_count = DIV_ROUND_UP(
> > + sch_ep->max_packet_size, FS_PAYLOAD_MAX) + 2;
> > + sch_ep->num_budget_microframes = sch_ep->cs_count + 2;
> > + sch_ep->bw_cost_per_microframe = FS_PAYLOAD_MAX;
> > + }
> > + }
> > +}
> > +
> > +/* Get maximum bandwidth when we schedule at offset slot. */
> > +static u32 get_max_bw(struct mu3h_sch_bw_info *sch_bw,
> > + struct mu3h_sch_ep_info *sch_ep, u32 offset)
> > +{
> > + u32 num_esit;
> > + u32 max_bw = 0;
> > + int i;
> > + int j;
> > +
> > + num_esit = XHCI_MTK_MAX_ESIT / sch_ep->esit;
> > + for (i = 0; i < num_esit; i++) {
> > + u32 base = offset + i * sch_ep->esit;
> > +
> > + for (j = 0; j < sch_ep->num_budget_microframes; j++) {
> > + if (sch_bw->bus_bw[base + j] > max_bw)
> > + max_bw = sch_bw->bus_bw[base + j];
> > + }
> > + }
> > + return max_bw;
> > +}
> > +
> > +static void update_bus_bw(struct mu3h_sch_bw_info *sch_bw,
> > + struct mu3h_sch_ep_info *sch_ep, int bw_cost)
> > +{
> > + u32 num_esit;
> > + u32 base;
> > + int i;
> > + int j;
> > +
> > + num_esit = XHCI_MTK_MAX_ESIT / sch_ep->esit;
> > + for (i = 0; i < num_esit; i++) {
> > + base = sch_ep->offset + i * sch_ep->esit;
> > + for (j = 0; j < sch_ep->num_budget_microframes; j++)
> > + sch_bw->bus_bw[base + j] += bw_cost;
> > + }
> > +
> > +}
> > +
> > +static void debug_sch_ep(struct mu3h_sch_ep_info *sch_ep)
> > +{
> > + pr_debug("%s:\n", __func__);
> > + pr_debug("sch_ep->ep_type = %d\n", sch_ep->ep_type);
> > + pr_debug("sch_ep->max_packet_size = %d\n", sch_ep->max_packet_size);
> > + pr_debug("sch_ep->esit = %d\n", sch_ep->esit);
> > + pr_debug("sch_ep->num_budget_microframes = %d\n",
> > + sch_ep->num_budget_microframes);
> > + pr_debug("sch_ep->bw_cost_per_microframe = %d\n",
> > + sch_ep->bw_cost_per_microframe);
> > + pr_debug("sch_ep->ep = %p\n", sch_ep->ep);
> > + pr_debug("sch_ep->offset = %d\n", sch_ep->offset);
> > + pr_debug("sch_ep->repeat = %d\n", sch_ep->repeat);
> > + pr_debug("sch_ep->pkts = %d\n", sch_ep->pkts);
> > + pr_debug("sch_ep->cs_count = %d\n", sch_ep->cs_count);
> > +}
> > +
> > +static int check_sch_bw(struct usb_device *udev,
> > + struct mu3h_sch_bw_info *sch_bw, struct mu3h_sch_ep_info *sch_ep)
> > +{
> > + u32 offset;
> > + u32 esit;
> > + u32 num_budget_microframes;
> > + u32 min_bw;
> > + u32 min_index;
> > + u32 worst_bw;
> > + u32 bw_boundary;
> > +
> > + if (sch_ep->esit > XHCI_MTK_MAX_ESIT)
> > + sch_ep->esit = XHCI_MTK_MAX_ESIT;
> > +
> > + esit = sch_ep->esit;
> > + num_budget_microframes = sch_ep->num_budget_microframes;
> > +
> > + /*
> > + * Search through all possible schedule microframes.
> > + * and find a microframe where its worst bandwidth is minimum.
> > + */
> > + min_bw = ~0;
> > + min_index = 0;
> > + for (offset = 0; offset < esit; offset++) {
> > + if ((offset + num_budget_microframes) > sch_ep->esit)
> > + break;
> > + /*
> > + * usb_20 spec section11.18:
> > + * must never schedule Start-Split in Y6
> > + */
> > + if (is_fs_or_ls(udev->speed) && (offset % 8 == 6))
> > + continue;
> > +
> > + worst_bw = get_max_bw(sch_bw, sch_ep, offset);
> > + if (min_bw > worst_bw) {
> > + min_bw = worst_bw;
> > + min_index = offset;
> > + }
> > + if (min_bw == 0)
> > + break;
> > + }
> > + sch_ep->offset = min_index;
> > +
> > + debug_sch_ep(sch_ep);
> > +
> > + bw_boundary = (udev->speed == USB_SPEED_SUPER)
> > + ? SS_BW_BOUNDARY : HS_BW_BOUNDARY;
> > +
> > + /* check bandwidth */
> > + if (min_bw + sch_ep->bw_cost_per_microframe > bw_boundary)
> > + return -1;
> > +
> > + /* update bus bandwidth info */
> > + update_bus_bw(sch_bw, sch_ep, sch_ep->bw_cost_per_microframe);
> > +
> > + return 0;
> > +}
> > +
> > +static void debug_sch_bw(struct mu3h_sch_bw_info *sch_bw)
> > +{
> > + int i;
> > +
> > + pr_debug("%s: bus_bw_info\n", __func__);
> > + for (i = 0; i < XHCI_MTK_MAX_ESIT; i++)
> > + pr_debug("%d ", sch_bw->bus_bw[i]);
> > +
> > + pr_debug("\n");
> > +}
> > +
> > +
> > +static bool need_bw_sch(struct usb_host_endpoint *ep,
> > + enum usb_device_speed speed, int has_tt)
> > +{
> > + /* only for periodic endpoints */
> > + if (usb_endpoint_xfer_control(&ep->desc)
> > + || usb_endpoint_xfer_bulk(&ep->desc))
> > + return false;
> > + /*
> > + * for LS & FS periodic endpoints which its device don't attach
> > + * to TT are also ignored, root-hub will schedule them directly
> > + */
> > + if (is_fs_or_ls(speed) && !has_tt)
> > + return false;
> > +
> > + return true;
> > +}
> > +
> > +static int xhci_mtk_sch_init(struct xhci_hcd *xhci)
> > +{
> > + struct usb_hcd *hcd = xhci_to_hcd(xhci);
> > + struct device *dev = hcd->self.controller;
> > + struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
> > + struct mu3h_sch_bw_info *sch_array;
> > + int num_usb_bus;
> > + int i;
> > +
> > + /* ss IN and OUT are separated */
> > + num_usb_bus = xhci->num_usb3_ports * 2 + xhci->num_usb2_ports;
> > +
> > + sch_array = kcalloc(num_usb_bus, sizeof(*sch_array), GFP_KERNEL);
> > + if (sch_array == NULL)
> > + return -ENOMEM;
> > +
> > + for (i = 0; i < num_usb_bus; i++)
> > + INIT_LIST_HEAD(&sch_array[i].bw_ep_list);
> > +
> > + mtk->sch_array = sch_array;
> > +
> > + return 0;
> > +}
> > +
> > +
> > +static void xhci_mtk_sch_exit(struct xhci_hcd *xhci)
> > +{
> > + struct usb_hcd *hcd = xhci_to_hcd(xhci);
> > + struct device *dev = hcd->self.controller;
> > + struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
> > +
> > + kfree(mtk->sch_array);
> > +}
> > +
> > +
> > +int xhci_mtk_add_ep_quirk(struct usb_hcd *hcd, struct usb_device *udev,
> > + struct usb_host_endpoint *ep)
> > +{
> > + struct device *dev = hcd->self.controller;
> > + struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
> > +
> > + int ret = 0;
> > + int port_id;
> > + int bw_index;
> > + struct xhci_hcd *xhci;
> > + unsigned int ep_index;
> > + struct xhci_ep_ctx *ep_ctx;
> > + struct xhci_slot_ctx *slot_ctx;
> > + struct xhci_virt_device *virt_dev;
> > + struct mu3h_sch_bw_info *sch_bw;
> > + struct mu3h_sch_ep_info *sch_ep;
> > + struct mu3h_sch_bw_info *sch_array;
> > +
> > + xhci = hcd_to_xhci(hcd);
> > + virt_dev = xhci->devs[udev->slot_id];
> > + ep_index = xhci_get_endpoint_index(&ep->desc);
> > + slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
> > + ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
> > + sch_array = mtk->sch_array;
> > +
> > + port_id = virt_dev->real_port;
> > + xhci_dbg(xhci, "%s() xfer_type: %d, speed:%d, ep:%p\n", __func__,
> > + usb_endpoint_type(&ep->desc), udev->speed, ep);
> > +
> > + if (!need_bw_sch(ep, udev->speed, slot_ctx->tt_info & TT_SLOT))
> > + return 0;
> > +
> > + bw_index = get_bw_index(xhci, udev, ep);
> > + sch_bw = &sch_array[bw_index];
> > +
> > + sch_ep = kzalloc(sizeof(struct mu3h_sch_ep_info), GFP_NOIO);
> > + if (!sch_ep)
> > + return -ENOMEM;
> > +
> > + setup_sch_info(udev, ep_ctx, sch_ep);
> > +
> > + ret = check_sch_bw(udev, sch_bw, sch_ep);
> > + if (ret) {
> > + xhci_err(xhci, "Not enough bandwidth!\n");
> > + kfree(sch_ep);
> > + return -ENOSPC;
> > + }
> > +
> > + list_add_tail(&sch_ep->endpoint, &sch_bw->bw_ep_list);
> > + sch_ep->ep = ep;
> > +
> > + ep_ctx->reserved[0] |= cpu_to_le32(EP_BPKTS(sch_ep->pkts)
> > + | EP_BCSCOUNT(sch_ep->cs_count) | EP_BBM(sch_ep->burst_mode));
> > + ep_ctx->reserved[1] |= cpu_to_le32(EP_BOFFSET(sch_ep->offset)
> > + | EP_BREPEAT(sch_ep->repeat));
> > +
> > + debug_sch_bw(sch_bw);
> > + return 0;
> > +}
> > +EXPORT_SYMBOL_GPL(xhci_mtk_add_ep_quirk);
> > +
> > +
> > +void xhci_mtk_drop_ep_quirk(struct usb_hcd *hcd, struct usb_device *udev,
> > + struct usb_host_endpoint *ep)
> > +{
> > + struct device *dev = hcd->self.controller;
> > + struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
> > +
> > + int bw_index;
> > + struct xhci_hcd *xhci;
> > + struct xhci_slot_ctx *slot_ctx;
> > + struct xhci_virt_device *virt_dev;
> > + struct mu3h_sch_bw_info *sch_array;
> > + struct mu3h_sch_bw_info *sch_bw;
> > + struct mu3h_sch_ep_info *sch_ep;
> > +
> > + xhci = hcd_to_xhci(hcd);
> > + virt_dev = xhci->devs[udev->slot_id];
> > + slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
> > + sch_array = mtk->sch_array;
> > +
> > + xhci_dbg(xhci, "%s() xfer_type: %d, speed:%d, ep:%p\n", __func__,
> > + usb_endpoint_type(&ep->desc), udev->speed, ep);
> > +
> > + if (!need_bw_sch(ep, udev->speed, slot_ctx->tt_info & TT_SLOT))
> > + return;
> > +
> > + bw_index = get_bw_index(xhci, udev, ep);
> > + sch_bw = &sch_array[bw_index];
> > +
> > + list_for_each_entry(sch_ep, &sch_bw->bw_ep_list, endpoint) {
> > + if (sch_ep->ep == ep) {
> > + update_bus_bw(sch_bw, sch_ep,
> > + -sch_ep->bw_cost_per_microframe);
> > + list_del(&sch_ep->endpoint);
> > + kfree(sch_ep);
> > + break;
> > + }
> > + }
> > + debug_sch_bw(sch_bw);
> > +}
> > +EXPORT_SYMBOL_GPL(xhci_mtk_drop_ep_quirk);
> > +
> > +
> > +/*
> > + * The TD size is the number of max packet sized packets remaining in the TD
> > + * (including this TRB), right shifted by 10.
> > + * It must fit in bits 21:17, so it can't be bigger than 31.
> > + */
> > +u32 xhci_mtk_td_remainder_quirk(unsigned int td_running_total,
> > + unsigned trb_buffer_length, struct urb *urb)
> > +{
> > + u32 max = 31;
> > + int remainder, td_packet_count, packet_transferred;
> > + unsigned int td_transfer_size = urb->transfer_buffer_length;
> > + unsigned int maxp;
> > +
> > + maxp = GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc));
> > +
> > + /* 0 for the last TRB */
> > + if (td_running_total + trb_buffer_length == td_transfer_size)
> > + return 0;
> > +
> > + packet_transferred = td_running_total / maxp;
> > + td_packet_count = DIV_ROUND_UP(td_transfer_size, maxp);
> > + remainder = td_packet_count - packet_transferred;
> > +
> > + if (remainder > max)
> > + return max << 17;
> > + else
> > + return remainder << 17;
> > +}
> > +EXPORT_SYMBOL_GPL(xhci_mtk_td_remainder_quirk);
> > +
> > +
> > +static int xhci_mtk_setup(struct usb_hcd *hcd);
> > +static const struct xhci_driver_overrides xhci_mtk_overrides __initconst = {
> > + .extra_priv_size = sizeof(struct xhci_hcd),
> > + .reset = xhci_mtk_setup,
> > +};
> > +
> > +static struct hc_driver __read_mostly xhci_mtk_hc_driver;
> > +
> > +
> > +static int xhci_mtk_ldos_enable(struct xhci_hcd_mtk *mtk)
> > +{
> > + int ret;
> > +
> > + ret = regulator_enable(mtk->vbus);
> > + if (ret) {
> > + dev_err(mtk->dev, "failed to enable vbus\n");
> > + return ret;
> > + }
> > +
> > + ret = regulator_enable(mtk->vusb33);
> > + if (ret) {
> > + dev_err(mtk->dev, "failed to enable vusb33\n");
> > + regulator_disable(mtk->vbus);
> > + return ret;
> > + }
> > + return 0;
> > +}
> > +
> > +static void xhci_mtk_ldos_disable(struct xhci_hcd_mtk *mtk)
> > +{
> > + regulator_disable(mtk->vbus);
> > + regulator_disable(mtk->vusb33);
> > +}
> > +
> > +static void xhci_mtk_quirks(struct device *dev, struct xhci_hcd *xhci)
> > +{
> > + /*
> > + * As of now platform drivers don't provide MSI support so we ensure
> > + * here that the generic code does not try to make a pci_dev from our
> > + * dev struct in order to setup MSI
> > + */
> > + xhci->quirks |= XHCI_PLAT;
> > + xhci->quirks |= XHCI_MTK_HOST;
> > + /*
> > + * MTK host controller gives a spurious successful event after a
> > + * short transfer. Ignore it.
> > + */
> > + xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
> > +}
> > +
> > +/* called during probe() after chip reset completes */
> > +static int xhci_mtk_setup(struct usb_hcd *hcd)
> > +{
> > + struct xhci_hcd *xhci;
> > + int ret;
> > +
> > + ret = xhci_gen_setup(hcd, xhci_mtk_quirks);
> > + if (ret)
> > + return ret;
> > +
> > + if (!usb_hcd_is_primary_hcd(hcd))
> > + return 0;
> > +
> > + xhci = hcd_to_xhci(hcd);
> > + ret = xhci_mtk_sch_init(xhci);
> > + if (ret) {
> > + kfree(xhci);
> > + return ret;
> > + }
> > +
> > + return ret;
> > +}
> > +
> > +
> > +static int xhci_mtk_probe(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct device_node *node = pdev->dev.of_node;
> > + struct usb_xhci_pdata *pdata = dev_get_platdata(dev);
> > + struct xhci_hcd_mtk *mtk;
> > + const struct hc_driver *driver;
> > + struct xhci_hcd *xhci;
> > + struct resource *res;
> > + struct usb_hcd *hcd;
> > + int ret = -ENODEV;
> > + int irq;
> > +
> > + if (usb_disabled())
> > + return -ENODEV;
> > +
> > + driver = &xhci_mtk_hc_driver;
> > + mtk = devm_kzalloc(dev, sizeof(*mtk), GFP_KERNEL);
> > + if (!mtk)
> > + return -ENOMEM;
> > + mtk->dev = dev;
> > +
> > + mtk->sys_mac = devm_clk_get(dev, "sys_mac");
> > + if (IS_ERR(mtk->sys_mac)) {
> > + dev_err(dev, "error to get sys_mac\n");
> > + ret = PTR_ERR(mtk->sys_mac);
> > + goto err;
> > + }
> > +
> > + mtk->vbus = devm_regulator_get(dev, "reg-vbus");
> > + if (IS_ERR(mtk->vbus)) {
> > + dev_err(dev, "fail to get vbus\n");
> > + ret = PTR_ERR(mtk->vbus);
> > + goto err;
> > + }
> > +
> > + mtk->vusb33 = devm_regulator_get(dev, "reg-vusb33");
> > + if (IS_ERR(mtk->vusb33)) {
> > + dev_err(dev, "fail to get vusb33\n");
> > + ret = PTR_ERR(mtk->vusb33);
> > + goto err;
> > + }
> > + pm_runtime_enable(dev);
> > + pm_runtime_get_sync(dev);
> > +
> > + ret = xhci_mtk_ldos_enable(mtk);
> > + if (ret)
> > + goto disable_pm;
> > +
> > + ret = clk_prepare_enable(mtk->sys_mac);
> > + if (ret)
> > + goto disable_ldos;
> > +
> > + irq = platform_get_irq(pdev, 0);
> > + if (irq < 0)
> > + goto disable_clk;
> > +
> > + /* Initialize dma_mask and coherent_dma_mask to 32-bits */
> > + ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
> > + if (ret)
> > + goto disable_clk;
> > +
> > + if (!dev->dma_mask)
> > + dev->dma_mask = &dev->coherent_dma_mask;
> > + else
> > + dma_set_mask(dev, DMA_BIT_MASK(32));
> > +
> > + hcd = usb_create_hcd(driver, dev, dev_name(dev));
> > + if (!hcd) {
> > + ret = -ENOMEM;
> > + goto disable_clk;
> > + }
> > +
> > + /*
> > + * USB 2.0 roothub is stored in the platform_device.
> > + * Swap it with mtk HCD.
> > + */
> > + mtk->hcd = platform_get_drvdata(pdev);
> > + platform_set_drvdata(pdev, mtk);
> > +
> > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > + hcd->regs = devm_ioremap_resource(dev, res);
> > + if (IS_ERR(hcd->regs)) {
> > + ret = PTR_ERR(hcd->regs);
> > + goto put_usb2_hcd;
> > + }
> > + hcd->rsrc_start = res->start;
> > + hcd->rsrc_len = resource_size(res);
> > +
> > + hcd->usb_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
> > + if (IS_ERR(hcd->usb_phy)) {
> > + ret = PTR_ERR(hcd->usb_phy);
> > + if (ret == -EPROBE_DEFER)
> > + goto put_usb2_hcd;
> > + hcd->usb_phy = NULL;
> > + } else {
> > + ret = usb_phy_init(hcd->usb_phy);
> > + if (ret)
> > + goto put_usb2_hcd;
> > + }
> > +
> > + device_wakeup_enable(hcd->self.controller);
> > +
> > + xhci = hcd_to_xhci(hcd);
> > + xhci->main_hcd = hcd;
> > + xhci->shared_hcd = usb_create_shared_hcd(driver, dev,
> > + dev_name(dev), hcd);
> > + if (!xhci->shared_hcd) {
> > + ret = -ENOMEM;
> > + goto disable_usb_phy;
> > + }
> > +
> > + if ((node && of_property_read_bool(node, "usb3-lpm-capable")) ||
> > + (pdata && pdata->usb3_lpm_capable))
> > + xhci->quirks |= XHCI_LPM_SUPPORT;
> > +
> > + if (HCC_MAX_PSA(xhci->hcc_params) >= 4)
> > + xhci->shared_hcd->can_do_streams = 1;
> > +
> > + ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
> > + if (ret)
> > + goto put_usb3_hcd;
> > +
> > + ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED);
> > + if (ret)
> > + goto dealloc_usb2_hcd;
> > +
> > + return 0;
> > +
> > +
> > +dealloc_usb2_hcd:
> > + usb_remove_hcd(hcd);
> > +
> > +put_usb3_hcd:
> > + usb_put_hcd(xhci->shared_hcd);
> > +
> > +disable_usb_phy:
> > + usb_phy_shutdown(hcd->usb_phy);
> > +
> > +put_usb2_hcd:
> > + usb_put_hcd(hcd);
> > +
> > +disable_clk:
> > + clk_disable_unprepare(mtk->sys_mac);
> > +
> > +disable_ldos:
> > + xhci_mtk_ldos_disable(mtk);
> > +
> > +disable_pm:
> > + pm_runtime_put_sync(dev);
> > + pm_runtime_disable(dev);
> > +
> > +err:
> > + return ret;
> > +}
> > +
> > +static int xhci_mtk_remove(struct platform_device *dev)
> > +{
> > + struct xhci_hcd_mtk *mtk = platform_get_drvdata(dev);
> > + struct usb_hcd *hcd = mtk->hcd;
> > + struct xhci_hcd *xhci = hcd_to_xhci(hcd);
> > +
> > + usb_remove_hcd(xhci->shared_hcd);
> > + usb_phy_shutdown(hcd->usb_phy);
> > +
> > + usb_remove_hcd(hcd);
> > + usb_put_hcd(xhci->shared_hcd);
> > + usb_put_hcd(hcd);
> > + xhci_mtk_sch_exit(xhci);
> > + clk_disable_unprepare(mtk->sys_mac);
> > + xhci_mtk_ldos_disable(mtk);
> > + pm_runtime_put_sync(&dev->dev);
> > + pm_runtime_disable(&dev->dev);
> > +
> > + return 0;
> > +}
> > +
> > +#ifdef CONFIG_PM_SLEEP
> > +static int xhci_mtk_suspend(struct device *dev)
> > +{
> > + struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
> > + struct usb_hcd *hcd = mtk->hcd;
> > + int ret;
> > +
> > + ret = usb_phy_set_suspend(hcd->usb_phy, 1);
> > + /* keep on power of mac to maintain register, and only close clock */
> > + clk_disable_unprepare(mtk->sys_mac);
> > + return ret;
> > +}
> > +
> > +static int xhci_mtk_resume(struct device *dev)
> > +{
> > + struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
> > + struct usb_hcd *hcd = mtk->hcd;
> > + int ret;
> > +
> > + clk_prepare_enable(mtk->sys_mac);
> > + ret = usb_phy_set_suspend(hcd->usb_phy, 0);
> > +
> > + return ret;
> > +}
> > +
> > +static const struct dev_pm_ops xhci_mtk_pm_ops = {
> > + SET_SYSTEM_SLEEP_PM_OPS(xhci_mtk_suspend, xhci_mtk_resume)
> > +};
> > +#define DEV_PM_OPS (&xhci_mtk_pm_ops)
> > +#else
> > +#define DEV_PM_OPS NULL
> > +#endif /* CONFIG_PM */
> > +
> > +#ifdef CONFIG_OF
> > +static const struct of_device_id mtk_xhci_of_match[] = {
> > + { .compatible = "mediatek,mt8173-xhci"},
> > + { },
> > +};
> > +MODULE_DEVICE_TABLE(of, mtk_xhci_of_match);
> > +#endif
> > +
> > +static struct platform_driver mtk_xhci_driver = {
> > + .probe = xhci_mtk_probe,
> > + .remove = xhci_mtk_remove,
> > + .driver = {
> > + .name = "xhci-mtk",
> > + .pm = DEV_PM_OPS,
> > + .of_match_table = of_match_ptr(mtk_xhci_of_match),
> > + },
> > +};
> > +
> > +static int __init xhci_mtk_init(void)
> > +{
> > + xhci_init_driver(&xhci_mtk_hc_driver, &xhci_mtk_overrides);
> > + return platform_driver_register(&mtk_xhci_driver);
> > +}
> > +module_init(xhci_mtk_init);
> > +
> > +static void __exit xhci_mtk_exit(void)
> > +{
> > + platform_driver_unregister(&mtk_xhci_driver);
> > +}
> > +module_exit(xhci_mtk_exit);
> > +
> > +MODULE_DESCRIPTION("MediaTek xHCI Host Controller Driver");
> > +MODULE_LICENSE("GPL v2");
> > +
> > diff --git a/drivers/usb/host/xhci-mtk.h b/drivers/usb/host/xhci-mtk.h
> > new file mode 100644
> > index 0000000..e0fdd19
> > --- /dev/null
> > +++ b/drivers/usb/host/xhci-mtk.h
> > @@ -0,0 +1,108 @@
> > +/*
> > + * Copyright (c) 2015 MediaTek Inc.
> > + * Author:
> > + * Zhigang.Wei <zhigang.wei@mediatek.com>
> > + * Chunfeng.Yun <chunfeng.yun@mediatek.com>
> > + *
> > + * This software is licensed under the terms of the GNU General Public
> > + * License version 2, as published by the Free Software Foundation, and
> > + * may be copied, distributed, and modified under those terms.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + *
> > + */
> > +
> > +#ifndef _XHCI_MTK_H_
> > +#define _XHCI_MTK_H_
> > +
> > +#include "xhci.h"
> > +
> > +/**
> > + * To simplify scheduler algorithm, set a upper limit for ESIT,
> > + * if a synchromous ep's ESIT is larger than @XHCI_MTK_MAX_ESIT,
> > + * round down to the limit value, that means allocating more
> > + * bandwidth to it.
> > + */
> > +#define XHCI_MTK_MAX_ESIT 64
> > +
> > +/**
> > + * struct mu3h_sch_bw_info
> > + * @bus_bw: array to keep track of bandwidth already used at each uframes
> > + * @bw_ep_list: eps in the bandwidth domain
> > + *
> > + * treat a HS root port as a bandwidth domain, but treat a SS root port as
> > + * two bandwidth domains, one for IN eps and another for OUT eps.
> > + */
> > +struct mu3h_sch_bw_info {
> > + u32 bus_bw[XHCI_MTK_MAX_ESIT];
> > + struct list_head bw_ep_list;
> > +};
> > +
> > +/**
> > + * struct mu3h_sch_ep_info
> > + * @esit: unit is 125us, equal to 2 << Interval field in ep-context
> > + * @num_budget_microframes: number of continuous uframes
> > + * (@repeat==1) scheduled within the interval
> > + * @ep: address of usb_host_endpoint
> > + * @offset: which uframe of the interval that transfer should be
> > + * scheduled first time within the interval
> > + * @repeat: the time gap between two uframes that transfers are
> > + * scheduled within a interval. in the simple algorithm, only
> > + * assign 0 or 1 to it; 0 means using only one uframe in a
> > + * interval, and1 means using @num_budget_microframes
> > + * continuous uframes
> > + * @pkts: number of packets to be transferred in the scheduled uframes
> > + * @cs_count: number of CS that host will trigger
> > + */
> > +struct mu3h_sch_ep_info {
> > + u32 ep_type;
> > + u32 max_packet_size;
> > + u32 esit;
> > + u32 num_budget_microframes;
> > + u32 bw_cost_per_microframe;
> > + void *ep;
> > + struct list_head endpoint;
> > +
> > + /* mtk xhci scheduling info */
> > + u32 offset;
> > + u32 repeat;
> > + u32 pkts;
> > + u32 cs_count;
> > + u32 burst_mode;
> > +};
> > +
> > +
> > +#if IS_ENABLED(CONFIG_USB_XHCI_MTK)
> > +
> > +int xhci_mtk_add_ep_quirk(struct usb_hcd *hcd, struct usb_device *udev,
> > + struct usb_host_endpoint *ep);
> > +void xhci_mtk_drop_ep_quirk(struct usb_hcd *hcd, struct usb_device *udev,
> > + struct usb_host_endpoint *ep);
> > +u32 xhci_mtk_td_remainder_quirk(unsigned int td_running_total,
> > + unsigned trb_buffer_length, struct urb *urb);
> > +
> > +#else
> > +static inline int xhci_mtk_add_ep_quirk(struct usb_hcd *hcd,
> > + struct usb_device *udev, struct usb_host_endpoint *ep)
> > +{
> > + return 0;
> > +}
> > +
> > +static inline void xhci_mtk_drop_ep_quirk(struct usb_hcd *hcd,
> > + struct usb_device *udev, struct usb_host_endpoint *ep)
> > +{
> > + return 0;
> > +}
> > +
> > +static inline u32 xhci_mtk_td_remainder_quirk(unsigned int td_running_total,
> > + unsigned trb_buffer_length, struct urb *urb)
> > +{
> > + return 0;
> > +}
> > +
> > +#endif
> > +
> > +#endif /* _XHCI_MTK_H_ */
> > diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
> > index 94416ff..73997a0 100644
> > --- a/drivers/usb/host/xhci-ring.c
> > +++ b/drivers/usb/host/xhci-ring.c
> > @@ -68,6 +68,7 @@
> > #include <linux/slab.h>
> > #include "xhci.h"
> > #include "xhci-trace.h"
> > +#include "xhci-mtk.h"
> >
> > /*
> > * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
> > @@ -3131,9 +3132,14 @@ static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
> >
> > /* Set the TRB length, TD size, and interrupter fields. */
> > if (xhci->hci_version < 0x100) {
> > - remainder = xhci_td_remainder(
> > + if (xhci->quirks & XHCI_MTK_HOST) {
> > + remainder = xhci_mtk_td_remainder_quirk(
> > + running_total, trb_buff_len, urb);
> > + } else {
> > + remainder = xhci_td_remainder(
> > urb->transfer_buffer_length -
> > running_total);
> > + }
> > } else {
> > remainder = xhci_v1_0_td_remainder(running_total,
> > trb_buff_len, total_packet_count, urb,
> > @@ -3286,9 +3292,14 @@ int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
> >
> > /* Set the TRB length, TD size, and interrupter fields. */
> > if (xhci->hci_version < 0x100) {
> > - remainder = xhci_td_remainder(
> > + if (xhci->quirks & XHCI_MTK_HOST) {
> > + remainder = xhci_mtk_td_remainder_quirk(
> > + running_total, trb_buff_len, urb);
> > + } else {
> > + remainder = xhci_td_remainder(
> > urb->transfer_buffer_length -
> > running_total);
> > + }
> > } else {
> > remainder = xhci_v1_0_td_remainder(running_total,
> > trb_buff_len, total_packet_count, urb,
> > @@ -3383,7 +3394,7 @@ int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
> > field |= 0x1;
> >
> > /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
> > - if (xhci->hci_version == 0x100) {
> > + if ((xhci->hci_version == 0x100) || (xhci->quirks & XHCI_MTK_HOST)) {
> > if (urb->transfer_buffer_length > 0) {
> > if (setup->bRequestType & USB_DIR_IN)
> > field |= TRB_TX_TYPE(TRB_DATA_IN);
> > @@ -3407,8 +3418,14 @@ int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
> > field = TRB_TYPE(TRB_DATA);
> >
> > length_field = TRB_LEN(urb->transfer_buffer_length) |
> > - xhci_td_remainder(urb->transfer_buffer_length) |
> > TRB_INTR_TARGET(0);
> > +
> > + if (xhci->quirks & XHCI_MTK_HOST)
> > + length_field |= xhci_mtk_td_remainder_quirk(0,
> > + urb->transfer_buffer_length, urb);
> > + else
> > + length_field |= xhci_td_remainder(urb->transfer_buffer_length);
> > +
> > if (urb->transfer_buffer_length > 0) {
> > if (setup->bRequestType & USB_DIR_IN)
> > field |= TRB_DIR_IN;
> > @@ -3632,8 +3649,14 @@ static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
> >
> > /* Set the TRB length, TD size, & interrupter fields. */
> > if (xhci->hci_version < 0x100) {
> > - remainder = xhci_td_remainder(
> > - td_len - running_total);
> > + if (xhci->quirks & XHCI_MTK_HOST) {
> > + remainder = xhci_mtk_td_remainder_quirk(
> > + running_total, trb_buff_len,
> > + urb);
> > + } else {
> > + remainder = xhci_td_remainder(
> > + td_len - running_total);
> > + }
> > } else {
> > remainder = xhci_v1_0_td_remainder(
> > running_total, trb_buff_len,
> > diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
> > index 7da0d60..209fc8a 100644
> > --- a/drivers/usb/host/xhci.c
> > +++ b/drivers/usb/host/xhci.c
> > @@ -31,6 +31,7 @@
> >
> > #include "xhci.h"
> > #include "xhci-trace.h"
> > +#include "xhci-mtk.h"
> >
> > #define DRIVER_AUTHOR "Sarah Sharp"
> > #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
> > @@ -623,7 +624,11 @@ int xhci_run(struct usb_hcd *hcd)
> > "// Set the interrupt modulation register");
> > temp = readl(&xhci->ir_set->irq_control);
> > temp &= ~ER_IRQ_INTERVAL_MASK;
> > - temp |= (u32) 160;
> > + /*
> > + * the increment interval is 8 times as much as that defined
> > + * in xHCI spec on MTK's controller
> > + */
> > + temp |= (u32) ((xhci->quirks & XHCI_MTK_HOST) ? 20 : 160);
> > writel(temp, &xhci->ir_set->irq_control);
> >
> > /* Set the HCD state before we enable the irqs */
> > @@ -1688,6 +1693,9 @@ int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
> >
> > xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
> >
> > + if (xhci->quirks & XHCI_MTK_HOST)
> > + xhci_mtk_drop_ep_quirk(hcd, udev, ep);
> > +
> > xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
> > (unsigned int) ep->desc.bEndpointAddress,
> > udev->slot_id,
> > @@ -1783,6 +1791,15 @@ int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
> > return -ENOMEM;
> > }
> >
> > + if (xhci->quirks & XHCI_MTK_HOST) {
> > + ret = xhci_mtk_add_ep_quirk(hcd, udev, ep);
> > + if (ret < 0) {
> > + xhci_free_or_cache_endpoint_ring(xhci,
> > + virt_dev, ep_index);
> > + return ret;
> > + }
> > + }
> > +
> > ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
> > new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
> >
> > diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
> > index 31e46cc..d257ce3 100644
> > --- a/drivers/usb/host/xhci.h
> > +++ b/drivers/usb/host/xhci.h
> > @@ -1567,6 +1567,7 @@ struct xhci_hcd {
> > /* For controllers with a broken beyond repair streams implementation */
> > #define XHCI_BROKEN_STREAMS (1 << 19)
> > #define XHCI_PME_STUCK_QUIRK (1 << 20)
> > +#define XHCI_MTK_HOST (1 << 21)
> > unsigned int num_active_eps;
> > unsigned int limit_active_eps;
> > /* There are two roothubs to keep track of bus suspend info for */
> >
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v2 5/5] arm64: dts: mediatek: add xHCI & usb phy for mt8173
2015-07-20 14:51 ` Yingjoe Chen
@ 2015-07-20 14:59 ` Daniel Kurtz
0 siblings, 0 replies; 22+ messages in thread
From: Daniel Kurtz @ 2015-07-20 14:59 UTC (permalink / raw)
To: Yingjoe Chen
Cc: chunfeng yun, Mark Rutland, open list:OPEN FIRMWARE AND...,
Mathias Nyman, Sascha Hauer, linux-usb, linux-kernel,
Felipe Balbi, Rob Herring, linux-mediatek, Matthias Brugger,
linux-arm-kernel, Roger Quadros
On Mon, Jul 20, 2015 at 10:51 PM, Yingjoe Chen
<yingjoe.chen@mediatek.com> wrote:
>
> Hi Daniel, Chunfeng,
>
>
> On Mon, 2015-07-20 at 22:39 +0800, chunfeng yun wrote:
>> Hi,
>>
>> On Tue, 2015-07-14 at 18:12 +0800, Daniel Kurtz wrote:
> <...>
>> > > +
>> > > + usb_p1_vbus: fixedregulator@0 {
>> >
>> > Why @0 ?
>> It is the first fixed regulator, so set it to 0 as a index.
>> I will remove it later
>
> Since this name should be unique, I think we should use gpio number as
> address for fixedregulator in case we need other fixedregulators. So
> this could be:
>
> usb_p1_vbus: fixedregulator@130 {
>
> Also, we should sort according to the address(gpio number) for these
> nodes. Does this make sense?
Yes - that makes some sense.
But, a quick check of other "fixedregulator@" nodes in
arch/arm/boot/dts/ shows that mostly they use @0 , @1.
So, I think the original patch is probably fine.
Sorry for the noise,
-Dan
>
> Joe.C
>
>> >
>> > > + compatible = "regulator-fixed";
>> > > + regulator-name = "usb_vbus";
>> > > + regulator-min-microvolt = <5000000>;
>> > > + regulator-max-microvolt = <5000000>;
>> > > + gpio = <&pio 130 GPIO_ACTIVE_HIGH>;
>> > > + enable-active-high;
>> > > + };
>
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v2 3/5] usb: phy: add usb3.0 phy driver for mt65xx SoCs
2015-07-10 6:42 ` Sascha Hauer
@ 2015-07-20 15:41 ` chunfeng yun
0 siblings, 0 replies; 22+ messages in thread
From: chunfeng yun @ 2015-07-20 15:41 UTC (permalink / raw)
To: Sascha Hauer
Cc: Mathias Nyman, Rob Herring, Mark Rutland, Matthias Brugger,
Felipe Balbi, devicetree, linux-kernel, linux-arm-kernel,
Roger Quadros, linux-usb, linux-mediatek
On Fri, 2015-07-10 at 08:42 +0200, Sascha Hauer wrote:
> On Wed, Jul 08, 2015 at 05:41:05PM +0800, Chunfeng Yun wrote:
> > Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> > ---
> > drivers/usb/phy/Kconfig | 10 +
> > drivers/usb/phy/Makefile | 1 +
> > drivers/usb/phy/phy-mt65xx-usb3.c | 856 ++++++++++++++++++++++++++++++++++++++
> > 3 files changed, 867 insertions(+)
> > create mode 100644 drivers/usb/phy/phy-mt65xx-usb3.c
> >
> > diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
> > index 869c0cfcad..66ded00 100644
> > --- a/drivers/usb/phy/Kconfig
> > +++ b/drivers/usb/phy/Kconfig
> > @@ -152,6 +152,16 @@ config USB_MSM_OTG
> > This driver is not supported on boards like trout which
> > has an external PHY.
> >
> > +config USB_MT65XX_USB3_PHY
> > + tristate "Mediatek USB3.0 PHY controller Driver"
> > + depends on ARCH_MEDIATEK || COMPILE_TEST
> > + select USB_PHY
> > + help
> > + Say 'Y' here to add support for Mediatek USB3.0 PHY driver
> > + for mt65xx SoCs. it supports two usb2.0 ports and
> > + one usb3.0 port.
> > + To compile this driver as a module, choose M here
> > +
> > config USB_MV_OTG
> > tristate "Marvell USB OTG support"
> > depends on USB_EHCI_MV && USB_MV_UDC && PM
> > diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
> > index e36ab1d..414ef57 100644
> > --- a/drivers/usb/phy/Makefile
> > +++ b/drivers/usb/phy/Makefile
> > @@ -20,6 +20,7 @@ obj-$(CONFIG_USB_EHCI_TEGRA) += phy-tegra-usb.o
> > obj-$(CONFIG_USB_GPIO_VBUS) += phy-gpio-vbus-usb.o
> > obj-$(CONFIG_USB_ISP1301) += phy-isp1301.o
> > obj-$(CONFIG_USB_MSM_OTG) += phy-msm-usb.o
> > +obj-$(CONFIG_USB_MT65XX_USB3_PHY) += phy-mt65xx-usb3.o
> > obj-$(CONFIG_USB_MV_OTG) += phy-mv-usb.o
> > obj-$(CONFIG_USB_MXS_PHY) += phy-mxs-usb.o
> > obj-$(CONFIG_USB_RCAR_PHY) += phy-rcar-usb.o
> > diff --git a/drivers/usb/phy/phy-mt65xx-usb3.c b/drivers/usb/phy/phy-mt65xx-usb3.c
> > new file mode 100644
> > index 0000000..38ee6f3
> > --- /dev/null
> > +++ b/drivers/usb/phy/phy-mt65xx-usb3.c
> > @@ -0,0 +1,856 @@
> > +/*
> > + * Copyright (c) 2015 MediaTek Inc.
> > + * Author: Chunfeng.Yun <chunfeng.yun@mediatek.com>
> > + *
> > + * This software is licensed under the terms of the GNU General Public
> > + * License version 2, as published by the Free Software Foundation, and
> > + * may be copied, distributed, and modified under those terms.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + *
> > + */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/delay.h>
> > +#include <linux/err.h>
> > +#include <linux/export.h>
> > +#include <linux/gpio.h>
> > +#include <linux/io.h>
> > +#include <linux/iopoll.h>
> > +#include <linux/mfd/syscon.h>
> > +#include <linux/module.h>
> > +#include <linux/of_address.h>
> > +#include <linux/of_device.h>
> > +#include <linux/of_gpio.h>
> > +#include <linux/of.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/pm_runtime.h>
> > +#include <linux/regmap.h>
> > +#include <linux/regulator/consumer.h>
> > +#include <linux/resource.h>
> > +#include <linux/slab.h>
> > +#include <linux/usb/of.h>
> > +#include <linux/usb/otg.h>
> > +#include <linux/usb/phy.h>
> > +
> > +/*
> > + * relative to MAC base address
> > + */
> > +#define SSUSB_USB3_MAC_CSR_BASE (0x1400)
> > +#define SSUSB_USB3_SYS_CSR_BASE (0x1400)
> > +#define SSUSB_USB2_CSR_BASE (0x2400)
>
> Please drop the unnecessary braces.
>
ok
> > +
> > +/*
> > + * for sifslv1 register
> > + * relative to USB3_SIF_BASE base address
> > + */
> > +#define SSUSB_SIFSLV_IPPC_BASE (0x700)
> > +
> > +/*
> > + * for sifslv2 register
> > + * relative to USB3_SIF_BASE base address
> > + */
> > +#define SSUSB_SIFSLV_U2PHY_COM_BASE (0x10800)
> > +#define SSUSB_SIFSLV_U3PHYD_BASE (0x10900)
> > +#define SSUSB_SIFSLV_U2FREQ_BASE (0x10f00)
> > +#define SSUSB_USB30_PHYA_SIV_B_BASE (0x10b00)
> > +#define SSUSB_SIFSLV_U3PHYA_DA_BASE (0x10c00)
> > +#define SSUSB_SIFSLV_SPLLC (0x10000)
> > +
> > +/*port1 refs. +0x800(refer to port0)*/
> > +#define U3P_PORT_OFFSET (0x800) /*based on port0 */
> > +#define U3P_PHY_BASE(index) ((U3P_PORT_OFFSET) * (index))
>
> According to my datasheet port(idx) base is at:
>
> sif_base + 0x800 + 0x100 * idx
>
> Am I missing something here?
Maybe, ssusb_sifslv_u2_phy_com_T28_Xp etc(X = 1,2,3,4)
and their interval is 0x800
> > +
> > +#define U3P_IP_PW_CTRL0 (SSUSB_SIFSLV_IPPC_BASE + 0x0000)
> > +#define CTRL0_IP_SW_RST (0x1 << 0)
> > +
> > +#define U3P_IP_PW_CTRL1 (SSUSB_SIFSLV_IPPC_BASE + 0x0004)
> > +#define CTRL1_IP_HOST_PDN (0x1 << 0)
> > +
> > +#define U3P_IP_PW_CTRL2 (SSUSB_SIFSLV_IPPC_BASE + 0x0008)
> > +#define CTRL2_IP_DEV_PDN (0x1 << 0)
> > +
> > +#define U3P_IP_PW_STS1 (SSUSB_SIFSLV_IPPC_BASE + 0x0010)
> > +#define STS1_IP_SLEEP_STS (0x1 << 30)
> > +#define STS1_U3_MAC_RST (0x1 << 16)
> > +#define STS1_SYS125_RST (0x1 << 10)
> > +#define STS1_REF_RST (0x1 << 8)
> > +#define STS1_SYSPLL_STABLE (0x1 << 0)
> > +
> > +#define U3P_IP_PW_STS2 (SSUSB_SIFSLV_IPPC_BASE + 0x0014)
> > +#define STS2_U2_MAC_RST (0x1 << 0)
> > +
> > +#define U3P_IP_XHCI_CAP (SSUSB_SIFSLV_IPPC_BASE + 0x0024)
> > +#define CAP_U3_PORT_NUM(p) ((p) & 0xff)
> > +#define CAP_U2_PORT_NUM(p) (((p) >> 8) & 0xff)
> > +
> > +#define U3P_U3_CTRL_0P (SSUSB_SIFSLV_IPPC_BASE + 0x0030)
> > +#define CTRL_U3_PORT_HOST_SEL (0x1 << 2)
> > +#define CTRL_U3_PORT_PDN (0x1 << 1)
> > +#define CTRL_U3_PORT_DIS (0x1 << 0)
> > +
> > +#define U3P_U2_CTRL_0P (SSUSB_SIFSLV_IPPC_BASE + 0x0050)
> > +#define CTRL_U2_PORT_HOST_SEL (0x1 << 2)
> > +#define CTRL_U2_PORT_PDN (0x1 << 1)
> > +#define CTRL_U2_PORT_DIS (0x1 << 0)
> > +
> > +#define U3P_U3_CTRL(p) (U3P_U3_CTRL_0P + ((p) * 0x08))
> > +#define U3P_U2_CTRL(p) (U3P_U2_CTRL_0P + ((p) * 0x08))
> > +
> > +#define U3P_USBPHYACR0 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0000)
> > +#define PA0_RG_U2PLL_FORCE_ON (0x1 << 15)
> > +
> > +#define U3P_USBPHYACR2 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0008)
> > +#define PA2_RG_SIF_U2PLL_FORCE_EN (0x1 << 18)
> > +
> > +#define U3P_USBPHYACR5 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0014)
> > +#define PA5_RG_U2_HSTX_SRCTRL (0x7 << 12)
> > +#define PA5_RG_U2_HSTX_SRCTRL_VAL(x) ((0x7 & (x)) << 12)
> > +#define PA5_RG_U2_HS_100U_U3_EN (0x1 << 11)
> > +
> > +#define U3P_USBPHYACR6 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0018)
> > +#define PA6_RG_U2_ISO_EN (0x1 << 31)
> > +#define PA6_RG_U2_BC11_SW_EN (0x1 << 23)
> > +#define PA6_RG_U2_OTG_VBUSCMP_EN (0x1 << 20)
> > +
> > +#define U3P_U2PHYACR4 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0020)
> > +#define P2C_RG_USB20_GPIO_CTL (0x1 << 9)
> > +#define P2C_USB20_GPIO_MODE (0x1 << 8)
> > +#define P2C_U2_GPIO_CTR_MSK (P2C_RG_USB20_GPIO_CTL | P2C_USB20_GPIO_MODE)
> > +
> > +#define U3D_U2PHYDCR0 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0060)
> > +#define P2C_RG_SIF_U2PLL_FORCE_ON (0x1 << 24)
> > +
> > +#define U3P_U2PHYDTM0 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0068)
> > +#define P2C_FORCE_UART_EN (0x1 << 26)
> > +#define P2C_FORCE_DATAIN (0x1 << 23)
> > +#define P2C_FORCE_DM_PULLDOWN (0x1 << 21)
> > +#define P2C_FORCE_DP_PULLDOWN (0x1 << 20)
> > +#define P2C_FORCE_XCVRSEL (0x1 << 19)
> > +#define P2C_FORCE_SUSPENDM (0x1 << 18)
> > +#define P2C_FORCE_TERMSEL (0x1 << 17)
> > +#define P2C_RG_DATAIN (0xf << 10)
> > +#define P2C_RG_DATAIN_VAL(x) ((0xf & (x)) << 10)
> > +#define P2C_RG_DMPULLDOWN (0x1 << 7)
> > +#define P2C_RG_DPPULLDOWN (0x1 << 6)
> > +#define P2C_RG_XCVRSEL (0x3 << 4)
> > +#define P2C_RG_XCVRSEL_VAL(x) ((0x3 & (x)) << 4)
> > +#define P2C_RG_SUSPENDM (0x1 << 3)
> > +#define P2C_RG_TERMSEL (0x1 << 2)
> > +#define P2C_DTM0_PART_MASK \
> > + (P2C_FORCE_DATAIN | P2C_FORCE_DM_PULLDOWN | \
> > + P2C_FORCE_DP_PULLDOWN | P2C_FORCE_XCVRSEL | \
> > + P2C_FORCE_TERMSEL | P2C_RG_DMPULLDOWN | \
> > + P2C_RG_DPPULLDOWN | P2C_RG_TERMSEL)
> > +
> > +#define U3P_U2PHYDTM1 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x006C)
> > +#define P2C_RG_UART_EN (0x1 << 16)
> > +#define P2C_RG_VBUSVALID (0x1 << 5)
> > +#define P2C_RG_SESSEND (0x1 << 4)
> > +#define P2C_RG_AVALID (0x1 << 2)
> > +
> > +#define U3P_U3_PHYA_REG0 (SSUSB_USB30_PHYA_SIV_B_BASE + 0x0000)
> > +#define P3A_RG_U3_VUSB10_ON (1 << 5)
> > +
> > +#define U3P_U3_PHYA_REG6 (SSUSB_USB30_PHYA_SIV_B_BASE + 0x0018)
> > +#define P3A_RG_TX_EIDLE_CM (0xf << 28)
> > +#define P3A_RG_TX_EIDLE_CM_VAL(x) ((0xf & (x)) << 28)
> > +
> > +#define U3P_U3_PHYA_REG9 (SSUSB_USB30_PHYA_SIV_B_BASE + 0x0024)
> > +#define P3A_RG_RX_DAC_MUX (0x1f << 1)
> > +#define P3A_RG_RX_DAC_MUX_VAL(x) ((0x1f & (x)) << 1)
> > +
> > +#define U3P_U3PHYA_DA_REG0 (SSUSB_SIFSLV_U3PHYA_DA_BASE + 0x0)
> > +#define P3A_RG_XTAL_EXT_EN_U3 (0x3 << 10)
> > +#define P3A_RG_XTAL_EXT_EN_U3_VAL(x) ((0x3 & (x)) << 10)
> > +
> > +#define U3P_PHYD_CDR1 (SSUSB_SIFSLV_U3PHYD_BASE + 0x5c)
> > +#define P3D_RG_CDR_BIR_LTD1 (0x1f << 24)
> > +#define P3D_RG_CDR_BIR_LTD1_VAL(x) ((0x1f & (x)) << 24)
> > +#define P3D_RG_CDR_BIR_LTD0 (0x1f << 8)
> > +#define P3D_RG_CDR_BIR_LTD0_VAL(x) ((0x1f & (x)) << 8)
> > +
> > +#define U3P_XTALCTL3 (SSUSB_SIFSLV_SPLLC + 0x18)
> > +#define XC3_RG_U3_XTAL_RX_PWD (0x1 << 9)
> > +#define XC3_RG_U3_FRC_XTAL_RX_PWD (0x1 << 8)
> > +
> > +#define U3P_UX_EXIT_LFPS_PARAM (SSUSB_USB3_MAC_CSR_BASE + 0x00A0)
> > +#define RX_UX_EXIT_REF (0xff << 8)
> > +#define RX_UX_EXIT_REF_VAL (0x3 << 8)
> > +
> > +#define U3P_REF_CLK_PARAM (SSUSB_USB3_MAC_CSR_BASE + 0x00B0)
> > +#define REF_CLK_1000NS (0xff << 0)
> > +#define REF_CLK_VAL_DEF (0xa << 0)
> > +
> > +#define U3P_LINK_PM_TIMER (SSUSB_USB3_SYS_CSR_BASE + 0x0208)
> > +#define PM_LC_TIMEOUT (0xf << 0)
> > +#define PM_LC_TIMEOUT_VAL (0x3 << 0)
> > +
> > +#define U3P_TIMING_PULSE_CTRL (SSUSB_USB3_SYS_CSR_BASE + 0x02B4)
> > +#define U3T_CNT_1US (0xff << 0)
> > +#define U3T_CNT_1US_VAL (0x3f << 0) /* 62.5MHz: 63 */
> > +
> > +#define U3P_U2_TIMING_PARAM (SSUSB_USB2_CSR_BASE + 0x0040)
> > +#define U2T_VAL_1US (0xff << 0)
> > +#define U2T_VAL_1US_VAL (0x3f << 0) /* 62.5MHz: 63 */
> > +
> > +
> > +#define PERI_WK_CTRL0 0x400
> > +#define UWK_CTL1_1P_LS_E (0x1 << 0)
> > +#define UWK_CTL1_1P_LS_C(x) (((x) & 0xf) << 1)
> > +#define UWK_CTR0_0P_LS_NE (0x1 << 7) /* negedge for 0p linestate*/
> > +#define UWK_CTR0_0P_LS_PE (0x1 << 8) /* posedge */
> > +
> > +#define PERI_WK_CTRL1 0x404
> > +#define UWK_CTL1_IS_P (0x1 << 6) /* polarity for ip sleep */
> > +#define UWK_CTL1_0P_LS_P (0x1 << 7)
> > +#define UWK_CTL1_IDDIG_P (0x1 << 9) /* polarity */
> > +#define UWK_CTL1_IDDIG_E (0x1 << 10) /* enable debounce */
> > +#define UWK_CTL1_IDDIG_C(x) (((x) & 0xf) << 11) /* cycle debounce */
> > +#define UWK_CTL1_0P_LS_E (0x1 << 20)
> > +#define UWK_CTL1_0P_LS_C(x) (((x) & 0xf) << 21)
> > +#define UWK_CTL1_IS_E (0x1 << 25)
> > +#define UWK_CTL1_IS_C(x) (((x) & 0xf) << 26)
> > +
> > +enum ssusb_wakeup_src {
> > + SSUSB_WK_IP_SLEEP = 1,
> > + SSUSB_WK_LINE_STATE = 2,
> > +};
> > +
> > +struct mt65xx_u3phy {
> > + struct usb_phy phy;
> > + struct device *dev;
> > + void __iomem *mac_base; /* only device-mac regs, exclude xhci's */
> > + void __iomem *sif_base; /* include sif & sif2 */
> > + struct regmap *pericfg;
> > + struct clk *wk_deb_p0; /* port0's wakeup debounce clock */
> > + struct clk *wk_deb_p1;
> > + struct clk *u3phya_ref; /* reference clock of usb3 anolog phy */
> > + int wakeup_src;
> > + int u2port_num;
> > +};
> > +
> > +
> > +static void u3p_writel(void __iomem *base, u32 offset, u32 data)
> > +{
> > + writel(data, base + offset);
> > +}
>
> Never ever name a function 'writel' that has the arguments reversed to
> the original writel function.
>
Remove it later
> > +
> > +static u32 u3p_readl(void __iomem *base, u32 offset)
> > +{
> > + return readl(base + offset);
> > +}
> > +
> > +static void u3p_setmsk(void __iomem *base, u32 offset, u32 msk)
> > +{
> > + void __iomem *addr = base + offset;
> > +
> > + writel((readl(addr) | msk), addr);
> > +}
> > +
> > +static void u3p_clrmsk(void __iomem *base, u32 offset, u32 msk)
> > +{
> > + void __iomem *addr = base + offset;
> > +
> > + writel((readl(addr) & ~msk), addr);
> > +}
> > +
> > +static void u3p_setval(void __iomem *base, u32 offset,
> > + u32 mask, u32 value)
> > +{
> > + void __iomem *addr = base + offset;
> > + unsigned int new_value;
> > +
> > + new_value = (readl(addr) & ~mask) | value;
> > + writel(new_value, addr);
> > +}
> > +
> > +static void phy_index_power_on(struct mt65xx_u3phy *u3phy, int index)
> > +{
> > + void __iomem *sif_base = u3phy->sif_base + U3P_PHY_BASE(index);
> > +
> > + if (!index) {
> > + /* Set RG_SSUSB_VUSB10_ON as 1 after VUSB10 ready */
> > + u3p_setmsk(sif_base, U3P_U3_PHYA_REG0, P3A_RG_U3_VUSB10_ON);
> > + /* power domain iso disable */
> > + u3p_clrmsk(sif_base, U3P_USBPHYACR6, PA6_RG_U2_ISO_EN);
> > + }
> > +
> > + /* switch to USB function. (system register, force ip into usb mode) */
> > + u3p_clrmsk(sif_base, U3P_U2PHYDTM0, P2C_FORCE_UART_EN);
> > + u3p_clrmsk(sif_base, U3P_U2PHYDTM1, P2C_RG_UART_EN);
> > + if (!index)
> > + u3p_clrmsk(sif_base, U3P_U2PHYACR4, P2C_U2_GPIO_CTR_MSK);
> > +
> > + /* (force_suspendm=0) (let suspendm=1, enable usb 480MHz pll) */
> > + u3p_clrmsk(sif_base, U3P_U2PHYDTM0, P2C_FORCE_SUSPENDM);
> > + u3p_clrmsk(sif_base, U3P_U2PHYDTM0,
> > + P2C_RG_XCVRSEL | P2C_RG_DATAIN | P2C_DTM0_PART_MASK);
> > +
> > + /* DP/DM BC1.1 path Disable */
> > + u3p_clrmsk(sif_base, U3P_USBPHYACR6, PA6_RG_U2_BC11_SW_EN);
> > + /* OTG Enable */
> > + u3p_setmsk(sif_base, U3P_USBPHYACR6, PA6_RG_U2_OTG_VBUSCMP_EN);
> > + u3p_setval(sif_base, U3P_U3PHYA_DA_REG0, P3A_RG_XTAL_EXT_EN_U3,
> > + P3A_RG_XTAL_EXT_EN_U3_VAL(2));
> > + u3p_setval(sif_base, U3P_U3_PHYA_REG9, P3A_RG_RX_DAC_MUX,
> > + P3A_RG_RX_DAC_MUX_VAL(4));
> > +
> > + if (!index) {
> > + u3p_setmsk(sif_base, U3P_XTALCTL3, XC3_RG_U3_XTAL_RX_PWD);
> > + u3p_setmsk(sif_base, U3P_XTALCTL3, XC3_RG_U3_FRC_XTAL_RX_PWD);
> > + /* [mt8173]disable Change 100uA current from SSUSB */
> > + u3p_clrmsk(sif_base, U3P_USBPHYACR5, PA5_RG_U2_HS_100U_U3_EN);
> > + }
> > + u3p_setval(sif_base, U3P_U3_PHYA_REG6, P3A_RG_TX_EIDLE_CM,
> > + P3A_RG_TX_EIDLE_CM_VAL(0xe));
> > + u3p_setval(sif_base, U3P_PHYD_CDR1, P3D_RG_CDR_BIR_LTD0,
> > + P3D_RG_CDR_BIR_LTD0_VAL(0xc));
> > + u3p_setval(sif_base, U3P_PHYD_CDR1, P3D_RG_CDR_BIR_LTD1,
> > + P3D_RG_CDR_BIR_LTD1_VAL(0x3));
> > +
> > + udelay(800);
> > + u3p_setmsk(sif_base, U3P_U2PHYDTM1, P2C_RG_VBUSVALID | P2C_RG_AVALID);
> > + u3p_clrmsk(sif_base, U3P_U2PHYDTM1, P2C_RG_SESSEND);
> > +
> > + /* USB 2.0 slew rate calibration */
> > + u3p_setval(sif_base, U3P_USBPHYACR5, PA5_RG_U2_HSTX_SRCTRL,
> > + PA5_RG_U2_HSTX_SRCTRL_VAL(4));
> > +
> > + dev_dbg(u3phy->dev, "%s(%d)\n", __func__, index);
> > +}
> > +
> > +static void phy_index_power_off(struct mt65xx_u3phy *u3phy, int index)
> > +{
> > + void __iomem *sif_base = u3phy->sif_base + U3P_PHY_BASE(index);
> > +
> > + /* switch to USB function. (system register, force ip into usb mode) */
> > + u3p_clrmsk(sif_base, U3P_U2PHYDTM0, P2C_FORCE_UART_EN);
> > + u3p_clrmsk(sif_base, U3P_U2PHYDTM1, P2C_RG_UART_EN);
>
> That's the same register sequence as above in power_on. Do you really
> need to do this twice or is this more something that should be done
> during initialization once?
>
I will put them into init function
> > + if (!index)
> > + u3p_clrmsk(sif_base, U3P_U2PHYACR4, P2C_U2_GPIO_CTR_MSK);
> > +
> > + u3p_setmsk(sif_base, U3P_U2PHYDTM0, P2C_FORCE_SUSPENDM);
> > + u3p_setval(sif_base, U3P_U2PHYDTM0,
> > + P2C_RG_XCVRSEL, P2C_RG_XCVRSEL_VAL(1));
> > + u3p_setval(sif_base, U3P_U2PHYDTM0,
> > + P2C_RG_DATAIN, P2C_RG_DATAIN_VAL(0));
> > + u3p_setmsk(sif_base, U3P_U2PHYDTM0, P2C_DTM0_PART_MASK);
>
> That's four read/write accesses in a row which is really hard to read.
> This should really be something like:
>
> val = readl(sif_base + U3P_U2PHYDTM0);
> val &= ~(P2C_RG_XCVRSEL | P2C_RG_DATAIN)
> val |= P2C_FORCE_SUSPENDM | P2C_RG_XCVRSEL_VAL(1);
> writel(val, sif_base + U3P_U2PHYDTM0);
>
> Those read/modify/write access functions often have the tendency to lead
> to inefficient code.
>
Sometimes the bits should be set by sequence, check it later.
> Generally review your register accesses. There are several bits that are
> cleared multiple times but never set, like:
>
> U3P_U2PHYDTM0, P2C_FORCE_UART_EN -> cleared multiple times, never set
> U3P_USBPHYACR6, PA6_RG_U2_BC11_SW_EN -> cleared mutliple times, never set
> U3P_U2PHYDTM1, P2C_RG_UART_EN -> cleared mutliple times, never set
>
> This probably belongs to some init code executed once.
>
OK,
> > + /* DP/DM BC1.1 path Disable */
> > + u3p_clrmsk(sif_base, U3P_USBPHYACR6, PA6_RG_U2_BC11_SW_EN);
> > + /* OTG Disable */
> > + u3p_clrmsk(sif_base, U3P_USBPHYACR6, PA6_RG_U2_OTG_VBUSCMP_EN);
> > + if (!index) {
> > + /* Change 100uA current switch to USB2.0 */
> > + u3p_clrmsk(sif_base, U3P_USBPHYACR5, PA5_RG_U2_HS_100U_U3_EN);
> > + }
> > + udelay(800);
> > +
> > + /* let suspendm=0, set utmi into analog power down */
> > + u3p_clrmsk(sif_base, U3P_U2PHYDTM0, P2C_RG_SUSPENDM);
> > + udelay(1);
> > +
> > + u3p_clrmsk(sif_base, U3P_U2PHYDTM1, P2C_RG_VBUSVALID | P2C_RG_AVALID);
> > + u3p_setmsk(sif_base, U3P_U2PHYDTM1, P2C_RG_SESSEND);
> > + if (!index) {
> > + /* Set RG_SSUSB_VUSB10_ON as 1 after VUSB10 ready */
> > + u3p_clrmsk(sif_base, U3P_U3_PHYA_REG0, P3A_RG_U3_VUSB10_ON);
> > + }
> > + dev_dbg(u3phy->dev, "%s(%d)\n", __func__, index);
> > +}
> > +
> > +static void u3phy_power_on(struct mt65xx_u3phy *u3phy)
> > +{
> > + phy_index_power_on(u3phy, 0);
> > + if (u3phy->u2port_num > 1)
> > + phy_index_power_on(u3phy, 1);
> > +}
> > +
> > +static void u3phy_power_off(struct mt65xx_u3phy *u3phy)
> > +{
> > + phy_index_power_off(u3phy, 0);
> > + if (u3phy->u2port_num > 1)
> > + phy_index_power_off(u3phy, 1);
> > +}
> > +
> > +static int check_ip_clk_status(struct mt65xx_u3phy *u3phy)
> > +{
> > + int ret;
> > + int u3_port_num;
> > + int u2_port_num;
> > + u32 xhci_cap;
> > + u32 val;
> > + void __iomem *sif_base = u3phy->sif_base;
> > +
> > + xhci_cap = u3p_readl(sif_base, U3P_IP_XHCI_CAP);
> > + u3_port_num = CAP_U3_PORT_NUM(xhci_cap);
> > + u2_port_num = CAP_U2_PORT_NUM(xhci_cap);
> > +
> > + ret = readl_poll_timeout(sif_base + U3P_IP_PW_STS1, val,
> > + (val & STS1_SYSPLL_STABLE), 100, 10000);
> > + if (ret) {
> > + dev_err(u3phy->dev, "sypll is not stable!!!\n");
> > + return ret;
> > + }
> > +
> > + ret = eadl_poll_timeout(sif_base + U3P_IP_PW_STS1, val,
> > + (val & STS1_REF_RST), 100, 10000);
> > + if (ret) {
> > + dev_err(u3phy->dev, "ref_clk is still active!!!\n");
> > + return ret;
> > + }
> > +
> > + ret = readl_poll_timeout(sif_base + U3P_IP_PW_STS1, val,
> > + (val & STS1_SYS125_RST), 100, 10000);
> > + if (ret) {
> > + dev_err(u3phy->dev, "sys125_ck is still active!!!\n");
> > + return ret;
> > + }
> > +
> > + if (u3_port_num) {
> > + ret = readl_poll_timeout(sif_base + U3P_IP_PW_STS1, val,
> > + (val & STS1_U3_MAC_RST), 100, 10000);
> > + if (ret) {
> > + dev_err(u3phy->dev, "mac3_mac_ck is still active!!!\n");
> > + return ret;
> > + }
> > + }
> > +
> > + if (u2_port_num) {
> > + ret = readl_poll_timeout(sif_base + U3P_IP_PW_STS2, val,
> > + (val & STS2_U2_MAC_RST), 100, 10000);
> > + if (ret) {
> > + dev_err(u3phy->dev, "mac2_sys_ck is still active!!!\n");
> > + return ret;
> > + }
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static int u3phy_ports_enable(struct mt65xx_u3phy *u3phy)
> > +{
> > + int i;
> > + u32 temp;
> > + int u3_port_num;
> > + int u2_port_num;
> > + void __iomem *sif_base = u3phy->sif_base;
> > +
> > + temp = u3p_readl(sif_base, U3P_IP_XHCI_CAP);
> > + u3_port_num = CAP_U3_PORT_NUM(temp);
> > + u2_port_num = CAP_U2_PORT_NUM(temp);
> > + dev_dbg(u3phy->dev, "%s u2p:%d, u3p:%d\n",
> > + __func__, u2_port_num, u3_port_num);
> > +
> > + /* power on host ip */
> > + u3p_clrmsk(sif_base, U3P_IP_PW_CTRL1, CTRL1_IP_HOST_PDN);
> > +
> > + /* power on and enable all u3 ports */
> > + for (i = 0; i < u3_port_num; i++) {
> > + temp = u3p_readl(sif_base, U3P_U3_CTRL(i));
> > + temp &= ~(CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS);
> > + temp |= CTRL_U3_PORT_HOST_SEL;
> > + u3p_writel(sif_base, U3P_U3_CTRL(i), temp);
> > + }
> > +
> > + /* power on and enable all u2 ports */
> > + for (i = 0; i < u2_port_num; i++) {
> > + temp = u3p_readl(sif_base, U3P_U2_CTRL(i));
> > + temp &= ~(CTRL_U2_PORT_PDN | CTRL_U2_PORT_DIS);
> > + temp |= CTRL_U2_PORT_HOST_SEL;
> > + u3p_writel(sif_base, U3P_U2_CTRL(i), temp);
> > + }
> > + return check_ip_clk_status(u3phy);
> > +}
> > +
> > +static int u3phy_ports_disable(struct mt65xx_u3phy *u3phy)
> > +{
> > + int i;
> > + u32 temp;
> > + int ret;
> > + int u3_port_num;
> > + int u2_port_num;
> > + void __iomem *sif_base = u3phy->sif_base;
> > +
> > + temp = u3p_readl(sif_base, U3P_IP_XHCI_CAP);
> > + u3_port_num = CAP_U3_PORT_NUM(temp);
> > + u2_port_num = CAP_U2_PORT_NUM(temp);
> > + dev_dbg(u3phy->dev, "%s u2p:%d, u3p:%d\n",
> > + __func__, u2_port_num, u3_port_num);
> > +
> > + /* power on and enable all u3 ports */
>
> This comment seems wrong.
>
Yes, It is my mistake
> > + for (i = 0; i < u3_port_num; i++) {
> > + temp = u3p_readl(sif_base, U3P_U3_CTRL(i));
> > + temp |= CTRL_U3_PORT_PDN;
> > + u3p_writel(sif_base, U3P_U3_CTRL(i), temp);
> > + }
> > +
> > + /* power on and enable all u2 ports */
>
> ditto
>
> > + for (i = 0; i < u2_port_num; i++) {
> > + temp = u3p_readl(sif_base, U3P_U2_CTRL(i));
> > + temp |= CTRL_U2_PORT_PDN;
> > + u3p_writel(sif_base, U3P_U2_CTRL(i), temp);
> > + }
> > +
> > + /* power off host ip */
> > + u3p_setmsk(sif_base, U3P_IP_PW_CTRL1, CTRL1_IP_HOST_PDN);
> > + u3p_setmsk(sif_base, U3P_IP_PW_CTRL2, CTRL2_IP_DEV_PDN);
> > +
> > + ret = readl_poll_timeout(sif_base + U3P_IP_PW_STS1, temp,
> > + (temp & STS1_IP_SLEEP_STS), 100, 100000);
> > + if (ret) {
> > + dev_err(u3phy->dev, "ip sleep failed!!!\n");
> > + return ret;
> > + }
> > + return 0;
> > +}
> > +
> > +static void u3phy_timing_init(struct mt65xx_u3phy *u3phy)
> > +{
> > + void __iomem *mbase = u3phy->mac_base;
> > + int u3_port_num;
> > + u32 temp;
> > +
> > + temp = u3p_readl(u3phy->sif_base, U3P_IP_XHCI_CAP);
> > + u3_port_num = CAP_U3_PORT_NUM(temp);
> > +
> > + if (u3_port_num) {
> > + /* set MAC reference clock speed */
> > + u3p_setval(mbase, U3P_UX_EXIT_LFPS_PARAM,
> > + RX_UX_EXIT_REF, RX_UX_EXIT_REF_VAL);
> > + /* set REF_CLK */
> > + u3p_setval(mbase, U3P_REF_CLK_PARAM,
> > + REF_CLK_1000NS, REF_CLK_VAL_DEF);
> > + /* set SYS_CLK */
> > + u3p_setval(mbase, U3P_TIMING_PULSE_CTRL,
> > + U3T_CNT_1US, U3T_CNT_1US_VAL);
> > + /* set LINK_PM_TIMER=3 */
> > + u3p_setval(mbase, U3P_LINK_PM_TIMER,
> > + PM_LC_TIMEOUT, PM_LC_TIMEOUT_VAL);
>
> This fiddles in the register space of the xhci controller. Should be
> done in the xhci driver, not here in the phy driver.
>
done
> > + }
> > + u3p_setval(mbase, U3P_U2_TIMING_PARAM, U2T_VAL_1US, U2T_VAL_1US_VAL);
> > +}
> > +
> > +static int u3phy_clks_enable(struct mt65xx_u3phy *u3phy)
> > +{
> > + int ret;
> > +
> > + ret = clk_prepare_enable(u3phy->u3phya_ref);
> > + if (ret) {
> > + dev_err(u3phy->dev, "failed to enable u3phya_ref\n");
> > + goto u3phya_ref_err;
> > + }
> > + ret = clk_prepare_enable(u3phy->wk_deb_p0);
> > + if (ret) {
> > + dev_err(u3phy->dev, "failed to enable wk_deb_p0\n");
> > + goto usb_p0_err;
> > + }
> > + if (u3phy->u2port_num > 1) {
> > + ret = clk_prepare_enable(u3phy->wk_deb_p1);
> > + if (ret) {
> > + dev_err(u3phy->dev, "failed to enable wk_deb_p1\n");
> > + goto usb_p1_err;
> > + }
> > + }
> > + udelay(50);
> > +
> > + return 0;
> > +
> > +usb_p1_err:
> > + clk_disable_unprepare(u3phy->wk_deb_p0);
> > +usb_p0_err:
> > + clk_disable_unprepare(u3phy->u3phya_ref);
> > +u3phya_ref_err:
> > + return -EINVAL;
> > +}
> > +
> > +static void u3phy_clks_disable(struct mt65xx_u3phy *u3phy)
> > +{
> > + if (u3phy->u2port_num > 1)
> > + clk_disable_unprepare(u3phy->wk_deb_p1);
> > + clk_disable_unprepare(u3phy->wk_deb_p0);
> > + clk_disable_unprepare(u3phy->u3phya_ref);
> > +}
> > +
> > +/* only clocks can be turn off for ip-sleep wakeup mode */
> > +static void usb_wakeup_ip_sleep_en(struct mt65xx_u3phy *u3phy)
> > +{
> > + u32 tmp;
> > + struct regmap *pericfg = u3phy->pericfg;
> > +
> > + regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
> > + tmp &= ~UWK_CTL1_IS_P;
> > + tmp &= ~(UWK_CTL1_IS_C(0xf));
> > + tmp |= UWK_CTL1_IS_C(0x8);
> > + regmap_write(pericfg, PERI_WK_CTRL1, tmp);
> > + regmap_write(pericfg, PERI_WK_CTRL1, tmp | UWK_CTL1_IS_E);
> > +
> > + regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
> > + dev_dbg(u3phy->dev, "%s(): WK_CTRL1[P6,E25,C26:29]=%#x\n", __func__,
> > + tmp);
> > +}
> > +
> > +static void usb_wakeup_ip_sleep_dis(struct mt65xx_u3phy *u3phy)
> > +{
> > + u32 tmp;
> > +
> > + regmap_read(u3phy->pericfg, PERI_WK_CTRL1, &tmp);
> > + tmp &= ~UWK_CTL1_IS_E;
> > + regmap_write(u3phy->pericfg, PERI_WK_CTRL1, tmp);
> > +}
> > +
> > +/*
> > +* for line-state wakeup mode, phy's power should not power-down
> > +* and only support cable plug in/out
> > +*/
> > +static void usb_wakeup_line_state_en(struct mt65xx_u3phy *u3phy)
> > +{
> > + u32 tmp;
> > + struct regmap *pericfg = u3phy->pericfg;
> > +
> > + /* line-state of u2-port0 */
> > + regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
> > + tmp &= ~UWK_CTL1_0P_LS_P;
> > + tmp &= ~(UWK_CTL1_0P_LS_C(0xf));
> > + tmp |= UWK_CTL1_0P_LS_C(0x8);
> > + regmap_write(pericfg, PERI_WK_CTRL1, tmp);
> > + regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
> > + regmap_write(pericfg, PERI_WK_CTRL1, tmp | UWK_CTL1_0P_LS_E);
> > +
> > + /* line-state of u2-port1 if support */
> > + if (u3phy->u2port_num > 1) {
> > + regmap_read(pericfg, PERI_WK_CTRL0, &tmp);
> > + tmp &= ~(UWK_CTL1_1P_LS_C(0xf));
> > + tmp |= UWK_CTL1_1P_LS_C(0x8);
> > + regmap_write(pericfg, PERI_WK_CTRL0, tmp);
> > + regmap_write(pericfg, PERI_WK_CTRL0, tmp | UWK_CTL1_1P_LS_E);
> > + }
> > +}
> > +
> > +static void usb_wakeup_line_state_dis(struct mt65xx_u3phy *u3phy)
> > +{
> > + u32 tmp;
> > + struct regmap *pericfg = u3phy->pericfg;
> > +
> > + regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
> > + tmp &= ~UWK_CTL1_0P_LS_E;
> > + regmap_write(pericfg, PERI_WK_CTRL1, tmp);
> > +
> > + if (u3phy->u2port_num > 1) {
> > + regmap_read(pericfg, PERI_WK_CTRL0, &tmp);
> > + tmp &= ~UWK_CTL1_1P_LS_E;
> > + regmap_write(pericfg, PERI_WK_CTRL0, tmp);
> > + }
> > +}
> > +
> > +static void usb_wakeup_enable(struct mt65xx_u3phy *u3phy)
> > +{
> > + if (u3phy->wakeup_src == SSUSB_WK_IP_SLEEP)
> > + usb_wakeup_ip_sleep_en(u3phy);
> > + else if (u3phy->wakeup_src == SSUSB_WK_LINE_STATE)
> > + usb_wakeup_line_state_en(u3phy);
> > +}
> > +
> > +static void usb_wakeup_disable(struct mt65xx_u3phy *u3phy)
> > +{
> > + if (u3phy->wakeup_src == SSUSB_WK_IP_SLEEP)
> > + usb_wakeup_ip_sleep_dis(u3phy);
> > + else if (u3phy->wakeup_src == SSUSB_WK_LINE_STATE)
> > + usb_wakeup_line_state_dis(u3phy);
> > +}
> > +
> > +static int mt65xx_u3phy_init(struct usb_phy *phy)
> > +{
> > + struct mt65xx_u3phy *u3phy;
> > + int ret;
> > +
> > + u3phy = container_of(phy, struct mt65xx_u3phy, phy);
> > + dev_dbg(u3phy->dev, "%s+\n", __func__);
> > +
> > + ret = pm_runtime_get_sync(u3phy->dev);
> > + if (ret < 0)
> > + goto pm_err;
> > +
> > + ret = u3phy_clks_enable(u3phy);
> > + if (ret) {
> > + dev_err(u3phy->dev, "failed to enable clks\n");
> > + goto clks_err;
> > + }
> > +
> > + /* reset whole ip */
> > + u3p_setmsk(u3phy->sif_base, U3P_IP_PW_CTRL0, CTRL0_IP_SW_RST);
> > + u3p_clrmsk(u3phy->sif_base, U3P_IP_PW_CTRL0, CTRL0_IP_SW_RST);
> > +
> > + ret = u3phy_ports_enable(u3phy);
> > + if (ret) {
> > + dev_err(u3phy->dev, "failed to enable ports\n");
> > + goto port_err;
> > + }
> > + u3phy_timing_init(u3phy);
> > + u3phy_power_on(u3phy);
> > + msleep(40);
> > +
> > + return 0;
> > +
> > +port_err:
> > + u3phy_clks_disable(u3phy);
> > +clks_err:
> > + pm_runtime_put_sync(u3phy->dev);
> > +pm_err:
> > + return ret;
> > +}
> > +
> > +
> > +static void mt65xx_u3phy_shutdown(struct usb_phy *phy)
> > +{
> > + struct mt65xx_u3phy *u3phy;
> > +
> > + u3phy = container_of(phy, struct mt65xx_u3phy, phy);
> > + u3phy_power_off(u3phy);
> > + u3phy_clks_disable(u3phy);
> > + pm_runtime_put_sync(u3phy->dev);
> > +}
> > +
> > +
> > +static int mt65xx_u3phy_suspend(struct usb_phy *x, int suspend)
> > +{
> > + struct mt65xx_u3phy *u3phy = container_of(x, struct mt65xx_u3phy, phy);
> > +
> > + if (suspend) {
> > + u3phy_ports_disable(u3phy);
> > + u3phy_power_off(u3phy);
> > + u3phy_clks_disable(u3phy);
> > + usb_wakeup_enable(u3phy);
> > + } else {
> > + usb_wakeup_disable(u3phy);
> > + u3phy_clks_enable(u3phy);
> > + u3phy_power_on(u3phy);
> > + u3phy_ports_enable(u3phy);
> > + }
> > + return 0;
> > +}
> > +
> > +
> > +static const struct of_device_id mt65xx_u3phy_id_table[] = {
> > + { .compatible = "mediatek,mt8173-u3phy",},
> > + { },
> > +};
> > +MODULE_DEVICE_TABLE(of, mt65xx_u3phy_id_table);
> > +
> > +
> > +static int mt65xx_u3phy_probe(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct device_node *np = dev->of_node;
> > + struct resource *mac_res;
> > + struct resource *sif_res;
> > + struct mt65xx_u3phy *u3phy;
> > + int retval = -ENOMEM;
> > +
> > + u3phy = devm_kzalloc(&pdev->dev, sizeof(*u3phy), GFP_KERNEL);
> > + if (!u3phy)
> > + goto err;
>
> No need for goto if all you do there is to return. return here.
Ok, I will revise it
Thank you very much.
>
> Sascha
>
>
^ permalink raw reply [flat|nested] 22+ messages in thread
end of thread, other threads:[~2015-07-20 15:41 UTC | newest]
Thread overview: 22+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-07-08 9:41 [PATCH v2 0/5] Mediatek xHCI support Chunfeng Yun
2015-07-08 9:41 ` [PATCH v2 1/5] dt-bindings: Add usb3.0 phy binding for MT65xx SoCs Chunfeng Yun
2015-07-10 5:10 ` Sascha Hauer
2015-07-14 6:19 ` chunfeng yun
2015-07-14 7:45 ` Sascha Hauer
2015-07-15 12:33 ` chunfeng yun
2015-07-08 9:41 ` [PATCH v2 2/5] dt-bindings: Add a binding for Mediatek xHCI host controller Chunfeng Yun
2015-07-10 8:31 ` Roger Quadros
2015-07-14 2:36 ` chunfeng yun
2015-07-14 2:50 ` chunfeng yun
2015-07-20 14:24 ` chunfeng yun
2015-07-08 9:41 ` [PATCH v2 3/5] usb: phy: add usb3.0 phy driver for mt65xx SoCs Chunfeng Yun
2015-07-10 6:42 ` Sascha Hauer
2015-07-20 15:41 ` chunfeng yun
2015-07-08 9:41 ` [PATCH v2 4/5] xhci: mediatek: support MTK xHCI host controller Chunfeng Yun
2015-07-13 14:52 ` John Crispin
2015-07-20 14:51 ` chunfeng yun
2015-07-08 9:41 ` [PATCH v2 5/5] arm64: dts: mediatek: add xHCI & usb phy for mt8173 Chunfeng Yun
2015-07-14 10:12 ` Daniel Kurtz
2015-07-20 14:39 ` chunfeng yun
2015-07-20 14:51 ` Yingjoe Chen
2015-07-20 14:59 ` Daniel Kurtz
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