Re: [PATCH v3 5/6] media: sun4i: Add H3 deinterlace driver

["Jernej Škrabec" <jernej.skrabec@siol.net>]

Dne četrtek, 17. oktober 2019 ob 11:28:00 CEST je Maxime Ripard napisal(a):
> Hi,
> 
> I have a small comment that can definitely be addressed in a subsequent
> patch
> On Wed, Oct 16, 2019 at 09:28:06PM +0200, Jernej Skrabec wrote:
> > +	dev->bus_clk = devm_clk_get(dev->dev, "bus");
> > +	if (IS_ERR(dev->bus_clk)) {
> > +		dev_err(dev->dev, "Failed to get bus clock\n");
> > +
> > +		return PTR_ERR(dev->bus_clk);
> > +	}
> > +
> > +	dev->mod_clk = devm_clk_get(dev->dev, "mod");
> > +	if (IS_ERR(dev->mod_clk)) {
> > +		dev_err(dev->dev, "Failed to get mod clock\n");
> > +
> > +		return PTR_ERR(dev->mod_clk);
> > +	}
> > +
> > +	dev->ram_clk = devm_clk_get(dev->dev, "ram");
> > +	if (IS_ERR(dev->ram_clk)) {
> > +		dev_err(dev->dev, "Failed to get ram clock\n");
> > +
> > +		return PTR_ERR(dev->ram_clk);
> > +	}
> > +
> > +	dev->rstc = devm_reset_control_get(dev->dev, NULL);
> > +	if (IS_ERR(dev->rstc)) {
> > +		dev_err(dev->dev, "Failed to get reset control\n");
> > +
> > +		return PTR_ERR(dev->rstc);
> > +	}
> > +
> > +	clk_set_rate_exclusive(dev->mod_clk, 300000000);
> 
> clk_set_rate_exclusive puts a pretty big constraint on the clock tree,
> and we shouldn't really enforce it if the device is unused.

That is true in general, but as I said before, that is not really an issue for 
H3. Deinterlace clock default parent is peripheral clock, which is fixed to 600 
MHz and doesn't change.

> 
> I guess we should move it to the runtime_pm resume hook (with the
> put_exclusive call in suspend).

Ok, I'll move it in case that this deinterlace core is used on other SoCs with 
non-fixed parent clock.

> 
> Otherwise, that patch is
> Acked-by: Maxime Ripard <mripard@kernel.org>

Thanks!

Best regards,
Jernej