From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752941AbbIPTDv (ORCPT ); Wed, 16 Sep 2015 15:03:51 -0400 Received: from eu-smtp-delivery-143.mimecast.com ([146.101.78.143]:62112 "EHLO eu-smtp-delivery-143.mimecast.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752169AbbIPTDo (ORCPT ); Wed, 16 Sep 2015 15:03:44 -0400 From: Jeremy Linton To: linux-arm-kernel@lists.infradead.org Cc: catalin.marinas@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, dwoods@ezcip.com, steve.capper@arm.com, shijie.huang@arm.com, Jeremy Linton Subject: [PATCH 2/7] arm64: Shorten lines which exceed 80 characters Date: Wed, 16 Sep 2015 14:03:01 -0500 Message-Id: <1442430186-9083-3-git-send-email-jeremy.linton@arm.com> X-Mailer: git-send-email 2.4.3 In-Reply-To: <1442430186-9083-1-git-send-email-jeremy.linton@arm.com> References: <1442430186-9083-1-git-send-email-jeremy.linton@arm.com> X-OriginalArrivalTime: 16 Sep 2015 19:03:41.0009 (UTC) FILETIME=[669C0410:01D0F0B2] X-MC-Unique: Y73hh3nMS8CsITE1rn4NLg-1 Content-Type: text/plain; charset=WINDOWS-1252 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from quoted-printable to 8bit by mail.home.local id t8GJ3vQ8004283 PTE definitions in this file exceed 80 characters Signed-off-by: Jeremy Linton --- arch/arm64/include/asm/pgtable-hwdef.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h index 24154b0..4489cf6 100644 --- a/arch/arm64/include/asm/pgtable-hwdef.h +++ b/arch/arm64/include/asm/pgtable-hwdef.h @@ -99,14 +99,14 @@ #define PTE_TYPE_FAULT (_AT(pteval_t, 0) << 0) #define PTE_TYPE_PAGE (_AT(pteval_t, 3) << 0) #define PTE_TABLE_BIT (_AT(pteval_t, 1) << 1) -#define PTE_USER (_AT(pteval_t, 1) << 6) /* AP[1] */ -#define PTE_RDONLY (_AT(pteval_t, 1) << 7) /* AP[2] */ -#define PTE_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */ -#define PTE_AF (_AT(pteval_t, 1) << 10) /* Access Flag */ -#define PTE_NG (_AT(pteval_t, 1) << 11) /* nG */ -#define PTE_DBM (_AT(pteval_t, 1) << 51) /* Dirty Bit Management */ -#define PTE_PXN (_AT(pteval_t, 1) << 53) /* Privileged XN */ -#define PTE_UXN (_AT(pteval_t, 1) << 54) /* User XN */ +#define PTE_USER (_AT(pteval_t, 1) << 6) /* AP[1] */ +#define PTE_RDONLY (_AT(pteval_t, 1) << 7) /* AP[2] */ +#define PTE_SHARED (_AT(pteval_t, 3) << 8) /* inner shareable */ +#define PTE_AF (_AT(pteval_t, 1) << 10) /* Access Flag */ +#define PTE_NG (_AT(pteval_t, 1) << 11) /* nG */ +#define PTE_DBM (_AT(pteval_t, 1) << 51) /* Dirty Bit Mgmt */ +#define PTE_PXN (_AT(pteval_t, 1) << 53) /* Privileged XN */ +#define PTE_UXN (_AT(pteval_t, 1) << 54) /* User XN */ /* * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers). -- 2.4.3