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Peter Anvin" CC: Daniel J Blueman , , , Daniel Lezcano , Steffen Persvold Subject: [PATCH 4/4] x86: Introduce Numachip2 timer mechanisms Date: Mon, 21 Sep 2015 01:02:02 +0800 Message-ID: <1442768522-19217-4-git-send-email-daniel@numascale.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1442768522-19217-1-git-send-email-daniel@numascale.com> References: <1442768522-19217-1-git-send-email-daniel@numascale.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [175.156.157.249] X-ClientProxiedBy: DB5PR03CA0064.eurprd03.prod.outlook.com (25.164.34.32) To AM4PR07MB1298.eurprd07.prod.outlook.com (25.164.81.156) X-Microsoft-Exchange-Diagnostics: 1;AM4PR07MB1298;2:/hsThpn4fd7vzRT3pkN0HGgWSWpvpBylFVDmehnWRnYZpljh8aDW1YWljDJWWzaM7VMeTgHMtyHNRAygwYNCGiSFdf3aZ1o2lzJawl+Ua3rFWLI8BKo2U+1pQrV+klkE8bWCBIE8eH6pPgFEyjoIfzHnW3V7VAc3Lx4STwl5ce8=;3:fuDHXxycFTvJl8SY4W6b7tIUuyNRrB74yp+DDkuwfLIc9nbuRddgtTCGI/XWHw0IyaSRuQgVtG4aBZfArJDYm63aKFZdWtsdZb9zKfu9Jl2ytzIExoBkuIGSKwk+GBPa99woMajL5dLswDI34WgdrA==;25:PVJKK1QISvYXMsLfIU/geY9qAFMgD/BT1FylCxXiUZp8bzmsg3VP5pT0EHfkGAi4GkVx6SwfTlH7IUe1RJG3KDti1zlVLwMwlY7rFvrTd4mpz+aumNKaPAeOHr2ajxPHygZkARpPxLN99q72ulANkPg72Jc7dWAOpz3KPFdCIM0n9X76NWo/3a4XzE5NgH5FF1vjQlSc0wsdRYDzo2r/DtTYeYufeeod1/xgPOKUgTX3Ew3Wlfi+RmwOyyi/PgFh;4:Yhy8ul2xfILOrbV39pOgYPri0tsI8ohb9y3mBLF+Tfq0RpaaSKAOmQM0AwLs/En28xTbIQ2J3p1iNKhLH/J+1GgOW3PoJHwBm7UOjdk5ARF4sWflUI+LPjDJFVC2AzHfmc68FZfKofOPE2LQIgHhdwT9qVh7vA0ADSxYTbe87h8PSpdsk7z4meKIhAApWFDwXS5XEM3NEEuYyFJgyi40WFcW+dN1AogMhSuBzkHRL2g= X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:AM4PR07MB1298; X-Exchange-Antispam-Report-CFA: BCL:0;PCL:0;RULEID:;SRVR:AM4PR07MB1298;BCL:0;PCL:0;RULEID:;SRVR:AM4PR07MB1298; X-Forefront-PRVS: 0705EB1700 X-Forefront-Antispam-Report: SFV:NSPM;SFS:(10019020)(6009001)(6069001)(189002)(199003)(33646002)(122386002)(46102003)(101416001)(92566002)(19580395003)(76176999)(62966003)(19580405001)(5001770100001)(77156002)(50986999)(87976001)(86362001)(36756003)(4001540100001)(40100003)(5001830100001)(81156007)(97736004)(50226001)(5001860100001)(189998001)(2950100001)(42186005)(106356001)(47776003)(77096005)(68736005)(105586002)(5004730100002)(229853001)(5003940100001)(64706001)(50466002)(48376002)(66066001)(2004002);DIR:OUT;SFP:1102;SCL:1;SRVR:AM4PR07MB1298;H:localhost.localdomain;FPR:;SPF:None;PTR:InfoNoRecords;MX:1;A:1;LANG:en; X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1;AM4PR07MB1298;23:eZ3gw3gUQb4gDH/uHB4WtwiRiFB/CmTx3OuTljEyG?= =?us-ascii?Q?XdNtY5DeDW6+vhaV6jEMoUdsPHk83raAzbEA8xq01zBicu/ZG8tme1Cnf9g3?= =?us-ascii?Q?V/rw3zVVAeSzvUEhLjhP5d1izDACJCRcVIx4T/fr87G9z0NHMUDoSDjWXhUQ?= =?us-ascii?Q?qLD6W0oLoi9qnrQfCq+xyXxUwc17cy7opLFTAXFJ/8eYekfOv0n37mCWXV+j?= =?us-ascii?Q?/vbVyXuMEbIP9fzgALc97bI1AKzskNcWQXvus/nSLXr8ahVW+RC57xOtJwly?= =?us-ascii?Q?r/pI8uaANhHpkbKNZ2Dl4Kh8joQn0r1zD6IAqCHBuz2fGpDTL3mqXbzZCvo5?= =?us-ascii?Q?/fs5zzH2zbUzEAG7Q74gXMBbAHpu2xX+SkcCloeZfOk7pK+5WcJeohKgE6mD?= =?us-ascii?Q?cOM9mwqXPf4S5c51qE9KKPQuZBgYpE8vXd8DjebpYyS/aiOsKykDU7C1xFwX?= =?us-ascii?Q?XyDfZOc7Yu/YG6e8my9gkKE8LQ42gASM7Fts6T+MRpJ87mCXVgmxp9BO07iy?= =?us-ascii?Q?spXH7UyI3RqopFeIz9AFJcwbiAx2pbiJI5W95MqsrC2V5tj+l1VR/w04KI+l?= =?us-ascii?Q?3JXIwsac8Cf3TdwuVInQ6HJxOLfDo/GsUQVNI7kghiOMWeXqBMNYo4Z4rGvC?= =?us-ascii?Q?z8YCnWDSEQ0wd9uzI6oHKoW/YY43MxBWr/9+4NAMRbvH+L/4HguuxxboLdgG?= =?us-ascii?Q?cxoBl2Xke4OPdsh2L+ZqjXMa5wOz5zQTjw/UVpfEVDCuYIZHzIcXnaycpf9u?= =?us-ascii?Q?7MjIPcADgngGCzbzBNmK+zv/nVnPuTYeXmu0ru26JnGyCNFpGByvf45Zvu8E?= =?us-ascii?Q?sCjgQonjAi/sY9TbChksaoGztwrPNXXUDovsCtN4KsQuWkN653Fs5bfV/Ej7?= =?us-ascii?Q?6F1J1gJBWH09mlmvgoND4s3E/9hLIapvGvXdTh09NQeHyUZplMZQoueXyFQQ?= =?us-ascii?Q?LtzPIWppYHkj4dzRX3TqHJPRKRKTyMlN4IXex7xQZYTOzVRDS1IIw6E8v0Fp?= =?us-ascii?Q?GnTq2+l6ln2rJK+fLqH9OdFaXYm3MX7Ez9ij9bnTFU+Ot+OVA7fNICfTmgFD?= =?us-ascii?Q?6YRz2w92nRH3YiXTOngnhyQEsYe+BDx6I18gXAKYBxyTZBfyo7hvi4Fb5C5x?= =?us-ascii?Q?k0qmXfWh1myeRwvaesIVHIB7Pi+CeTD?= X-Microsoft-Exchange-Diagnostics: 1;AM4PR07MB1298;5:rjhCBqOMDPx2v63FoK2N+LKz3CzrjqhRMs8UkxNmm+vt3vPhhWS3264mk+uuvvI6lbKj/A6A/FzPA9ofZxkqxC2h/wFR2mkWr3Gf7wVA+7A1OllOVs3BIcbGaidrwVACvtce8DRfQpQ1XvLySj4ZoA==;24:8/JYzoVsYclwsVPySyrfckD4O8l9D9O1HghbTmOXtzSmkP11eDFDzopir9YnebGR3BkWUn71CLEkQnswMtkVKUlZ/7r+EM7GA0wA1Sw2YH8=;20:xtDX0uyYxLVmw8XYN8unp/jeQWd6BXkymT3a70OdVQ4b0YMPHYkKFkbfNpwR6SyK8rsG8p5Rw88ixsabMg8wBA== SpamDiagnosticOutput: 1:23 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: numascale.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Sep 2015 17:02:27.9652 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM4PR07MB1298 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add 1GHz 64-bit Numachip2 clocksource timer support for accurate system-wide timekeeping, as core TSCs are unsynchronised. Additionally, add a per-core clockevent mechanism that interrupts via the platform IPI vector after a programmed period. Signed-off-by: Daniel J Blueman Acked-by: Steffen Persvold --- arch/x86/include/asm/numachip/numachip_csr.h | 9 +++++++++ drivers/clocksource/Makefile | 1 + 2 files changed, 10 insertions(+) diff --git a/arch/x86/include/asm/numachip/numachip_csr.h b/arch/x86/include/asm/numachip/numachip_csr.h index e09d845..29719ee 100644 --- a/arch/x86/include/asm/numachip/numachip_csr.h +++ b/arch/x86/include/asm/numachip/numachip_csr.h @@ -59,6 +59,10 @@ static inline void write_lcsr(unsigned long offset, unsigned int val) #define NUMACHIP2_LCSR_BASE 0xf0000000UL #define NUMACHIP2_LCSR_SIZE 0x1000000UL #define NUMACHIP2_APIC_ICR 0x100000 +#define NUMACHIP2_TIMER_DEADLINE 0x200000 +#define NUMACHIP2_TIMER_INT 0x200008 +#define NUMACHIP2_TIMER_NOW 0x200018 +#define NUMACHIP2_TIMER_RESET 0x200020 static inline void __iomem *numachip2_lcsr_address(unsigned long offset) { @@ -86,4 +90,9 @@ static inline void numachip2_write64_lcsr(unsigned long offset, u64 val) writeq(val, numachip2_lcsr_address(offset)); } +static inline unsigned int numachip2_timer(void) +{ + return (smp_processor_id() % 48) << 6; +} + #endif /* _ASM_X86_NUMACHIP_NUMACHIP_CSR_H */ diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index 5c00863..57dfad3 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -62,3 +62,4 @@ obj-$(CONFIG_H8300) += h8300_timer8.o obj-$(CONFIG_H8300_TMR16) += h8300_timer16.o obj-$(CONFIG_H8300_TPU) += h8300_tpu.o obj-$(CONFIG_CLKSRC_ST_LPC) += clksrc_st_lpc.o +obj-$(CONFIG_X86_NUMACHIP) += numachip.o diff --git a/drivers/clocksource/numachip.c b/drivers/clocksource/numachip.c new file mode 100644 index 0000000..5e4f90e --- /dev/null +++ b/drivers/clocksource/numachip.c @@ -0,0 +1,95 @@ +/* + * + * Copyright (C) 2015 Numascale AS. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include + +#include +#include +#include + +static DEFINE_PER_CPU(struct clock_event_device, cpu_ced); + +static cycles_t numachip2_timer_read(struct clocksource *cs) +{ + return numachip2_read64_lcsr(NUMACHIP2_TIMER_NOW); +} + +static struct clocksource numachip2_clocksource = { + .name = "numachip2", + .rating = 295, + .read = numachip2_timer_read, + .mask = CLOCKSOURCE_MASK(64), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, + .mult = 1, + .shift = 0, +}; + +static int numachip2_set_next_event(unsigned long delta, struct clock_event_device *ced) +{ + numachip2_write64_lcsr(NUMACHIP2_TIMER_DEADLINE + numachip2_timer(), + delta); + return 0; +} + +static struct clock_event_device numachip2_clockevent = { + .name = "numachip2", + .rating = 400, + .set_next_event = numachip2_set_next_event, + .features = CLOCK_EVT_FEAT_ONESHOT, + .mult = 1, + .shift = 0, + .min_delta_ns = 1250, + .max_delta_ns = LONG_MAX, +}; + +static void numachip_timer_interrupt(void) +{ + struct clock_event_device *ced = this_cpu_ptr(&cpu_ced); + + ced->event_handler(ced); +} + +static __init void numachip_timer_each(struct work_struct *work) +{ + unsigned local_apicid = __this_cpu_read(x86_cpu_to_apicid) & 0xff; + struct clock_event_device *ced = this_cpu_ptr(&cpu_ced); + + /* Setup IPI vector to local core and relative timing mode */ + numachip2_write64_lcsr(NUMACHIP2_TIMER_INT + numachip2_timer(), + | (X86_PLATFORM_IPI_VECTOR << 14) | + (local_apicid << 6)); + + *ced = numachip2_clockevent; + ced->cpumask = cpumask_of(smp_processor_id()); + clockevents_register_device(ced); +} + +static int __init numachip_timer_init(void) +{ + if (numachip_system != 2) + return -ENODEV; + + /* Reset timer */ + numachip2_write64_lcsr(NUMACHIP2_TIMER_RESET, 0); + clocksource_register_hz(&numachip2_clocksource, NSEC_PER_SEC); + + /* Setup per-cpu clockevents */ + x86_platform_ipi_callback = numachip_timer_interrupt; + schedule_on_each_cpu(&numachip_timer_each); + + return 0; +} + +arch_initcall(numachip_timer_init); -- 2.5.0