From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753903AbbJHAtt (ORCPT ); Wed, 7 Oct 2015 20:49:49 -0400 Received: from mail-pa0-f47.google.com ([209.85.220.47]:34070 "EHLO mail-pa0-f47.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753848AbbJHAtT (ORCPT ); Wed, 7 Oct 2015 20:49:19 -0400 From: Douglas Anderson To: John Youn Cc: Yunzhi Li , =?UTF-8?q?Heiko=20St=C3=BCbner?= , linux-rockchip@lists.infradead.org, Julius Werner , Douglas Anderson , johnyoun@synopsys.com, gregkh@linuxfoundation.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/5] usb: dwc2: Speed dwc2_get_hwparams() on some host-only ports Date: Wed, 7 Oct 2015 17:48:40 -0700 Message-Id: <1444265321-16768-5-git-send-email-dianders@chromium.org> X-Mailer: git-send-email 2.6.0.rc2.230.g3dd15c0 In-Reply-To: <1444265321-16768-1-git-send-email-dianders@chromium.org> References: <1444265321-16768-1-git-send-email-dianders@chromium.org> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On some host-only DWC2 ports (like the one in rk3288) when we set GUSBCFG_FORCEHOSTMODE in GUSBCFG and then read back, we don't see the bit set. Presumably that's because the port is always forced to HOST mode so there's no reason to implement these status bits. Since we know dwc2_core_reset() is always called before dwc2_get_hwparams() and we know dwc2_core_reset() should have set GUSBCFG_FORCEHOSTMODE whenever hsotg->dr_mode == USB_DR_MODE_HOST, we can just check hsotg->dr_mode to decide that we can skip the delays in dwc2_get_hwparams(). Signed-off-by: Douglas Anderson --- drivers/usb/dwc2/core.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/usb/dwc2/core.c b/drivers/usb/dwc2/core.c index 9f1c438..27ade0c 100644 --- a/drivers/usb/dwc2/core.c +++ b/drivers/usb/dwc2/core.c @@ -3070,7 +3070,7 @@ int dwc2_get_hwparams(struct dwc2_hsotg *hsotg) unsigned width; u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4; u32 hptxfsiz, grxfsiz, gnptxfsiz; - u32 gusbcfg; + u32 gusbcfg = 0; /* * Attempt to ensure this device is really a DWC_otg Controller. @@ -3103,8 +3103,8 @@ int dwc2_get_hwparams(struct dwc2_hsotg *hsotg) dev_dbg(hsotg->dev, "grxfsiz=%08x\n", grxfsiz); /* Force host mode to get HPTXFSIZ / GNPTXFSIZ exact power on value */ - gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG); - if (!(gusbcfg & GUSBCFG_FORCEHOSTMODE)) { + if (hsotg->dr_mode != USB_DR_MODE_HOST) { + gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG); dwc2_writel(gusbcfg | GUSBCFG_FORCEHOSTMODE, hsotg->regs + GUSBCFG); usleep_range(100000, 150000); @@ -3114,7 +3114,7 @@ int dwc2_get_hwparams(struct dwc2_hsotg *hsotg) hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ); dev_dbg(hsotg->dev, "gnptxfsiz=%08x\n", gnptxfsiz); dev_dbg(hsotg->dev, "hptxfsiz=%08x\n", hptxfsiz); - if (!(gusbcfg & GUSBCFG_FORCEHOSTMODE)) { + if (hsotg->dr_mode != USB_DR_MODE_HOST) { dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG); usleep_range(100000, 150000); } -- 2.6.0.rc2.230.g3dd15c0