From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932844AbbJNP4k (ORCPT ); Wed, 14 Oct 2015 11:56:40 -0400 Received: from mail-io0-f176.google.com ([209.85.223.176]:35729 "EHLO mail-io0-f176.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932812AbbJNP4h (ORCPT ); Wed, 14 Oct 2015 11:56:37 -0400 From: Boqun Feng To: linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org Cc: Peter Zijlstra , Ingo Molnar , Benjamin Herrenschmidt , Paul Mackerras , Michael Ellerman , Thomas Gleixner , Will Deacon , "Paul E. McKenney" , Waiman Long , Davidlohr Bueso , Boqun Feng Subject: [PATCH tip/locking/core v4 0/6] atomics: powerpc: Implement relaxed/acquire/release variants of some atomics Date: Wed, 14 Oct 2015 23:55:55 +0800 Message-Id: <1444838161-17209-1-git-send-email-boqun.feng@gmail.com> X-Mailer: git-send-email 2.5.3 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi all, This is v4 of the series. Link for v1: https://lkml.org/lkml/2015/8/27/798 Link for v2: https://lkml.org/lkml/2015/9/16/527 Link for v3: https://lkml.org/lkml/2015/10/12/368 Changes since v3: * avoid to introduce smp_acquire_barrier__after_atomic() (Will Deacon) * explain a little bit why we don't implement cmpxchg_release with assembly code (Will Deacon) Relaxed/acquire/release variants of atomic operations {add,sub}_return and {cmp,}xchg are introduced by commit: "atomics: add acquire/release/relaxed variants of some atomic operations" and {inc,dec}_return has been introduced by commit: "locking/asm-generic: Add _{relaxed|acquire|release}() variants for inc/dec atomics" Both of these are in the current locking/core branch of the tip tree. By default, the generic code will implement a relaxed variant as a full ordered atomic operation and release/acquire a variant as a relaxed variant with a necessary general barrier before or after. On powerpc, which has a weak memory order model, a relaxed variant can be implemented more lightweightly than a full ordered one. Further more, release and acquire variants can be implemented with arch-specific lightweight barriers. Besides, cmpxchg, xchg and their atomic_ versions are only RELEASE+ACQUIRE rather that full barriers in current PPC implementation, which is incorrect according to memory-barriers.txt. Therefore this patchset fix the order guarantee of cmpxchg, xchg and their atomic_ versions and implements the relaxed/acquire/release variants based on powerpc memory model and specific barriers, Some trivial tests for these new variants are also included in this series, because some of these variants are not used in kernel for now, I think is a good idea to at least generate the code for these variants somewhere. The patchset consists of 6 parts: 1. Make xchg, cmpxchg and their atomic_ versions a full barrier 2. Add trivial tests for the new variants in lib/atomic64_test.c 3. Allow architectures to define their own __atomic_op_*() helpers to build other variants based on relaxed. 4. Implement atomic{,64}_{add,sub,inc,dec}_return_* variants 5. Implement xchg_* and atomic{,64}_xchg_* variants 6. Implement cmpxchg_* atomic{,64}_cmpxchg_* variants This patchset is based on current locking/core branch of the tip tree and all patches are built and boot tested for little endian pseries, and also tested by 0day. Looking forward to any suggestion, question and comment ;-) Regards, Boqun