From: Andi Kleen <andi@firstfloor.org>
To: peterz@infradead.org
Cc: linux-kernel@vger.kernel.org, Andi Kleen <ak@linux.intel.com>
Subject: [PATCH 2/4] x86, perf: Factor out BTS enable/disable functions
Date: Thu, 15 Oct 2015 16:37:58 -0700 [thread overview]
Message-ID: <1444952280-24184-3-git-send-email-andi@firstfloor.org> (raw)
In-Reply-To: <1444952280-24184-1-git-send-email-andi@firstfloor.org>
From: Andi Kleen <ak@linux.intel.com>
Move BTS enable/disable into own functions. Used by the next
patch.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
---
arch/x86/kernel/cpu/perf_event_intel.c | 43 ++++++++++++++++++++--------------
1 file changed, 26 insertions(+), 17 deletions(-)
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index 69a545e..a466055 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -1457,20 +1457,39 @@ static __initconst const u64 slm_hw_cache_event_ids
},
};
-/*
- * Use from PMIs where the LBRs are already disabled.
- */
-static void __intel_pmu_disable_all(void)
+static inline void intel_pmu_maybe_disable_bts(void)
{
struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
- wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
-
if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
intel_pmu_disable_bts();
else
intel_bts_disable_local();
+}
+
+static inline void intel_pmu_maybe_enable_bts(void)
+{
+ struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
+ if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
+ struct perf_event *event =
+ cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
+
+ if (WARN_ON_ONCE(!event))
+ return;
+
+ intel_pmu_enable_bts(event->hw.config);
+ } else
+ intel_bts_enable_local();
+}
+
+/*
+ * Use from PMIs where the LBRs are already disabled.
+ */
+static void __intel_pmu_disable_all(void)
+{
+ wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
+ intel_pmu_maybe_disable_bts();
intel_pmu_pebs_disable_all();
}
@@ -1488,17 +1507,7 @@ static void __intel_pmu_enable_all(int added, bool pmi)
intel_pmu_lbr_enable_all(pmi);
wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
-
- if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
- struct perf_event *event =
- cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
-
- if (WARN_ON_ONCE(!event))
- return;
-
- intel_pmu_enable_bts(event->hw.config);
- } else
- intel_bts_enable_local();
+ intel_pmu_maybe_enable_bts();
}
static void intel_pmu_enable_all(int added)
--
2.4.3
next prev parent reply other threads:[~2015-10-15 23:38 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-15 23:37 perf: Some improvements for Skylake perf Andi Kleen
2015-10-15 23:37 ` [PATCH 1/4] x86, perf: Use a new PMU ack sequence on Skylake Andi Kleen
2015-10-16 11:51 ` Peter Zijlstra
2015-10-16 13:35 ` Andi Kleen
2015-10-16 15:00 ` Peter Zijlstra
2015-10-16 16:14 ` Mike Galbraith
2015-10-19 7:08 ` Ingo Molnar
2015-10-15 23:37 ` Andi Kleen [this message]
2015-10-15 23:37 ` [PATCH 3/4] perf, x86: Use counter freezing with Arch Perfmon v4 Andi Kleen
2015-10-15 23:38 ` [PATCH 4/4] x86, perf: Use INST_RETIRED.PREC_DIST for cycles:pp on Skylake Andi Kleen
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