From: Mika Westerberg <mika.westerberg@linux.intel.com>
To: Linus Walleij <linus.walleij@linaro.org>
Cc: Heikki Krogerus <heikki.krogerus@linux.intel.com>,
Mika Westerberg <mika.westerberg@linux.intel.com>,
linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org
Subject: [PATCH 0/3] pinctrl: Add support for Intel Broxton SoC
Date: Wed, 21 Oct 2015 13:08:42 +0300 [thread overview]
Message-ID: <1445422125-72075-1-git-send-email-mika.westerberg@linux.intel.com> (raw)
Hi,
This series adds pinctrl/GPIO support for Intel Broxton SoC. The GPIO
hardware is based on the same design already found in Intel Skylake
(Sunrisepoint PCH).
This series adds a new driver pinctrl-broxton.c which reuses the existing
Intel pinctrl core functionality and provides Broxton specific pin
configuration.
Mika Westerberg (3):
pinctrl: intel: Add support for multiple GPIO chips sharing the interrupt
pinctrl: intel: Allow requesting pins which are in ACPI mode as GPIOs
pinctrl: intel: Add Intel Broxton pin controller support
drivers/pinctrl/intel/Kconfig | 8 +
drivers/pinctrl/intel/Makefile | 1 +
drivers/pinctrl/intel/pinctrl-broxton.c | 1065 +++++++++++++++++++++++++++++++
drivers/pinctrl/intel/pinctrl-intel.c | 68 +-
4 files changed, 1123 insertions(+), 19 deletions(-)
create mode 100644 drivers/pinctrl/intel/pinctrl-broxton.c
--
2.6.1
next reply other threads:[~2015-10-21 10:09 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-21 10:08 Mika Westerberg [this message]
2015-10-21 10:08 ` [PATCH 1/3] pinctrl: intel: Add support for multiple GPIO chips sharing the interrupt Mika Westerberg
2015-10-27 12:29 ` Linus Walleij
2015-10-21 10:08 ` [PATCH 2/3] pinctrl: intel: Allow requesting pins which are in ACPI mode as GPIOs Mika Westerberg
2015-10-27 12:31 ` Linus Walleij
2015-10-21 10:08 ` [PATCH 3/3] pinctrl: intel: Add Intel Broxton pin controller support Mika Westerberg
2015-10-27 12:33 ` Linus Walleij
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