From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754127AbbJ0HR1 (ORCPT ); Tue, 27 Oct 2015 03:17:27 -0400 Received: from szxga02-in.huawei.com ([119.145.14.65]:17957 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753872AbbJ0HRZ (ORCPT ); Tue, 27 Oct 2015 03:17:25 -0400 From: Chen Feng To: , , , , , , , , , , , , , , , , , CC: , , , Subject: [PATCH V3 RESEND 1/3] bindings for hisilicon hi6220 iommu driver Date: Tue, 27 Oct 2015 15:16:19 +0800 Message-ID: <1445930181-71565-1-git-send-email-puck.chen@hisilicon.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.184.163.62] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org docs: iommu: Documentation for iommu in hi6220 SoC. Signed-off-by: Chen Feng Signed-off-by: Yu Dongbin --- .../bindings/iommu/hisi,hi6220-iommu.txt | 56 ++++++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 Documentation/devicetree/bindings/iommu/hisi,hi6220-iommu.txt diff --git a/Documentation/devicetree/bindings/iommu/hisi,hi6220-iommu.txt b/Documentation/devicetree/bindings/iommu/hisi,hi6220-iommu.txt new file mode 100644 index 0000000..756e64f --- /dev/null +++ b/Documentation/devicetree/bindings/iommu/hisi,hi6220-iommu.txt @@ -0,0 +1,56 @@ +Hi6220 SoC SMMU Device Driver devicetree document +======================================================================= +The Architecture of SMMU on Hi6220 SoC: + + +------------------------------------------------------------------+ + | | + | +---------+ +--------+ +-------------+ +-------+ | + | | ADE | | ISP | | V/J codec | | G3D | | + | +----|----+ +---|----+ +------|------+ +---|---| | + | | | | | | + | ---------v-----------v--------------v--------------v----- | + | Media Bus | + | --------------------------------|---------------|-------- | + | | | | + | +---v---------------v--------+ | + | | SMMU | | + | +----------|---------|-------+ | + | | | | + +--------------------------------------------|---------|-----------+ + | | + +------------v---------v-----------+ + | DDRC | + +----------------------------------+ + +Note: +The media system shared the same smmu IP to access DDR memory. And all +media IP used the same page table. + +Below binding describes the system mmu for media system in hi6220 platform + +Required properties: +- compatible: should contain "hisilicon,hi6220-smmu". +- reg: A tuple of base address and size of System MMU registers. +- clocks: a list of phandle + clock-specifier pairs, one for each entry + in clock-names. +- clock-names: should contain: + * "smmu" + * "media-sc" + * "smmu-peri" +- interrupts: An interrupt specifier for interrupt signal of System MMU. +- #iommu-cells: The iommu-cells should be 0. Because no additional information + needs to be encoded in the specifier. + +Examples: + iommu@f4210000 { + compatible = "hisilicon,hi6220-smmu"; + reg = <0x0 0xf4210000 0x0 0x1000>; + interrupts = ; + clocks = <&sys_ctrl HI6220_MMU_CLK>, + <&media_ctrl HI6220_MED_MMU>, + <&sys_ctrl HI6220_MEDIA_PLL_SRC>; + clock-names = "smmu", + "media-sc", + "smmu-peri"; + #iommu-cells = <0>; + }; -- 1.9.1