From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754091AbbJ0JxV (ORCPT ); Tue, 27 Oct 2015 05:53:21 -0400 Received: from szxga01-in.huawei.com ([58.251.152.64]:65046 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753062AbbJ0JxT (ORCPT ); Tue, 27 Oct 2015 05:53:19 -0400 From: Chen Feng To: , , , , , , Subject: [PATCH V5 Base on RC7 3/3] Add reset controller for hi6220 SoC platform. Date: Tue, 27 Oct 2015 17:51:38 +0800 Message-ID: <1445939498-94147-3-git-send-email-puck.chen@hisilicon.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1445939498-94147-1-git-send-email-puck.chen@hisilicon.com> References: <1445939498-94147-1-git-send-email-puck.chen@hisilicon.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.184.163.62] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org reset: add driver for hi6220 reset controller Signed-off-by: Chen Feng --- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index 3f03380..3f055e2 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -167,5 +167,12 @@ clocks = <&ao_ctrl 36>, <&ao_ctrl 36>; clock-names = "uartclk", "apb_pclk"; }; + + reset_ctrl: reset_ctrl@f7030000 { + compatible = "hisilicon,hi6220-reset-ctl"; + reg = <0x0 0xf7030000 0x0 0x1000>; + #reset-cells = <1>; + }; + }; }; -- 1.9.1