From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753546AbbJaNQ6 (ORCPT ); Sat, 31 Oct 2015 09:16:58 -0400 Received: from mail-db3on0075.outbound.protection.outlook.com ([157.55.234.75]:43205 "EHLO emea01-db3-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753186AbbJaNQz (ORCPT ); Sat, 31 Oct 2015 09:16:55 -0400 Authentication-Results: spf=fail (sender IP is 212.179.42.66) smtp.mailfrom=ezchip.com; vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=none action=none header.from=ezchip.com; From: Noam Camus To: CC: , , , , Noam Camus Subject: [PATCH v1 00/20] eznps a new ARC platform Date: Sat, 31 Oct 2015 15:15:07 +0200 Message-ID: <1446297327-16298-1-git-send-email-noamc@ezchip.com> X-Mailer: git-send-email 1.7.1 MIME-Version: 1.0 Content-Type: text/plain X-TM-AS-Product-Ver: SMEX-11.0.0.1191-8.000.1202-21912.007 X-TM-AS-Result: No--11.966600-8.000000-31 X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-EOPAttributedMessage: 0 X-Microsoft-Exchange-Diagnostics: 1;DB3FFO11FD038;1:xs5LwsF1LmfBlNZ99HiP3idK/79M65vx3wD5f1KhKegjI13m+dmkKXMvHaLvShGpFU3jD4lALcg7shatCK3TE/yEbBsJljs7EwntjzEbRqpWUKiiCroikWYt8bE9qrsbWJU6rVMTHD2ymZkdv2MqN0rJ+2c5/Ggkmrn9/nl41QK2XdOlag3FN2ARlBqGLSWNpYpUbMCmRadklPfeauNvaAXISpbsDOFjaaB/FmgTcDiaC3yBVTxkTDa6Im2b6X8tsvqWJ5tB8OX4+qHM/WORdEyK+xTS3p6cmbeOSofHDrJf8/Evg+iUL6/48TJQ785V2we2REKYMDfgN42rbkQ1pwQi+lj0TngIwT0OtfRBmRnKkwZa6Ny2CRji9hROFXqJxpvYKzRy85Lww4279RytKA== X-Forefront-Antispam-Report: CIP:212.179.42.66;CTRY:IL;IPV:NLI;EFV:NLI;SFV:NSPM;SFS:(10009020)(6009001)(2980300002)(1109001)(1110001)(339900001)(189002)(199003)(54164003)(66654002)(85426001)(5007970100001)(49486002)(50466002)(5003940100001)(107886002)(87936001)(110136002)(105606002)(92566002)(5001970100001)(189998001)(50226001)(77096005)(36756003)(11100500001)(106466001)(6806005)(19580395003)(50986999)(19580405001)(48376002)(47776003)(4001430100002)(229853001)(2351001)(5008740100001)(33646002)(86362001)(104016004);DIR:OUT;SFP:1101;SCL:1;SRVR:AMSPR02MB181;H:ezex10.ezchip.com;FPR:;SPF:Fail;PTR:ezmail.ezchip.com;MX:1;A:1;LANG:en; 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Platform name called "eznps" for working with EZchip NPS400 Network Proccessor. NPS400 is targeted to service "fast path" network applications. NPS400 got mesh of 256 extended ARC cores (AKA CTOP), each core got 16 HW threats. This is basically SMT core where at any point of time only one HW thread is active. Each core have HW scheduler that round robin between eligible HW threads. Totaly, kernel sees 4096 CPUs which I belive is a high record. There is no cache coherency between cores so generic user applications and kernel do not use D$. Cores got special memory mappings for huge pages (8MB). Mapping is static and should provide application enough memory without any "TLB miss". This mapping is on top of TLB mapping. This is a basic set that will later be followed with additional set of patches with all advanced features. Many thanks to all people helping to make this happen. Regards, Noam Camus Noam Camus (17): Documentation: Add EZchip vendor to binding list clocksource: Add NPS400 timers driver irqchip: add nps Internal and external irqchips ARC: Set vmalloc size from configuration ARC: rwlock: disable interrupts in !LLSC variant ARC: Mark cpu online only after it has executed the per cpu init hook. ARC: mm: use generic macros _BITUL() ARC: add CONFIG_CLKSRC_OF support to time_init() ARC: [plat-eznps] Add eznps board defconfig and dts ARC: [plat-eznps] Add eznps platform ARC: [plat-eznps] Use dedicated user stack top ARC: [plat-eznps] Use dedicated bitops/atomic/cmpxchg ARC: [plat-eznps] Use dedicated SMP barriers ARC: [plat-eznps] Use dedicated identity auxiliary register. ARC: [plat-eznps] Use dedicated COMMAND_LINE_SIZE ARC: [plat-eznps] define IPI_IRQ ARC: Add eznps platform to Kconfig and Makefile Tal Zilcer (3): ARC: Use res_service as entry point for secondaries ARC: [plat-eznps] Use dedicated cpu_relax() ARC: [plat-eznps] replace sync with proper cpu barrier Documentation/devicetree/bindings/arc/eznps.txt | 7 + .../interrupt-controller/ezchip,nps400-ic.txt | 17 ++ .../bindings/timer/ezchip,nps400-timer.txt | 11 + .../devicetree/bindings/vendor-prefixes.txt | 1 + MAINTAINERS | 6 + arch/arc/Kconfig | 9 + arch/arc/Makefile | 9 + arch/arc/boot/dts/eznps.dts | 76 ++++++ arch/arc/configs/nps_defconfig | 85 +++++++ arch/arc/include/asm/atomic.h | 69 +++++ arch/arc/include/asm/barrier.h | 8 + arch/arc/include/asm/bitops.h | 49 ++++ arch/arc/include/asm/cmpxchg.h | 49 ++++ arch/arc/include/asm/entry-compact.h | 8 + arch/arc/include/asm/irq.h | 4 + arch/arc/include/asm/pgtable.h | 2 +- arch/arc/include/asm/processor.h | 32 ++- arch/arc/include/asm/setup.h | 4 + arch/arc/include/asm/smp.h | 2 +- arch/arc/include/asm/spinlock.h | 14 + arch/arc/kernel/ctx_sw.c | 20 ++ arch/arc/kernel/smp.c | 9 +- arch/arc/kernel/time.c | 4 + arch/arc/mm/tlb.c | 12 + arch/arc/plat-eznps/Kconfig | 34 +++ arch/arc/plat-eznps/Makefile | 7 + arch/arc/plat-eznps/entry.S | 76 ++++++ arch/arc/plat-eznps/include/plat/ctop.h | 265 ++++++++++++++++++++ arch/arc/plat-eznps/include/plat/mtm.h | 60 +++++ arch/arc/plat-eznps/include/plat/smp.h | 27 ++ arch/arc/plat-eznps/mtm.c | 152 +++++++++++ arch/arc/plat-eznps/platform.c | 40 +++ arch/arc/plat-eznps/smp.c | 160 ++++++++++++ drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-nps.c | 103 ++++++++ drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-eznps.c | 222 ++++++++++++++++ 37 files changed, 1644 insertions(+), 11 deletions(-) create mode 100644 Documentation/devicetree/bindings/arc/eznps.txt create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt create mode 100644 Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt create mode 100644 arch/arc/boot/dts/eznps.dts create mode 100644 arch/arc/configs/nps_defconfig create mode 100644 arch/arc/plat-eznps/Kconfig create mode 100644 arch/arc/plat-eznps/Makefile create mode 100644 arch/arc/plat-eznps/entry.S create mode 100644 arch/arc/plat-eznps/include/plat/ctop.h create mode 100644 arch/arc/plat-eznps/include/plat/mtm.h create mode 100644 arch/arc/plat-eznps/include/plat/smp.h create mode 100644 arch/arc/plat-eznps/mtm.c create mode 100644 arch/arc/plat-eznps/platform.c create mode 100644 arch/arc/plat-eznps/smp.c create mode 100644 drivers/clocksource/timer-nps.c create mode 100644 drivers/irqchip/irq-eznps.c