From: Noam Camus <noamc@ezchip.com>
To: <linux-snps-arc@lists.infradead.org>
Cc: <linux-kernel@vger.kernel.org>, <talz@ezchip.com>,
<gilf@ezchip.com>, <cmetcalf@ezchip.com>,
Noam Camus <noamc@ezchip.com>
Subject: [PATCH v2 13/19] ARC: [plat-eznps] Use dedicated atomic/bitops/cmpxchg
Date: Sat, 7 Nov 2015 12:52:31 +0200 [thread overview]
Message-ID: <1446893557-29748-14-git-send-email-noamc@ezchip.com> (raw)
In-Reply-To: <1446297327-16298-1-git-send-email-noamc@ezchip.com>
From: Noam Camus <noamc@ezchip.com>
We need our own implementaions since we lack LLSC support.
Our extended ISA provided with optimized solution for all 32bit
operations we see in these three headers.
Signed-off-by: Noam Camus <noamc@ezchip.com>
---
arch/arc/include/asm/atomic.h | 79 +++++++++++++++++++++++++++++++++++-
arch/arc/include/asm/bitops.h | 54 +++++++++++++++++++++++++
arch/arc/include/asm/cmpxchg.h | 87 +++++++++++++++++++++++++++++++++-------
3 files changed, 202 insertions(+), 18 deletions(-)
diff --git a/arch/arc/include/asm/atomic.h b/arch/arc/include/asm/atomic.h
index c3ecda0..1b2e78a 100644
--- a/arch/arc/include/asm/atomic.h
+++ b/arch/arc/include/asm/atomic.h
@@ -17,6 +17,7 @@
#include <asm/barrier.h>
#include <asm/smp.h>
+#ifndef CONFIG_ARC_PLAT_EZNPS
#define atomic_read(v) ((v)->counter)
#ifdef CONFIG_ARC_HAS_LLSC
@@ -180,12 +181,84 @@ ATOMIC_OP(andnot, &= ~, bic)
ATOMIC_OP(or, |=, or)
ATOMIC_OP(xor, ^=, xor)
-#undef ATOMIC_OPS
-#undef ATOMIC_OP_RETURN
-#undef ATOMIC_OP
#undef SCOND_FAIL_RETRY_VAR_DEF
#undef SCOND_FAIL_RETRY_ASM
#undef SCOND_FAIL_RETRY_VARS
+#else /* CONFIG_ARC_PLAT_EZNPS */
+static inline int atomic_read(const atomic_t *v)
+{
+ int temp;
+
+ __asm__ __volatile__(
+ " ld.di %0, [%1]"
+ : "=r"(temp)
+ : "r"(&v->counter)
+ : "memory");
+ return temp;
+}
+
+static inline void atomic_set(atomic_t *v, int i)
+{
+ __asm__ __volatile__(
+ " st.di %0,[%1]"
+ :
+ : "r"(i), "r"(&v->counter)
+ : "memory");
+}
+
+#define ATOMIC_OP(op, c_op, asm_op) \
+static inline void atomic_##op(int i, atomic_t *v) \
+{ \
+ __asm__ __volatile__( \
+ " mov r2, %0\n" \
+ " mov r3, %1\n" \
+ " .word %2\n" \
+ : \
+ : "r"(i), "r"(&v->counter), "i"(asm_op) \
+ : "r2", "r3", "memory"); \
+} \
+
+#define ATOMIC_OP_RETURN(op, c_op, asm_op) \
+static inline int atomic_##op##_return(int i, atomic_t *v) \
+{ \
+ unsigned int temp = i; \
+ \
+ /* Explicit full memory barrier needed before/after */ \
+ smp_mb(); \
+ \
+ __asm__ __volatile__( \
+ " mov r2, %0\n" \
+ " mov r3, %1\n" \
+ " .word %2\n" \
+ " mov %0, r2" \
+ : "+r"(temp) \
+ : "r"(&v->counter), "i"(asm_op) \
+ : "r2", "r3", "memory"); \
+ \
+ smp_mb(); \
+ \
+ temp c_op i; \
+ \
+ return temp; \
+}
+
+#define ATOMIC_OPS(op, c_op, asm_op) \
+ ATOMIC_OP(op, c_op, asm_op) \
+ ATOMIC_OP_RETURN(op, c_op, asm_op)
+
+ATOMIC_OPS(add, +=, CTOP_INST_AADD_DI_R2_R2_R3)
+#define atomic_sub(i, v) atomic_add(-(i), (v))
+#define atomic_sub_return(i, v) atomic_add_return(-(i), (v))
+
+ATOMIC_OP(and, &=, CTOP_INST_AAND_DI_R2_R2_R3)
+#define atomic_andnot(mask, v) atomic_and(~(mask), (v))
+ATOMIC_OP(or, |=, CTOP_INST_AOR_DI_R2_R2_R3)
+ATOMIC_OP(xor, ^=, CTOP_INST_AXOR_DI_R2_R2_R3)
+#endif /* CONFIG_ARC_PLAT_EZNPS */
+
+#undef ATOMIC_OPS
+#undef ATOMIC_OP_RETURN
+#undef ATOMIC_OP
/**
* __atomic_add_unless - add unless the number is a given value
diff --git a/arch/arc/include/asm/bitops.h b/arch/arc/include/asm/bitops.h
index 57c1f33..5a29185 100644
--- a/arch/arc/include/asm/bitops.h
+++ b/arch/arc/include/asm/bitops.h
@@ -22,6 +22,7 @@
#include <asm/smp.h>
#endif
+#ifndef CONFIG_ARC_PLAT_EZNPS
#if defined(CONFIG_ARC_HAS_LLSC)
/*
@@ -155,6 +156,53 @@ static inline int test_and_##op##_bit(unsigned long nr, volatile unsigned long *
}
#endif /* CONFIG_ARC_HAS_LLSC */
+#else /* CONFIG_ARC_PLAT_EZNPS */
+#define BIT_OP(op, c_op, asm_op) \
+static inline void op##_bit(unsigned long nr, volatile unsigned long *m)\
+{ \
+ m += nr >> 5; \
+ \
+ nr = (1UL << (nr & 0x1f)); \
+ if (asm_op == CTOP_INST_AAND_DI_R2_R2_R3) \
+ nr = ~nr; \
+ \
+ __asm__ __volatile__( \
+ " mov r2, %0\n" \
+ " mov r3, %1\n" \
+ " .word %2\n" \
+ : \
+ : "r"(nr), "r"(m), "i"(asm_op) \
+ : "r2", "r3", "memory"); \
+}
+
+#define TEST_N_BIT_OP(op, c_op, asm_op) \
+static inline int test_and_##op##_bit(unsigned long nr, volatile unsigned long *m)\
+{ \
+ unsigned long old; \
+ \
+ m += nr >> 5; \
+ \
+ nr = old = (1UL << (nr & 0x1f)); \
+ if (asm_op == CTOP_INST_AAND_DI_R2_R2_R3) \
+ old = ~old; \
+ \
+ /* Explicit full memory barrier needed before/after */ \
+ smp_mb(); \
+ \
+ __asm__ __volatile__( \
+ " mov r2, %0\n" \
+ " mov r3, %1\n" \
+ " .word %2\n" \
+ " mov %0, r2" \
+ : "+r"(old) \
+ : "r"(m), "i"(asm_op) \
+ : "r2", "r3", "memory"); \
+ \
+ smp_mb(); \
+ \
+ return (old & nr) != 0; \
+}
+#endif /* CONFIG_ARC_PLAT_EZNPS */
/***************************************
* Non atomic variants
@@ -196,9 +244,15 @@ static inline int __test_and_##op##_bit(unsigned long nr, volatile unsigned long
/* __test_and_set_bit(), __test_and_clear_bit(), __test_and_change_bit() */\
__TEST_N_BIT_OP(op, c_op, asm_op)
+#ifndef CONFIG_ARC_PLAT_EZNPS
BIT_OPS(set, |, bset)
BIT_OPS(clear, & ~, bclr)
BIT_OPS(change, ^, bxor)
+#else
+BIT_OPS(set, |, CTOP_INST_AOR_DI_R2_R2_R3)
+BIT_OPS(clear, & ~, CTOP_INST_AAND_DI_R2_R2_R3)
+BIT_OPS(change, ^, CTOP_INST_AXOR_DI_R2_R2_R3)
+#endif
/*
* This routine doesn't need to be atomic.
diff --git a/arch/arc/include/asm/cmpxchg.h b/arch/arc/include/asm/cmpxchg.h
index af7a2db..6d320d3 100644
--- a/arch/arc/include/asm/cmpxchg.h
+++ b/arch/arc/include/asm/cmpxchg.h
@@ -14,6 +14,7 @@
#include <asm/barrier.h>
#include <asm/smp.h>
+#ifndef CONFIG_ARC_PLAT_EZNPS
#ifdef CONFIG_ARC_HAS_LLSC
static inline unsigned long
@@ -66,21 +67,6 @@ __cmpxchg(volatile void *ptr, unsigned long expected, unsigned long new)
#endif /* CONFIG_ARC_HAS_LLSC */
-#define cmpxchg(ptr, o, n) ((typeof(*(ptr)))__cmpxchg((ptr), \
- (unsigned long)(o), (unsigned long)(n)))
-
-/*
- * Since not supported natively, ARC cmpxchg() uses atomic_ops_lock (UP/SMP)
- * just to gaurantee semantics.
- * atomic_cmpxchg() needs to use the same locks as it's other atomic siblings
- * which also happens to be atomic_ops_lock.
- *
- * Thus despite semantically being different, implementation of atomic_cmpxchg()
- * is same as cmpxchg().
- */
-#define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n)))
-
-
/*
* xchg (reg with memory) based on "Native atomic" EX insn
*/
@@ -143,6 +129,63 @@ static inline unsigned long __xchg(unsigned long val, volatile void *ptr,
#endif
+#else /* CONFIG_ARC_PLAT_EZNPS */
+static inline unsigned long
+__cmpxchg(volatile void *ptr, unsigned long expected, unsigned long new)
+{
+ /*
+ * Explicit full memory barrier needed before/after
+ */
+ smp_mb();
+
+ write_aux_reg(CTOP_AUX_GPA1, expected);
+
+ __asm__ __volatile__(
+ " mov r2, %0\n"
+ " mov r3, %1\n"
+ " .word %2\n"
+ " mov %0, r2"
+ : "+r"(new)
+ : "r"(ptr), "i"(CTOP_INST_EXC_DI_R2_R2_R3)
+ : "r2", "r3", "memory");
+
+ smp_mb();
+
+ return new;
+}
+
+static inline unsigned long __xchg(unsigned long val, volatile void *ptr,
+ int size)
+{
+ extern unsigned long __xchg_bad_pointer(void);
+
+ switch (size) {
+ case 4:
+ /*
+ * Explicit full memory barrier needed before/after
+ */
+ smp_mb();
+
+ __asm__ __volatile__(
+ " mov r2, %0\n"
+ " mov r3, %1\n"
+ " .word %2\n"
+ " mov %0, r2\n"
+ : "+r"(val)
+ : "r"(ptr), "i"(CTOP_INST_XEX_DI_R2_R2_R3)
+ : "r2", "r3", "memory");
+
+ smp_mb();
+
+ return val;
+ }
+ return __xchg_bad_pointer();
+}
+
+#define xchg(ptr, with) ((typeof(*(ptr)))__xchg((unsigned long)(with), (ptr), \
+ sizeof(*(ptr))))
+#endif /* CONFIG_ARC_PLAT_EZNPS */
+
/*
* "atomic" variant of xchg()
* REQ: It needs to follow the same serialization rules as other atomic_xxx()
@@ -158,4 +201,18 @@ static inline unsigned long __xchg(unsigned long val, volatile void *ptr,
*/
#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
+#define cmpxchg(ptr, o, n) ((typeof(*(ptr)))__cmpxchg((ptr), \
+ (unsigned long)(o), (unsigned long)(n)))
+
+/*
+ * Since not supported natively, ARC cmpxchg() uses atomic_ops_lock (UP/SMP)
+ * just to gaurantee semantics.
+ * atomic_cmpxchg() needs to use the same locks as it's other atomic siblings
+ * which also happens to be atomic_ops_lock.
+ *
+ * Thus despite semantically being different, implementation of atomic_cmpxchg()
+ * is same as cmpxchg().
+ */
+#define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n)))
+
#endif
--
1.7.1
next prev parent reply other threads:[~2015-11-07 10:59 UTC|newest]
Thread overview: 95+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-31 13:15 [PATCH v1 00/20] eznps a new ARC platform Noam Camus
2015-10-31 13:15 ` [PATCH v1 01/20] Documentation: Add EZchip vendor to binding list Noam Camus
2015-10-31 13:15 ` [PATCH v1 02/20] clocksource: Add NPS400 timers driver Noam Camus
2015-11-01 20:44 ` Daniel Lezcano
2015-11-02 7:57 ` Noam Camus
2015-11-02 11:03 ` Vineet Gupta
2015-11-03 15:18 ` Noam Camus
2015-10-31 13:15 ` [PATCH v1 03/20] irqchip: add nps Internal and external irqchips Noam Camus
2015-10-31 13:15 ` [PATCH v1 04/20] ARC: Set vmalloc size from configuration Noam Camus
2015-10-31 13:15 ` [PATCH v1 05/20] ARC: rwlock: disable interrupts in !LLSC variant Noam Camus
2015-11-02 9:16 ` Peter Zijlstra
2015-11-02 9:42 ` Vineet Gupta
2015-11-02 10:03 ` Peter Zijlstra
2015-10-31 13:15 ` [PATCH v1 06/20] ARC: Mark cpu online only after it has executed the per cpu init hook Noam Camus
2015-10-31 13:15 ` [PATCH v1 07/20] ARC: mm: use generic macros _BITUL() Noam Camus
2015-11-02 6:23 ` Vineet Gupta
2015-11-02 6:27 ` Noam Camus
2015-10-31 13:15 ` [PATCH v1 08/20] ARC: Use res_service as entry point for secondaries Noam Camus
2015-11-02 6:38 ` Vineet Gupta
2015-11-02 8:05 ` Noam Camus
2015-10-31 13:15 ` [PATCH v1 09/20] ARC: add CONFIG_CLKSRC_OF support to time_init() Noam Camus
2015-11-02 6:32 ` Vineet Gupta
2015-10-31 13:15 ` [PATCH v1 10/20] ARC: [plat-eznps] Add eznps board defconfig and dts Noam Camus
2015-10-31 13:15 ` [PATCH v1 11/20] ARC: [plat-eznps] Add eznps platform Noam Camus
2015-11-02 10:56 ` Vineet Gupta
2015-11-03 15:59 ` Noam Camus
2015-11-04 12:38 ` Noam Camus
2015-11-05 5:09 ` Vineet Gupta
2015-10-31 13:15 ` [PATCH v1 12/20] ARC: [plat-eznps] Use dedicated user stack top Noam Camus
2015-10-31 13:15 ` [PATCH v1 13/20] ARC: [plat-eznps] Use dedicated bitops/atomic/cmpxchg Noam Camus
2015-11-02 11:56 ` Vineet Gupta
2015-10-31 13:15 ` [PATCH v1 14/20] ARC: [plat-eznps] Use dedicated SMP barriers Noam Camus
2015-11-02 8:02 ` Vineet Gupta
2015-11-02 13:08 ` Noam Camus
2015-10-31 13:15 ` [PATCH v1 15/20] ARC: [plat-eznps] Use dedicated identity auxiliary register Noam Camus
2015-10-31 13:15 ` [PATCH v1 16/20] ARC: [plat-eznps] Use dedicated cpu_relax() Noam Camus
2015-11-02 7:54 ` Vineet Gupta
2015-11-02 9:21 ` Peter Zijlstra
2015-11-03 14:02 ` Noam Camus
2015-10-31 13:15 ` [PATCH v1 17/20] ARC: [plat-eznps] Use dedicated COMMAND_LINE_SIZE Noam Camus
2015-10-31 13:15 ` [PATCH v1 18/20] ARC: [plat-eznps] define IPI_IRQ Noam Camus
2015-11-02 7:52 ` Vineet Gupta
2015-11-02 12:16 ` Noam Camus
2015-10-31 13:15 ` [PATCH v1 19/20] ARC: [plat-eznps] replace sync with proper cpu barrier Noam Camus
2015-11-02 7:48 ` Vineet Gupta
2015-11-02 9:26 ` Peter Zijlstra
2015-11-17 13:48 ` [PATCH] ARC: remove SYNC from __switch_to() Vineet Gupta
2015-10-31 13:15 ` [PATCH v1 20/20] ARC: Add eznps platform to Kconfig and Makefile Noam Camus
2015-11-02 11:06 ` Vineet Gupta
2015-11-03 15:32 ` Noam Camus
2015-11-04 15:35 ` [PATCH v1 00/20] eznps a new ARC platform Vineet Gupta
2015-11-04 15:53 ` Noam Camus
2015-11-04 17:42 ` Vineet Gupta
2015-11-07 10:52 ` [PATCH v2 00/19] " Noam Camus
2015-11-07 10:52 ` [PATCH v2 01/19] Documentation: Add EZchip vendor to binding list Noam Camus
2015-11-07 10:52 ` [PATCH v2 02/19] ARC: [plat-eznps] define IPI_IRQ Noam Camus
2015-11-07 10:52 ` [PATCH v2 03/19] clocksource: Add NPS400 timers driver Noam Camus
2015-11-07 11:26 ` Thomas Gleixner
2015-11-20 11:59 ` Noam Camus
2015-11-07 10:52 ` [PATCH v2 04/19] irqchip: add nps Internal and external irqchips Noam Camus
2015-11-07 11:38 ` Thomas Gleixner
2015-11-07 20:52 ` Noam Camus
2015-11-07 23:52 ` Thomas Gleixner
2015-11-07 10:52 ` [PATCH v2 05/19] ARC: Set vmalloc size from configuration Noam Camus
2015-11-07 10:52 ` [PATCH v2 06/19] ARC: rwlock: disable interrupts in !LLSC variant Noam Camus
2015-11-07 10:52 ` [PATCH v2 07/19] ARC: rename smp operation init_irq_cpu() to init_per_cpu() Noam Camus
2015-11-17 11:15 ` Vineet Gupta
2015-11-17 11:38 ` Noam Camus
2015-11-17 11:42 ` Vineet Gupta
2015-11-07 10:52 ` [PATCH v2 08/19] ARC: Mark secondary cpu online only after all HW setup is done Noam Camus
2015-11-17 11:17 ` Vineet Gupta
2015-11-07 10:52 ` [PATCH v2 09/19] ARC: add CONFIG_CLKSRC_OF support to time_init() Noam Camus
2015-11-07 10:52 ` [PATCH v2 10/19] ARC: [plat-eznps] Add eznps board defconfig and dts Noam Camus
2015-11-07 10:52 ` [PATCH v2 11/19] ARC: [plat-eznps] Add eznps platform Noam Camus
2015-11-07 10:52 ` [PATCH v2 12/19] ARC: [plat-eznps] Use dedicated user stack top Noam Camus
2015-11-07 10:52 ` Noam Camus [this message]
2015-11-07 10:52 ` [PATCH v2 14/19] ARC: [plat-eznps] Use dedicated SMP barriers Noam Camus
2015-11-07 10:52 ` [PATCH v2 15/19] ARC: [plat-eznps] Use dedicated identity auxiliary register Noam Camus
2015-11-07 10:52 ` [PATCH v2 16/19] ARC: [plat-eznps] Use dedicated cpu_relax() Noam Camus
2015-11-09 10:05 ` Peter Zijlstra
2015-11-09 10:22 ` Vineet Gupta
2015-11-09 10:45 ` Peter Zijlstra
2015-11-09 12:27 ` Vineet Gupta
2015-11-09 12:51 ` Peter Zijlstra
2015-11-07 10:52 ` [PATCH v2 17/19] ARC: [plat-eznps] Use dedicated COMMAND_LINE_SIZE Noam Camus
2015-11-07 10:52 ` [PATCH v2 18/19] ARC: [plat-eznps] replace sync with proper cpu barrier Noam Camus
2015-11-17 11:12 ` Vineet Gupta
2015-11-17 11:23 ` Peter Zijlstra
2015-11-17 11:37 ` Vineet Gupta
2015-11-17 12:22 ` Peter Zijlstra
2015-11-17 12:37 ` Vineet Gupta
2015-11-17 12:44 ` Peter Zijlstra
2015-11-17 13:32 ` Vineet Gupta
2015-11-17 13:59 ` Peter Zijlstra
2015-11-07 10:52 ` [PATCH v2 19/19] ARC: Add eznps platform to Kconfig and Makefile Noam Camus
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1446893557-29748-14-git-send-email-noamc@ezchip.com \
--to=noamc@ezchip.com \
--cc=cmetcalf@ezchip.com \
--cc=gilf@ezchip.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-snps-arc@lists.infradead.org \
--cc=talz@ezchip.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).