From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752867AbbKGKzK (ORCPT ); Sat, 7 Nov 2015 05:55:10 -0500 Received: from mail-db3on0081.outbound.protection.outlook.com ([157.55.234.81]:63040 "EHLO emea01-db3-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752625AbbKGKzH (ORCPT ); Sat, 7 Nov 2015 05:55:07 -0500 Authentication-Results: spf=fail (sender IP is 212.179.42.66) smtp.mailfrom=ezchip.com; kernel.org; dkim=none (message not signed) header.d=none;kernel.org; dmarc=none action=none header.from=ezchip.com; From: Noam Camus To: CC: , , , , Noam Camus , Daniel Lezcano , Rob Herring , "Thomas Gleixner" , John Stultz Subject: [PATCH v2 03/19] clocksource: Add NPS400 timers driver Date: Sat, 7 Nov 2015 12:52:21 +0200 Message-ID: <1446893557-29748-4-git-send-email-noamc@ezchip.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1446297327-16298-1-git-send-email-noamc@ezchip.com> References: <1446297327-16298-1-git-send-email-noamc@ezchip.com> MIME-Version: 1.0 Content-Type: text/plain X-TM-AS-Product-Ver: SMEX-11.0.0.1191-8.000.1202-21926.006 X-TM-AS-Result: No--20.492500-8.000000-31 X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-EOPAttributedMessage: 0 X-Microsoft-Exchange-Diagnostics: 1;AM1FFO11OLC008;1:YTQkLIz8r8C8ayPgkYq2dJgh3pipPJ6q6Tj5DvkPWqVKqJIe0fxndEaFEVCUEPAYK1VUfaP3DpLev6OoG9z89WbxwFq1Hm5V050NTOIvL+IemsX2s9r4c2YUxLlueOm2cBiiVtwinAO7dtIiUPl1w1gC3m55Zx5JqzUzHb2nYsjwP5H18a/rfmYyeHqPG3demofo2fKjvRnWB8Bdsg8O3ahClhtboOdGZl/0tE4rnUNokZpXFRgf3NG4n8KBiIbmuO4tbjpFKpoCDfe34LG4A5fnR3fQTl0OdxVrz3V1Icdb+wq7cFaC9+n0U/9oVWZ7EE1JR7TClkcMdjyUcjEXC00/I3+ayevqVSLDWuaofZ2mwkucBMO1aGxkWJBj7Zi6lXXT7i8wA3sAy60qUiZmFQ== X-Forefront-Antispam-Report: CIP:212.179.42.66;CTRY:IL;IPV:NLI;EFV:NLI;SFV:NSPM;SFS:(10009020)(6009001)(2980300002)(1110001)(1109001)(339900001)(189002)(199003)(76176999)(229853001)(50986999)(33646002)(19580405001)(105606002)(36756003)(19580395003)(106466001)(50226001)(2351001)(77096005)(5001970100001)(5007970100001)(49486002)(48376002)(6806005)(104016004)(86362001)(87936001)(2950100001)(47776003)(85426001)(5008740100001)(92566002)(50466002)(110136002)(11100500001)(5003940100001)(189998001)(2004002);DIR:OUT;SFP:1101;SCL:1;SRVR:DB4PR02MB189;H:ezex10.ezchip.com;FPR:;SPF:Fail;PTR:ezmail.ezchip.com;MX:1;A:1;LANG:en; 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Each cluster of cores view it through dedicated address. This is used for SMP system where all CPUs synced by same clock source. Signed-off-by: Noam Camus Cc: Daniel Lezcano Cc: Rob Herring Cc: Thomas Gleixner Cc: John Stultz Acked-by: Vineet Gupta --- .../bindings/timer/ezchip,nps400-timer.txt | 11 +++ drivers/clocksource/Kconfig | 7 ++ drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-nps.c | 85 ++++++++++++++++++++ 4 files changed, 104 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt create mode 100644 drivers/clocksource/timer-nps.c diff --git a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt new file mode 100644 index 0000000..c5102c2 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt @@ -0,0 +1,11 @@ +NPS Network Processor + +Required properties: + +- compatible : should be "ezchip,nps400-timer" + +Example: + +timer { + compatible = "ezchip,nps400-timer"; +}; diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index a7726db..8437113 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -115,6 +115,13 @@ config CLKSRC_PISTACHIO bool select CLKSRC_OF +config CLKSRC_NPS + bool "NPS400 clocksource driver" if COMPILE_TEST + select CLKSRC_OF + help + NPS400 clocksource support. + Got 64 bit counter with update rate up to 1000MHz. + config CLKSRC_STM32 bool "Clocksource for STM32 SoCs" if !ARCH_STM32 depends on OF && ARM && (ARCH_STM32 || COMPILE_TEST) diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index 5c00863..28c17dc 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -45,6 +45,7 @@ obj-$(CONFIG_VF_PIT_TIMER) += vf_pit_timer.o obj-$(CONFIG_CLKSRC_QCOM) += qcom-timer.o obj-$(CONFIG_MTK_TIMER) += mtk_timer.o obj-$(CONFIG_CLKSRC_PISTACHIO) += time-pistachio.o +obj-$(CONFIG_ARC_PLAT_EZNPS) += timer-nps.o obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o diff --git a/drivers/clocksource/timer-nps.c b/drivers/clocksource/timer-nps.c new file mode 100644 index 0000000..7abde9e --- /dev/null +++ b/drivers/clocksource/timer-nps.c @@ -0,0 +1,85 @@ +/* + * Copyright(c) 2015 EZchip Technologies. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in + * the file called "COPYING". + */ + +#include +#include +#include +#include + +#define NPS_MSU_TICK_LOW 0xC8 +#define NPS_CLUSTER_OFFSET 8 +#define NPS_CLUSTER_NUM 16 + +static void *nps_msu_reg_low_addr[NPS_CLUSTER_NUM] __read_mostly; + +/* + * To get the value from the Global Timer Counter register proceed as follows: + * 1. Read the upper 32-bit timer counter register + * 2. Read the lower 32-bit timer counter register + * 3. Read the upper 32-bit timer counter register again. If the value is + * different to the 32-bit upper value read previously, go back to step 2. + * Otherwise the 64-bit timer counter value is correct. + */ +static cycle_t nps_clksrc_read(struct clocksource *clksrc) +{ + u64 counter; + u32 lower, upper, old_upper; + void *lower_p, *upper_p; + int cluster = (smp_processor_id() >> NPS_CLUSTER_OFFSET); + + lower_p = nps_msu_reg_low_addr[cluster]; + upper_p = lower_p + 4; + + upper = ioread32be(upper_p); + do { + old_upper = upper; + lower = ioread32be(lower_p); + upper = ioread32be(upper_p); + } while (upper != old_upper); + + counter = (upper << 32) | lower; + return (cycle_t)counter; +} + +static struct clocksource nps_counter = { + .name = "EZnps-tick", + .rating = 301, + .read = nps_clksrc_read, + .mask = CLOCKSOURCE_MASK(64), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +static void __init nps_setup_clocksource(struct device_node *node) +{ + struct clocksource *clksrc = &nps_counter; + unsigned long rate, dt_root; + int ret, cluster; + + for (cluster = 0; cluster < NPS_CLUSTER_NUM; cluster++) + nps_msu_reg_low_addr[cluster] = + nps_host_reg((cluster << NPS_CLUSTER_OFFSET), + NPS_MSU_BLKID, NPS_MSU_TICK_LOW); + + dt_root = of_get_flat_dt_root(); + rate = (u32)of_get_flat_dt_prop(dt_root, "clock-frequency", NULL); + + ret = clocksource_register_hz(clksrc, rate); + if (ret) + pr_err("Couldn't register clock source.\n"); +} + +CLOCKSOURCE_OF_DECLARE(nps_400, "nps,400-timer", + nps_setup_clocksource); -- 1.7.1