From: Yakir Yang <ykk@rock-chips.com>
To: Inki Dae <inki.dae@samsung.com>,
Mark Yao <mark.yao@rock-chips.com>,
Jingoo Han <jingoohan1@gmail.com>,
Heiko Stuebner <heiko@sntech.de>
Cc: Thierry Reding <treding@nvidia.com>,
Krzysztof Kozlowski <k.kozlowski@samsung.com>,
Rob Herring <robh+dt@kernel.org>,
Andrzej Hajda <a.hajda@samsung.com>,
Joonyoung Shim <jy0922.shim@samsung.com>,
Seung-Woo Kim <sw0312.kim@samsung.com>,
Kyungmin Park <kyungmin.park@samsung.com>,
Russell King <linux@arm.linux.org.uk>,
emil.l.velikov@gmail.com,
Gustavo Padovan <gustavo.padovan@collabora.co.uk>,
Kishon Vijay Abraham I <kishon@ti.com>,
ajaynumb@gmail.com, javier@osg.samsung.com,
Andy Yan <andy.yan@rock-chips.com>,
Yakir Yang <ykk@rock-chips.com>,
dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org,
linux-rockchip@lists.infradead.org,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v10 03/17] drm: bridge: analogix/dp: remove duplicate configuration of link rate and link count
Date: Mon, 7 Dec 2015 14:38:44 +0800 [thread overview]
Message-ID: <1449470324-30975-1-git-send-email-ykk@rock-chips.com> (raw)
In-Reply-To: <1449470239-30667-1-git-send-email-ykk@rock-chips.com>
link_rate and lane_count already configured in analogix_dp_set_link_train(),
so we don't need to config those repeatly after training finished, just
remove them out.
Beside Display Port 1.2 already support 5.4Gbps link rate, the maximum sets
would change from {1.62Gbps, 2.7Gbps} to {1.62Gbps, 2.7Gbps, 5.4Gbps}.
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
---
Changes in v10: None
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4:
- Update commit message more readable. (Jingoo)
- Adjust the order from 05 to 04
Changes in v3:
- The link_rate and lane_count shouldn't config to the DT property value
directly, but we can take those as hardware limite. For example, RK3288
only support 4 physical lanes of 2.7/1.62 Gbps/lane, so DT property would
like "link-rate = 0x0a" "lane-count = 4". (Thierry)
Changes in v2: None
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 8 ++++----
drivers/gpu/drm/bridge/analogix/analogix_dp_core.h | 5 +++--
2 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 039aaab..1f66deb 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -624,6 +624,8 @@ static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
/*
* For DP rev.1.1, Maximum link rate of Main Link lanes
* 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
+ * For DP rev.1.2, Maximum link rate of Main Link lanes
+ * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps
*/
analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data);
*bandwidth = data;
@@ -657,7 +659,8 @@ static void analogix_dp_init_training(struct analogix_dp_device *dp,
analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
- (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
+ (dp->link_train.link_rate != LINK_RATE_2_70GBPS) &&
+ (dp->link_train.link_rate != LINK_RATE_5_40GBPS)) {
dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
dp->link_train.link_rate);
dp->link_train.link_rate = LINK_RATE_1_62GBPS;
@@ -898,9 +901,6 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
analogix_dp_enable_rx_to_enhanced_mode(dp, 1);
analogix_dp_enable_enhanced_mode(dp, 1);
- analogix_dp_set_lane_count(dp, dp->video_info->lane_count);
- analogix_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
-
analogix_dp_init_video(dp);
ret = analogix_dp_config_video(dp);
if (ret)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index 14d20be..9a90a18 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -21,8 +21,9 @@
#define MAX_EQ_LOOP 5
enum link_rate_type {
- LINK_RATE_1_62GBPS = 0x06,
- LINK_RATE_2_70GBPS = 0x0a
+ LINK_RATE_1_62GBPS = DP_LINK_BW_1_62,
+ LINK_RATE_2_70GBPS = DP_LINK_BW_2_7,
+ LINK_RATE_5_40GBPS = DP_LINK_BW_5_4,
};
enum link_lane_count_type {
--
1.9.1
next prev parent reply other threads:[~2015-12-07 6:43 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-12-07 6:37 [PATCH v10 0/17] Add Analogix Core Display Port Driver Yakir Yang
2015-12-07 6:38 ` [PATCH v10 01/17] drm: bridge: analogix/dp: split exynos dp driver to bridge directory Yakir Yang
2015-12-07 7:37 ` Yakir Yang
2015-12-07 6:38 ` [PATCH v10 02/17] drm: bridge: analogix/dp: fix some obvious code style Yakir Yang
2015-12-07 6:38 ` Yakir Yang [this message]
2015-12-07 6:38 ` [PATCH v10 04/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range Yakir Yang
2015-12-07 6:39 ` [PATCH v10 05/17] dt-bindings: add document for analogix display port driver Yakir Yang
2015-12-08 15:01 ` Rob Herring
2015-12-09 1:02 ` Yakir Yang
2015-12-07 6:39 ` [PATCH v10 06/17] ARM: dts: exynos/dp: remove some properties that deprecated by analogix_dp driver Yakir Yang
2015-12-07 6:39 ` [PATCH v10 07/17] drm: rockchip: dp: add rockchip platform dp driver Yakir Yang
2015-12-07 6:39 ` [PATCH v10 08/17] dt-bindings: add document for rockchip variant of analogix_dp Yakir Yang
2015-12-08 15:03 ` Rob Herring
2015-12-09 1:05 ` Yakir Yang
2015-12-07 6:39 ` [PATCH v10 09/17] phy: Add driver for rockchip Display Port PHY Yakir Yang
2015-12-07 6:39 ` [PATCH v10 10/17] dt-bindings: add document for rockchip dp phy Yakir Yang
2015-12-08 15:06 ` Rob Herring
2015-12-09 1:16 ` Yakir Yang
2015-12-07 6:40 ` [PATCH v10 11/17] drm: rockchip: vop: add bpc and color mode setting Yakir Yang
2015-12-07 6:40 ` [PATCH v10 12/17] drm: bridge: analogix/dp: add some rk3288 special registers setting Yakir Yang
2015-12-07 6:40 ` [PATCH v10 13/17] drm: bridge: analogix/dp: add max link rate and lane count limit for RK3288 Yakir Yang
2015-12-07 6:40 ` [PATCH v10 14/17] drm: bridge: analogix/dp: try force hpd after plug in lookup failed Yakir Yang
2015-12-08 15:09 ` Rob Herring
2015-12-09 1:21 ` Yakir Yang
2015-12-07 6:40 ` [PATCH v10 15/17] drm: bridge: analogix/dp: move hpd detect to connector detect function Yakir Yang
2015-12-07 6:40 ` [PATCH v10 16/17] drm: bridge: analogix/dp: add edid modes parse in get_modes method Yakir Yang
2015-12-07 6:41 ` [PATCH v10 17/17] drm: bridge: analogix/dp: expand the look time for waiting AUX CH reply Yakir Yang
2015-12-07 7:52 ` [PATCH v11 01/17] drm: bridge: analogix/dp: split exynos dp driver to bridge directory Yakir Yang
2015-12-08 15:33 ` [PATCH v10 0/17] Add Analogix Core Display Port Driver Heiko Stübner
[not found] ` <5667A4B6.4090708@rock-chips.com>
2015-12-09 14:51 ` Heiko Stübner
2015-12-09 2:06 ` [PATCH v10.1 05/17] dt-bindings: add document for analogix display port driver Yakir Yang
2015-12-09 2:07 ` [PATCH v10.1 08/17] dt-bindings: add document for rockchip variant of analogix_dp Yakir Yang
2015-12-09 2:07 ` [PATCH v10.1 10/17] dt-bindings: add document for rockchip dp phy Yakir Yang
2015-12-09 2:10 ` [PATCH v10.1 14/17] drm: bridge: analogix/dp: try force hpd after plug in lookup failed Yakir Yang
2015-12-09 4:25 ` Rob Herring
2015-12-09 5:55 ` Yakir Yang
2015-12-09 6:17 ` [PATCH v10.2 " Yakir Yang
2015-12-10 8:50 ` [PATCH v10.1 15/19] drm: bridge: analogix/dp: move hpd detect to connector detect function Yakir Yang
2015-12-10 8:52 ` [PATCH v10 18/19] drm: bridge: analogix/dp: add panel prepare/unprepare in suspend/resume time Yakir Yang
2015-12-10 8:55 ` [PATCH v10 19/19] drm: bridge: analogix/dp: Fix the possible dead lock in bridge disable time Yakir Yang
2015-12-15 0:06 ` [PATCH v10 0/17] Add Analogix Core Display Port Driver Heiko Stübner
2015-12-16 0:50 ` Yakir Yang
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