From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752848AbbLNGlR (ORCPT ); Mon, 14 Dec 2015 01:41:17 -0500 Received: from mailout2.samsung.com ([203.254.224.25]:34004 "EHLO mailout2.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932126AbbLNGjd (ORCPT ); Mon, 14 Dec 2015 01:39:33 -0500 X-AuditID: cbfee68f-f793a6d000001364-61-566e642225d4 From: Chanwoo Choi To: myungjoo.ham@samsung.com, k.kozlowski@samsung.com, kgene@kernel.org Cc: kyungmin.park@samsung.com, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, linux@arm.linux.org.uk, tjakobi@math.uni-bielefeld.de, linux.amoon@gmail.com, cw00.choi@samsung.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v4 16/20] ARM: dts: Add bus nodes using VDD_MIF for Exynos4210 Date: Mon, 14 Dec 2015 15:38:20 +0900 Message-id: <1450075104-13705-17-git-send-email-cw00.choi@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1450075104-13705-1-git-send-email-cw00.choi@samsung.com> References: <1450075104-13705-1-git-send-email-cw00.choi@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprDIsWRmVeSWpSXmKPExsWyRsSkUFcpJS/MYN0ZbYvrX56zWsw/co7V ov/NQlaLc69WMlq8fmFo0f/4NbPF2aY37BaXd81hs/jce4TRYsb5fUwW6zbeYre4fZnXYun1 i0wWtxtXsFlMmL6WxaJ17xF2i7bVH1gdBD3WzFvD6NHS3MPmcbmvl8lj56y77B4rl39h89i0 qpPN498xdo++LasYPT5vkgvgjOKySUnNySxLLdK3S+DK6FohXLBLpeL7JaUGxucyXYycHBIC JhLz+9pZIWwxiQv31rN1MXJxCAmsYJSYe+oFexcjB1jRrZ+CEPFZjBLXe86zQDhfGCVenl3O DNLNJqAlsf/FDTYQW0TAXeLrvd1gk5gFvjBJtE7+DlYkLOAnsf3GASaQqSwCqhLzNhWAhHkF 3CTOHrwGdYWcxIc9j9hBbE6g+L6v08FmCgm4ShyeDzKGC6imkUPi0LV7YA0sAgIS3yYfYoG4 VFZi0wFmiDmSEgdX3GCZwCi8gJFhFaNoakFyQXFSepGxXnFibnFpXrpecn7uJkZgpJ3+96x/ B+PdA9aHGAU4GJV4eDOW5YYJsSaWFVfmHmI0BdowkVlKNDkfGM95JfGGxmZGFqYmpsZG5pZm SuK8C6V+BgsJpCeWpGanphakFsUXleakFh9iZOLglGpgXOb/KKX4WE0985ZTT7j/FXknN8Uf zS952ZEUw9X2cIvCnsfFETZLVFK+b/8SW1Mszv52qV948g7Z7K1fsmSMxBjkNd0kd+8V7Nd2 tfhk5jopfF7JRJmv2/O+dxQtrJ/6dMv21I6lz19VvF2Tm+l/Q+j2ZmHmLaqHPDyf/l+n8fTE zuMtgTq3lFiKMxINtZiLihMBCbufI68CAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrJIsWRmVeSWpSXmKPExsVy+t9jQV2llLwwg1UbVC2uf3nOajH/yDlW i/43C1ktzr1ayWjx+oWhRf/j18wWZ5vesFtc3jWHzeJz7xFGixnn9zFZrNt4i93i9mVei6XX LzJZ3G5cwWYxYfpaFovWvUfYLdpWf2B1EPRYM28No0dLcw+bx+W+XiaPnbPusnusXP6FzWPT qk42j3/H2D36tqxi9Pi8SS6AM6qB0SYjNTEltUghNS85PyUzL91WyTs43jne1MzAUNfQ0sJc SSEvMTfVVsnFJ0DXLTMH6BUlhbLEnFKgUEBicbGSvh2mCaEhbroWMI0Rur4hQXA9RgZoIGEN Y0bXCuGCXSoV3y8pNTA+l+li5OCQEDCRuPVTsIuRE8gUk7hwbz1bFyMXh5DALEaJ6z3nWSCc L4wSL88uZwapYhPQktj/4gYbiC0i4C7x9d5usA5mgS9MEq2Tv4MVCQv4SWy/cYAJZAOLgKrE vE0FIGFeATeJswevsUJsk5P4sOcRO4jNCRTf93U62EwhAVeJw/O/M09g5F3AyLCKUSK1ILmg OCk91zAvtVyvODG3uDQvXS85P3cTIzian0ntYDy4y/0QowAHoxIPb+ay3DAh1sSy4srcQ4wS HMxKIrwJVnlhQrwpiZVVqUX58UWlOanFhxhNge6ayCwlmpwPTDR5JfGGxiZmRpZG5oYWRsbm SuK8tZciw4QE0hNLUrNTUwtSi2D6mDg4pRoYT8c3Zsds9t1rNck07+Nqlu5kvtdx4tvL8/85 es72upfO6/7Ecn2Cweno2Xc3ibjO5Ip5vZAl9Pnl2lDDlyvXHvW8bDjt5vMlx4L2/Xss9MD6 Txr3S7fPKw+neQddDrcW05Av+F8TbsrxOl4hUEUh+f7aFaefLEhImhVh2+GTYx3G9Vek/l2H EktxRqKhFnNRcSIAwb6s7fwCAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds the bus nodes for Exynos4210 SoC. Exynos4210 SoC has one power line for all buses to translate data between DRAM and sub-blocks. Following list specifies the detailed relation between DRAM and sub-blocks: - DMC/ACP clock for DMC (Dynamic Memory Controller) - ACLK200 clock for LCD0 - ACLK100 clock for PERIL/PERIR/MFC(PCLK) - ACLK160 clock for CAM/TV/LCD0/LCD1 - ACLK133 clock for FSYS/GPS - GDL/GDR clock for LEFTBUS/RIGHTBUS - SCLK_MFC clock for MFC Signed-off-by: Chanwoo Choi Reviewed-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4210.dtsi | 159 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 159 insertions(+) diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index c1cb8df6da07..2d9b02967105 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -257,6 +257,165 @@ power-domains = <&pd_lcd1>; #iommu-cells = <0>; }; + + bus_dmc: bus_dmc { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_DMC>; + clock-names = "bus"; + operating-points-v2 = <&bus_dmc_opp_table>; + status = "disabled"; + }; + + bus_acp: bus_acp { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_ACP>; + clock-names = "bus"; + operating-points-v2 = <&bus_acp_opp_table>; + status = "disabled"; + }; + + bus_peri: bus_peri { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK100>; + clock-names = "bus"; + operating-points-v2 = <&bus_peri_opp_table>; + status = "disabled"; + }; + + bus_fsys: bus_fsys { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK133>; + clock-names = "bus"; + operating-points-v2 = <&bus_fsys_opp_table>; + status = "disabled"; + }; + + bus_display: bus_display { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK160>; + clock-names = "bus"; + operating-points-v2 = <&bus_display_opp_table>; + status = "disabled"; + }; + + bus_lcd0: bus_lcd0 { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK200>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_leftbus: bus_leftbus { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_GDL>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_rightbus: bus_rightbus { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_GDR>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_mfc: bus_mfc { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_SCLK_MFC>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_dmc_opp_table: opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp@134000000 { + opp-hz = /bits/ 64 <134000000>; + opp-microvolt = <1025000>; + }; + opp@267000000 { + opp-hz = /bits/ 64 <267000000>; + opp-microvolt = <1050000>; + }; + opp@400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1150000>; + }; + }; + + bus_acp_opp_table: opp_table2 { + compatible = "operating-points-v2"; + opp-shared; + + opp@134000000 { + opp-hz = /bits/ 64 <134000000>; + }; + opp@160000000 { + opp-hz = /bits/ 64 <160000000>; + }; + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + }; + + bus_peri_opp_table: opp_table3 { + compatible = "operating-points-v2"; + opp-shared; + + opp@5000000 { + opp-hz = /bits/ 64 <5000000>; + }; + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + }; + + bus_fsys_opp_table: opp_table4 { + compatible = "operating-points-v2"; + opp-shared; + + opp@10000000 { + opp-hz = /bits/ 64 <10000000>; + }; + opp@134000000 { + opp-hz = /bits/ 64 <134000000>; + }; + }; + + bus_display_opp_table: opp_table5 { + compatible = "operating-points-v2"; + opp-shared; + + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + opp@134000000 { + opp-hz = /bits/ 64 <134000000>; + }; + opp@160000000 { + opp-hz = /bits/ 64 <160000000>; + }; + }; + + bus_leftbus_opp_table: opp_table6 { + compatible = "operating-points-v2"; + opp-shared; + + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + opp@160000000 { + opp-hz = /bits/ 64 <160000000>; + }; + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + }; }; &gic { -- 1.9.1