On Sun, 2015-12-20 at 22:55 +0200, Andy Shevchenko wrote:
> On Sun, Dec 20, 2015 at 10:17 PM, Andy Shevchenko
> <andy.shevchenko@gmail.com> wrote:
> > On Sun, Dec 20, 2015 at 8:49 PM, Måns Rullgård <mans@mansr.com>
> > wrote:
> > I noticed thanks to DWC_PARAMS that burst size is hardcoded to 32
> > items on this board, however registers for SATA program it to 64. I
> > remember that I got no interrupt when I programmed transfer width
> > wrongly (64 bits against 32 bits) when I ported dw_dmac to be used
> > on
> > Intel SoCs.
> 
> One more thing, I have a patch to monitor DMA IO, we may check what
> exactly the values are written / read  in DMA. I can share it
> tomorrow.

As promised the patch I have to debug IO of DW DMA. Didn't check though
if it applies cleanly on top of recent vanilla kernel.

-- 
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Intel Finland Oy