Re: [PATCH 1/3] ata: sata_dwc_460ex: use "dmas" DT property to find dma channel

[Andy Shevchenko <andriy.shevchenko@linux.intel.com>]

On Mon, 2015-12-21 at 18:16 +0000, Måns Rullgård wrote:
> Andy Shevchenko <andy.shevchenko@gmail.com> writes:
> 
> > On Mon, Dec 21, 2015 at 2:15 PM, Måns Rullgård <mans@mansr.com>
> > wrote:
> > > Andy Shevchenko <andy.shevchenko@gmail.com> writes:
> > > 
> > I used to have a patch to implement this in dw_dmac driver.
> > However, I
> > dropped it at some point. Seems we need it back and now I possible
> > have a good explanation why.
> 
> Are you still able to find that patch?  Shouldn't be too hard to do
> from
> scratch if not.

Yes, I found a version of it, let me mock up tomorrow something
working.

> 
> > > If those values didn't matter, why would the fields exist in the
> > > first place?
> > 
> > Because someone can have more than one AHB bus on the system and
> > connect DMA to all of them (up to 4).
> 
> Which apparently these guys did.  Well, not a full-blown AHB bus, but
> they seem to be using two master interfaces.

To different buses? Intel HW uses two masters and they are quite equal
(at least from OS point of view, it might be HW adjusts it).

> 
> > > > In any case on all Intel SoCs and AVR32, and as far as I can
> > > > tell on
> > > > Spear13xx (Viresh?) there is not a case, that's why I hardly
> > > > imagine
> > > > that the problem is in master numbers by themselves.
> > > 
> > > The 460EX is a PowerPC system.  Expect unusual topologies.
> > 
> > Yeah, that's right.
> 
> BTW, there's a good reason for wiring it like this.  If the source
> and
> destination are on different buses, the DMA engine can do a read and
> a
> write in each cycle.  Otherwise the reads and writes have to be
> issued
> alternately.

Okay. We need first to have a confirmation. I would try to set other
bits under question to see if it helps first (CFG register in DMA).

> Most likely nothing happens, but I think it ought to be
> > > > > fixed.  In fact,
> > > > > I have a patch already.
> > > > 
> > > > Good. Send with Fixes tag if it's upstream ready.
> > > > 
> > > > > Come to think of it, I have an AVR32 dev somewhere.  Maybe I
> > > > > should dust
> > > > > it off.
> > > > 
> > > > I have ATNGW100.
> > > 
> > > I have an AT32ATK1006.  Can you suggest a good test to exercise
> > > the DMA
> > > engine?
> > 
> > On that board I tried MMC (the only available user for me), though
> > it
> > is not reliable, I also tried the dmatest module.
> 
> Hmm, is there anywhere this damn driver actually works?  ;-)

Yes, on Intel HW.

-- 
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Intel Finland Oy