* [PATCH v2 0/5] fix some clock configuration for the RK3036 platform
@ 2016-01-07 12:17 Xing Zheng
2016-01-07 12:17 ` [PATCH v2 1/5] clk: rockchip: rk3036: fix the FLAGs for clock mux Xing Zheng
` (5 more replies)
0 siblings, 6 replies; 8+ messages in thread
From: Xing Zheng @ 2016-01-07 12:17 UTC (permalink / raw)
To: heiko
Cc: keescook, leozwang, linux-rockchip, Xing Zheng, devicetree,
Michael Turquette, Stephen Boyd, linux-kernel, Kumar Gala,
Ian Campbell, Rob Herring, Pawel Moll, Mark Rutland, linux-clk,
linux-arm-kernel
Hi:
In the development work, we found that some of the previous
incorrect clock configuration on the RK3036 platform, we should
fix them.
Xing Zheng (5):
clk: rockchip: rk3036: fix the FLAGs for clock mux
clk: rockchip: rk3036: fix uarts clock error
clk: rockchip: rk3036: fix the div offset for emac clock
clk: rockchip: rk3036: rename emac ext source clock
clk: rockchip: rk3036: add HCLK_MAC id for emac
drivers/clk/rockchip/clk-rk3036.c | 28 ++++++++++++++--------------
include/dt-bindings/clock/rk3036-cru.h | 1 +
2 files changed, 15 insertions(+), 14 deletions(-)
--
1.7.9.5
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 1/5] clk: rockchip: rk3036: fix the FLAGs for clock mux
2016-01-07 12:17 [PATCH v2 0/5] fix some clock configuration for the RK3036 platform Xing Zheng
@ 2016-01-07 12:17 ` Xing Zheng
2016-01-07 12:17 ` [PATCH v2 2/5] clk: rockchip: rk3036: fix uarts clock error Xing Zheng
` (4 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Xing Zheng @ 2016-01-07 12:17 UTC (permalink / raw)
To: heiko
Cc: keescook, leozwang, linux-rockchip, Xing Zheng,
Michael Turquette, Stephen Boyd, linux-clk, linux-arm-kernel,
linux-kernel
The DFLAGS are used for the clock dividers, the CLKSEL_CON flags
of COMPOSITE_NODIV type should be MFLAGS.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
---
drivers/clk/rockchip/clk-rk3036.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c
index ebce980..7e3b41c 100644
--- a/drivers/clk/rockchip/clk-rk3036.c
+++ b/drivers/clk/rockchip/clk-rk3036.c
@@ -224,16 +224,16 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
RK2928_CLKGATE_CON(2), 2, GFLAGS),
COMPOSITE_NODIV(SCLK_TIMER0, "sclk_timer0", mux_timer_p, CLK_IGNORE_UNUSED,
- RK2928_CLKSEL_CON(2), 4, 1, DFLAGS,
+ RK2928_CLKSEL_CON(2), 4, 1, MFLAGS,
RK2928_CLKGATE_CON(1), 0, GFLAGS),
COMPOSITE_NODIV(SCLK_TIMER1, "sclk_timer1", mux_timer_p, CLK_IGNORE_UNUSED,
- RK2928_CLKSEL_CON(2), 5, 1, DFLAGS,
+ RK2928_CLKSEL_CON(2), 5, 1, MFLAGS,
RK2928_CLKGATE_CON(1), 1, GFLAGS),
COMPOSITE_NODIV(SCLK_TIMER2, "sclk_timer2", mux_timer_p, CLK_IGNORE_UNUSED,
- RK2928_CLKSEL_CON(2), 6, 1, DFLAGS,
+ RK2928_CLKSEL_CON(2), 6, 1, MFLAGS,
RK2928_CLKGATE_CON(2), 4, GFLAGS),
COMPOSITE_NODIV(SCLK_TIMER3, "sclk_timer3", mux_timer_p, CLK_IGNORE_UNUSED,
- RK2928_CLKSEL_CON(2), 7, 1, DFLAGS,
+ RK2928_CLKSEL_CON(2), 7, 1, MFLAGS,
RK2928_CLKGATE_CON(2), 5, GFLAGS),
MUX(0, "uart_pll_clk", mux_pll_src_apll_dpll_gpll_usb480m_p, 0,
@@ -279,13 +279,13 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
RK2928_CLKGATE_CON(3), 2, GFLAGS),
COMPOSITE_NODIV(0, "sclk_sdmmc_src", mux_mmc_src_p, 0,
- RK2928_CLKSEL_CON(12), 8, 2, DFLAGS,
+ RK2928_CLKSEL_CON(12), 8, 2, MFLAGS,
RK2928_CLKGATE_CON(2), 11, GFLAGS),
DIV(SCLK_SDMMC, "sclk_sdmmc", "sclk_sdmmc_src", 0,
RK2928_CLKSEL_CON(11), 0, 7, DFLAGS),
COMPOSITE_NODIV(0, "sclk_sdio_src", mux_mmc_src_p, 0,
- RK2928_CLKSEL_CON(12), 10, 2, DFLAGS,
+ RK2928_CLKSEL_CON(12), 10, 2, MFLAGS,
RK2928_CLKGATE_CON(2), 13, GFLAGS),
DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0,
RK2928_CLKSEL_CON(11), 8, 7, DFLAGS),
--
1.7.9.5
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v2 2/5] clk: rockchip: rk3036: fix uarts clock error
2016-01-07 12:17 [PATCH v2 0/5] fix some clock configuration for the RK3036 platform Xing Zheng
2016-01-07 12:17 ` [PATCH v2 1/5] clk: rockchip: rk3036: fix the FLAGs for clock mux Xing Zheng
@ 2016-01-07 12:17 ` Xing Zheng
2016-01-07 12:17 ` [PATCH v2 3/5] clk: rockchip: rk3036: fix the div offset for emac clock Xing Zheng
` (3 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Xing Zheng @ 2016-01-07 12:17 UTC (permalink / raw)
To: heiko
Cc: keescook, leozwang, linux-rockchip, Xing Zheng,
Michael Turquette, Stephen Boyd, linux-clk, linux-arm-kernel,
linux-kernel
Due to a copy-paste error the uart1 and uart2 clock div set
incorrect, we should to fix it.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
---
drivers/clk/rockchip/clk-rk3036.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c
index 7e3b41c..04b5249 100644
--- a/drivers/clk/rockchip/clk-rk3036.c
+++ b/drivers/clk/rockchip/clk-rk3036.c
@@ -242,11 +242,11 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
RK2928_CLKSEL_CON(13), 0, 7, DFLAGS,
RK2928_CLKGATE_CON(1), 8, GFLAGS),
COMPOSITE_NOMUX(0, "uart1_src", "uart_pll_clk", 0,
- RK2928_CLKSEL_CON(13), 0, 7, DFLAGS,
- RK2928_CLKGATE_CON(1), 8, GFLAGS),
+ RK2928_CLKSEL_CON(14), 0, 7, DFLAGS,
+ RK2928_CLKGATE_CON(1), 10, GFLAGS),
COMPOSITE_NOMUX(0, "uart2_src", "uart_pll_clk", 0,
- RK2928_CLKSEL_CON(13), 0, 7, DFLAGS,
- RK2928_CLKGATE_CON(1), 8, GFLAGS),
+ RK2928_CLKSEL_CON(15), 0, 7, DFLAGS,
+ RK2928_CLKGATE_CON(1), 12, GFLAGS),
COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(17), 0,
RK2928_CLKGATE_CON(1), 9, GFLAGS,
--
1.7.9.5
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v2 3/5] clk: rockchip: rk3036: fix the div offset for emac clock
2016-01-07 12:17 [PATCH v2 0/5] fix some clock configuration for the RK3036 platform Xing Zheng
2016-01-07 12:17 ` [PATCH v2 1/5] clk: rockchip: rk3036: fix the FLAGs for clock mux Xing Zheng
2016-01-07 12:17 ` [PATCH v2 2/5] clk: rockchip: rk3036: fix uarts clock error Xing Zheng
@ 2016-01-07 12:17 ` Xing Zheng
2016-01-07 12:17 ` [PATCH v2 4/5] clk: rockchip: rk3036: rename emac ext source clock Xing Zheng
` (2 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Xing Zheng @ 2016-01-07 12:17 UTC (permalink / raw)
To: heiko
Cc: keescook, leozwang, linux-rockchip, Xing Zheng,
Michael Turquette, Stephen Boyd, linux-clk, linux-arm-kernel,
linux-kernel
Due to reference to old version TRM, there are incorrect emac clock node.
The SEL_21_9 is used for the parent div, the SEL_21_4 is used for the
child div.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
---
drivers/clk/rockchip/clk-rk3036.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c
index 04b5249..1f00fab 100644
--- a/drivers/clk/rockchip/clk-rk3036.c
+++ b/drivers/clk/rockchip/clk-rk3036.c
@@ -344,12 +344,12 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
RK2928_CLKGATE_CON(10), 5, GFLAGS),
COMPOSITE_NOGATE(0, "mac_pll_src", mux_pll_src_3plls_p, 0,
- RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 4, 5, DFLAGS),
+ RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 9, 5, DFLAGS),
MUX(SCLK_MACREF, "mac_clk_ref", mux_mac_p, CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(21), 3, 1, MFLAGS),
COMPOSITE_NOMUX(SCLK_MAC, "mac_clk", "mac_clk_ref", 0,
- RK2928_CLKSEL_CON(21), 9, 5, DFLAGS,
+ RK2928_CLKSEL_CON(21), 4, 5, DFLAGS,
RK2928_CLKGATE_CON(2), 6, GFLAGS),
MUX(SCLK_HDMI, "dclk_hdmi", mux_dclk_p, 0,
--
1.7.9.5
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v2 4/5] clk: rockchip: rk3036: rename emac ext source clock
2016-01-07 12:17 [PATCH v2 0/5] fix some clock configuration for the RK3036 platform Xing Zheng
` (2 preceding siblings ...)
2016-01-07 12:17 ` [PATCH v2 3/5] clk: rockchip: rk3036: fix the div offset for emac clock Xing Zheng
@ 2016-01-07 12:17 ` Xing Zheng
2016-01-07 12:26 ` [PATCH v2 5/5] clk: rockchip: rk3036: add HCLK_MAC id for emac Xing Zheng
2016-01-09 20:10 ` [PATCH v2 0/5] fix some clock configuration for the RK3036 platform Heiko Stuebner
5 siblings, 0 replies; 8+ messages in thread
From: Xing Zheng @ 2016-01-07 12:17 UTC (permalink / raw)
To: heiko
Cc: keescook, leozwang, linux-rockchip, Xing Zheng,
Michael Turquette, Stephen Boyd, linux-clk, linux-arm-kernel,
linux-kernel
There is only support rmii in the RK3036, so we should use the correct
ext clock name.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
---
drivers/clk/rockchip/clk-rk3036.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c
index 1f00fab..bc7fbac 100644
--- a/drivers/clk/rockchip/clk-rk3036.c
+++ b/drivers/clk/rockchip/clk-rk3036.c
@@ -133,7 +133,7 @@ PNAME(mux_spdif_p) = { "spdif_src", "spdif_frac", "xin12m" };
PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" };
PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" };
PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" };
-PNAME(mux_mac_p) = { "mac_pll_src", "ext_gmac" };
+PNAME(mux_mac_p) = { "mac_pll_src", "rmii_clkin" };
PNAME(mux_dclk_p) = { "dclk_lcdc", "dclk_cru" };
static struct rockchip_pll_clock rk3036_pll_clks[] __initdata = {
--
1.7.9.5
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v2 5/5] clk: rockchip: rk3036: add HCLK_MAC id for emac
2016-01-07 12:17 [PATCH v2 0/5] fix some clock configuration for the RK3036 platform Xing Zheng
` (3 preceding siblings ...)
2016-01-07 12:17 ` [PATCH v2 4/5] clk: rockchip: rk3036: rename emac ext source clock Xing Zheng
@ 2016-01-07 12:26 ` Xing Zheng
2016-01-09 20:10 ` [PATCH v2 0/5] fix some clock configuration for the RK3036 platform Heiko Stuebner
5 siblings, 0 replies; 8+ messages in thread
From: Xing Zheng @ 2016-01-07 12:26 UTC (permalink / raw)
To: heiko
Cc: mturquette, sboyd, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, zhengxing, linux-clk, linux-arm-kernel,
linux-rockchip, linux-kernel, devicetree, keescook, leozwang
We need to add HCLK_MAC id explicitly because that it is referred
by hclk in the emac driver.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
---
drivers/clk/rockchip/clk-rk3036.c | 2 +-
include/dt-bindings/clock/rk3036-cru.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c
index bc7fbac..15cd29a 100644
--- a/drivers/clk/rockchip/clk-rk3036.c
+++ b/drivers/clk/rockchip/clk-rk3036.c
@@ -404,7 +404,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
GATE(HCLK_OTG1, "hclk_otg1", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(7), 3, GFLAGS),
GATE(HCLK_I2S, "hclk_i2s", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS),
GATE(0, "hclk_sfc", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 14, GFLAGS),
- GATE(0, "hclk_mac", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 15, GFLAGS),
+ GATE(HCLK_MAC, "hclk_mac", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 15, GFLAGS),
/* pclk_peri gates */
GATE(0, "pclk_peri_matrix", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 1, GFLAGS),
diff --git a/include/dt-bindings/clock/rk3036-cru.h b/include/dt-bindings/clock/rk3036-cru.h
index ebc7a7b..3396591 100644
--- a/include/dt-bindings/clock/rk3036-cru.h
+++ b/include/dt-bindings/clock/rk3036-cru.h
@@ -92,6 +92,7 @@
#define HCLK_SDMMC 456
#define HCLK_SDIO 457
#define HCLK_EMMC 459
+#define HCLK_MAC 460
#define HCLK_I2S 462
#define HCLK_LCDC 465
#define HCLK_ROM 467
--
1.7.9.5
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v2 0/5] fix some clock configuration for the RK3036 platform
2016-01-07 12:17 [PATCH v2 0/5] fix some clock configuration for the RK3036 platform Xing Zheng
` (4 preceding siblings ...)
2016-01-07 12:26 ` [PATCH v2 5/5] clk: rockchip: rk3036: add HCLK_MAC id for emac Xing Zheng
@ 2016-01-09 20:10 ` Heiko Stuebner
2016-01-10 7:26 ` Xing Zheng
5 siblings, 1 reply; 8+ messages in thread
From: Heiko Stuebner @ 2016-01-09 20:10 UTC (permalink / raw)
To: Xing Zheng
Cc: keescook, leozwang, linux-rockchip, devicetree,
Michael Turquette, Stephen Boyd, linux-kernel, Kumar Gala,
Ian Campbell, Rob Herring, Pawel Moll, Mark Rutland, linux-clk,
linux-arm-kernel
Hi Xing
Am Donnerstag, 7. Januar 2016, 20:17:32 schrieb Xing Zheng:
> In the development work, we found that some of the previous
> incorrect clock configuration on the RK3036 platform, we should
> fix them.
I've applied patches 1-4 as fixes for 4.5 [0] and will apply patch 5
regularly once 4.5-rc1 is released and I have stable base again.
> Xing Zheng (5):
> clk: rockchip: rk3036: fix the FLAGs for clock mux
> clk: rockchip: rk3036: fix uarts clock error
> clk: rockchip: rk3036: fix the div offset for emac clock
> clk: rockchip: rk3036: rename emac ext source clock
please make sure to also update the binding document in such cases.
I've done it myself for this one.
[for people reading along: the rk3036 clock-driver + binding is new in
4.5 so we should be ok to fix the naming before it is actually released]
Heiko
[0] https://git.kernel.org/cgit/linux/kernel/git/mmind/linux-rockchip.git/log/?h=v4.5-clk/fixes
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 0/5] fix some clock configuration for the RK3036 platform
2016-01-09 20:10 ` [PATCH v2 0/5] fix some clock configuration for the RK3036 platform Heiko Stuebner
@ 2016-01-10 7:26 ` Xing Zheng
0 siblings, 0 replies; 8+ messages in thread
From: Xing Zheng @ 2016-01-10 7:26 UTC (permalink / raw)
To: Heiko Stuebner
Cc: keescook, leozwang, linux-rockchip, devicetree,
Michael Turquette, Stephen Boyd, linux-kernel, Kumar Gala,
Ian Campbell, Rob Herring, Pawel Moll, Mark Rutland, linux-clk,
linux-arm-kernel, 郑兴
Hi Heiko,
On 2016年01月10日 04:10, Heiko Stuebner wrote:
> Hi Xing
>
> Am Donnerstag, 7. Januar 2016, 20:17:32 schrieb Xing Zheng:
>> In the development work, we found that some of the previous
>> incorrect clock configuration on the RK3036 platform, we should
>> fix them.
> I've applied patches 1-4 as fixes for 4.5 [0] and will apply patch 5
> regularly once 4.5-rc1 is released and I have stable base again.
>
>
>> Xing Zheng (5):
>> clk: rockchip: rk3036: fix the FLAGs for clock mux
>> clk: rockchip: rk3036: fix uarts clock error
>> clk: rockchip: rk3036: fix the div offset for emac clock
>> clk: rockchip: rk3036: rename emac ext source clock
> please make sure to also update the binding document in such cases.
> I've done it myself for this one.
>
> [for people reading along: the rk3036 clock-driver + binding is new in
> 4.5 so we should be ok to fix the naming before it is actually released]
>
>
> Heiko
>
>
> [0] https://git.kernel.org/cgit/linux/kernel/git/mmind/linux-rockchip.git/log/?h=v4.5-clk/fixes
>
OK, I have updated the rockchip,rk3036-cru.txt and sent a patch to the
upstream.
Thanks.
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2016-01-10 7:26 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
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2016-01-07 12:17 [PATCH v2 0/5] fix some clock configuration for the RK3036 platform Xing Zheng
2016-01-07 12:17 ` [PATCH v2 1/5] clk: rockchip: rk3036: fix the FLAGs for clock mux Xing Zheng
2016-01-07 12:17 ` [PATCH v2 2/5] clk: rockchip: rk3036: fix uarts clock error Xing Zheng
2016-01-07 12:17 ` [PATCH v2 3/5] clk: rockchip: rk3036: fix the div offset for emac clock Xing Zheng
2016-01-07 12:17 ` [PATCH v2 4/5] clk: rockchip: rk3036: rename emac ext source clock Xing Zheng
2016-01-07 12:26 ` [PATCH v2 5/5] clk: rockchip: rk3036: add HCLK_MAC id for emac Xing Zheng
2016-01-09 20:10 ` [PATCH v2 0/5] fix some clock configuration for the RK3036 platform Heiko Stuebner
2016-01-10 7:26 ` Xing Zheng
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