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From: Chen-Yu Tsai <wens@csie.org>
To: Ulf Hansson <ulf.hansson@linaro.org>,
	Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Chen-Yu Tsai <wens@csie.org>, Hans de Goede <hdegoede@redhat.com>,
	linux-mmc@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com
Subject: [PATCH RFC 12/15] ARM: dts: sun9i: Use sun9i specific mmc compatible
Date: Thu, 21 Jan 2016 13:26:39 +0800	[thread overview]
Message-ID: <1453354002-28366-13-git-send-email-wens@csie.org> (raw)
In-Reply-To: <1453354002-28366-1-git-send-email-wens@csie.org>

sun9i/A80 MMC controllers have a larger FIFO, and the FIFO DMA
trigger levels can be increased. Also, the mmc module clock parent
has a higher clock rate, and the sample and output delay phases
are different.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun9i-a80.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index e838f206f2a0..f4f61b02be1a 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -543,7 +543,7 @@
 		};
 
 		mmc0: mmc@01c0f000 {
-			compatible = "allwinner,sun5i-a13-mmc";
+			compatible = "allwinner,sun9i-a80-mmc";
 			reg = <0x01c0f000 0x1000>;
 			clocks = <&mmc_config_clk 0>, <&mmc0_clk 0>,
 				 <&mmc0_clk 1>, <&mmc0_clk 2>;
@@ -557,7 +557,7 @@
 		};
 
 		mmc1: mmc@01c10000 {
-			compatible = "allwinner,sun5i-a13-mmc";
+			compatible = "allwinner,sun9i-a80-mmc";
 			reg = <0x01c10000 0x1000>;
 			clocks = <&mmc_config_clk 1>, <&mmc1_clk 0>,
 				 <&mmc1_clk 1>, <&mmc1_clk 2>;
@@ -571,7 +571,7 @@
 		};
 
 		mmc2: mmc@01c11000 {
-			compatible = "allwinner,sun5i-a13-mmc";
+			compatible = "allwinner,sun9i-a80-mmc";
 			reg = <0x01c11000 0x1000>;
 			clocks = <&mmc_config_clk 2>, <&mmc2_clk 0>,
 				 <&mmc2_clk 1>, <&mmc2_clk 2>;
@@ -585,7 +585,7 @@
 		};
 
 		mmc3: mmc@01c12000 {
-			compatible = "allwinner,sun5i-a13-mmc";
+			compatible = "allwinner,sun9i-a80-mmc";
 			reg = <0x01c12000 0x1000>;
 			clocks = <&mmc_config_clk 3>, <&mmc3_clk 0>,
 				 <&mmc3_clk 1>, <&mmc3_clk 2>;
-- 
2.7.0.rc3

  parent reply	other threads:[~2016-01-21  5:35 UTC|newest]

Thread overview: 43+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-01-21  5:26 [PATCH RFC 00/15] mmc: sunxi: Support vqmmc regulator and eMMC DDR modes Chen-Yu Tsai
2016-01-21  5:26 ` [PATCH RFC 01/15] mmc: sunxi: Document host init sequence Chen-Yu Tsai
2016-01-29 11:39   ` Ulf Hansson
2016-01-21  5:26 ` [PATCH RFC 02/15] mmc: sunxi: Return error on mmc_regulator_set_ocr() fail in .set_ios op Chen-Yu Tsai
2016-01-29 11:40   ` Ulf Hansson
2016-01-21  5:26 ` [PATCH RFC 03/15] mmc: sunxi: Block signal voltage switching (CMD11) Chen-Yu Tsai
2016-01-29 10:42   ` Ulf Hansson
2016-01-29 14:44     ` Chen-Yu Tsai
2016-01-21  5:26 ` [PATCH RFC 04/15] mmc: sunxi: Support vqmmc regulator Chen-Yu Tsai
2016-01-29 11:40   ` Ulf Hansson
2016-01-21  5:26 ` [PATCH RFC 05/15] mmc: sunxi: Support MMC_DDR52 timing modes Chen-Yu Tsai
2016-01-21 11:14   ` Hans de Goede
2016-01-21 11:55     ` Chen-Yu Tsai
2016-01-21 12:26       ` Hans de Goede
2016-01-21  5:26 ` [PATCH RFC 06/15] mmc: sunxi: Support 8 bit eMMC DDR transfer modes Chen-Yu Tsai
2016-01-21  5:26 ` [PATCH RFC 07/15] mmc: sunxi: Enable eMMC HS-DDR (MMC_CAP_1_8V_DDR) support Chen-Yu Tsai
2016-01-21  5:26 ` [PATCH RFC 08/15] ARM: dts: sun6i: Add mmc3 pins for 8 bit emmc Chen-Yu Tsai
2016-01-22 20:31   ` Maxime Ripard
2016-01-23 11:04     ` Chen-Yu Tsai
2016-01-24 16:54       ` Maxime Ripard
2016-01-21  5:26 ` [PATCH RFC 09/15] ARM: dts: sun6i: sina31s: Switch to mmc3 for onboard eMMC Chen-Yu Tsai
2016-01-21 11:16   ` Hans de Goede
2016-01-21 12:23     ` Chen-Yu Tsai
2016-01-21 12:25       ` Hans de Goede
2016-01-21 12:28         ` Chen-Yu Tsai
2016-01-21 12:38           ` Hans de Goede
2016-01-22 20:39   ` Maxime Ripard
2016-01-23  4:21     ` Chen-Yu Tsai
2016-01-24 16:56       ` Maxime Ripard
2016-01-21  5:26 ` [PATCH RFC 10/15] ARM: dts: sun8i: Include SDC2_RST pin in mmc2_8bit_pins Chen-Yu Tsai
2016-01-24 16:58   ` Maxime Ripard
2016-01-21  5:26 ` [PATCH RFC 11/15] ARM: dts: sun8i: sina33: Enable hardware reset and HS-DDR for eMMC Chen-Yu Tsai
2016-01-22 20:42   ` Maxime Ripard
2016-01-21  5:26 ` Chen-Yu Tsai [this message]
2016-01-22 20:44   ` [PATCH RFC 12/15] ARM: dts: sun9i: Use sun9i specific mmc compatible Maxime Ripard
2016-01-23 10:50     ` Chen-Yu Tsai
2016-01-21  5:26 ` [PATCH RFC 13/15] ARM: dts: sun9i: Include SDC2_RST pin in mmc2_8bit_pins Chen-Yu Tsai
2016-01-24 16:58   ` Maxime Ripard
2016-01-21  5:26 ` [PATCH RFC 14/15] ARM: dts: sun9i: a80-optimus: Enable hardware reset and HS-DDR for eMMC Chen-Yu Tsai
2016-01-24 16:59   ` Maxime Ripard
2016-01-21  5:26 ` [PATCH RFC 15/15] ARM: dts: sun9i: cubieboard4: " Chen-Yu Tsai
2016-01-24 16:59   ` Maxime Ripard
2016-01-21 11:19 ` [PATCH RFC 00/15] mmc: sunxi: Support vqmmc regulator and eMMC DDR modes Hans de Goede

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