From: Toshi Kani <toshi.kani@hpe.com>
To: mingo@kernel.org, bp@suse.de, hpa@zytor.com, tglx@linutronix.de
Cc: mcgrof@suse.com, jgross@suse.com, paul.gortmaker@windriver.com,
x86@kernel.org, linux-kernel@vger.kernel.org,
Toshi Kani <toshi.kani@hpe.com>
Subject: [PATCH 1/2] x86/mm/pat: Change pat_disable() to emulate PAT table
Date: Thu, 10 Mar 2016 21:45:45 -0700 [thread overview]
Message-ID: <1457671546-13486-2-git-send-email-toshi.kani@hpe.com> (raw)
In-Reply-To: <1457671546-13486-1-git-send-email-toshi.kani@hpe.com>
Since 'commit 9cd25aac1f44 ("x86/mm/pat: Emulate PAT when it
is disabled")', we emulate a PAT table when PAT is disabled.
This requires pat_init() be called even if PAT is disabled,
which revealed a long standing issue that PAT is left enabled
without calling pat_init() at all.
pat_init() is called from MTRR code since it relies on MTRR's
rendezvous handler to initialize PAT for all APs . However,
when CPU does not support MTRR, ex. qemu32's virtual CPU, MTRR
is set disabled and does not call pat_init(). There is no
interface available for MTRR to disable PAT, either.
Change pat_disable() to a regular function (from an inline func)
so that MTRR can call it to disable PAT when MTRR is disabled.
pat_disable() sets PAT disabled, and calls pat_disable_init()
to emulate the PAT table.
link: https://lkml.org/lkml/2016/3/10/402
Reported-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Toshi Kani <toshi.kani@hpe.com>
Cc: Borislav Petkov <bp@suse.de>
Cc: Luis R. Rodriguez <mcgrof@suse.com>
Cc: Juergen Gross <jgross@suse.com>
Cc: Ingo Molnar <mingo@kernel.org>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
---
arch/x86/include/asm/pat.h | 1 +
arch/x86/mm/pat.c | 84 +++++++++++++++++++++++++++-----------------
2 files changed, 52 insertions(+), 33 deletions(-)
diff --git a/arch/x86/include/asm/pat.h b/arch/x86/include/asm/pat.h
index ca6c228..016142b 100644
--- a/arch/x86/include/asm/pat.h
+++ b/arch/x86/include/asm/pat.h
@@ -5,6 +5,7 @@
#include <asm/pgtable_types.h>
bool pat_enabled(void);
+void pat_disable(const char *reason);
extern void pat_init(void);
void pat_init_cache_modes(u64);
diff --git a/arch/x86/mm/pat.c b/arch/x86/mm/pat.c
index f4ae536..1ff8aa9 100644
--- a/arch/x86/mm/pat.c
+++ b/arch/x86/mm/pat.c
@@ -40,11 +40,19 @@
static bool boot_cpu_done;
static int __read_mostly __pat_enabled = IS_ENABLED(CONFIG_X86_PAT);
+static void pat_disable_init(void);
-static inline void pat_disable(const char *reason)
+void pat_disable(const char *reason)
{
+ if (boot_cpu_done) {
+ pr_info("x86/PAT: PAT cannot be disabled after initialized\n");
+ return;
+ }
+
__pat_enabled = 0;
pr_info("x86/PAT: %s\n", reason);
+
+ pat_disable_init();
}
static int __init nopat(char *str)
@@ -207,9 +215,6 @@ static void pat_bsp_init(u64 pat)
return;
}
- if (!pat_enabled())
- goto done;
-
rdmsrl(MSR_IA32_CR_PAT, tmp_pat);
if (!tmp_pat) {
pat_disable("PAT MSR is 0, disabled.");
@@ -218,15 +223,11 @@ static void pat_bsp_init(u64 pat)
wrmsrl(MSR_IA32_CR_PAT, pat);
-done:
pat_init_cache_modes(pat);
}
static void pat_ap_init(u64 pat)
{
- if (!pat_enabled())
- return;
-
if (!cpu_has_pat) {
/*
* If this happens we are on a secondary CPU, but switched to
@@ -238,38 +239,55 @@ static void pat_ap_init(u64 pat)
wrmsrl(MSR_IA32_CR_PAT, pat);
}
+static void pat_disable_init(void)
+{
+ u64 pat;
+ static int disable_init_done;
+
+ if (disable_init_done)
+ return;
+
+ /*
+ * No PAT. Emulate the PAT table that corresponds to the two
+ * cache bits, PWT (Write Through) and PCD (Cache Disable). This
+ * setup is the same as the BIOS default setup when the system
+ * has PAT but the "nopat" boot option has been specified. This
+ * emulated PAT table is used when MSR_IA32_CR_PAT returns 0.
+ *
+ * PTE encoding:
+ *
+ * PCD
+ * |PWT PAT
+ * || slot
+ * 00 0 WB : _PAGE_CACHE_MODE_WB
+ * 01 1 WT : _PAGE_CACHE_MODE_WT
+ * 10 2 UC-: _PAGE_CACHE_MODE_UC_MINUS
+ * 11 3 UC : _PAGE_CACHE_MODE_UC
+ *
+ * NOTE: When WC or WP is used, it is redirected to UC- per
+ * the default setup in __cachemode2pte_tbl[].
+ */
+ pat = PAT(0, WB) | PAT(1, WT) | PAT(2, UC_MINUS) | PAT(3, UC) |
+ PAT(4, WB) | PAT(5, WT) | PAT(6, UC_MINUS) | PAT(7, UC);
+
+ pat_init_cache_modes(pat);
+
+ disable_init_done = 1;
+}
+
void pat_init(void)
{
u64 pat;
struct cpuinfo_x86 *c = &boot_cpu_data;
if (!pat_enabled()) {
- /*
- * No PAT. Emulate the PAT table that corresponds to the two
- * cache bits, PWT (Write Through) and PCD (Cache Disable). This
- * setup is the same as the BIOS default setup when the system
- * has PAT but the "nopat" boot option has been specified. This
- * emulated PAT table is used when MSR_IA32_CR_PAT returns 0.
- *
- * PTE encoding:
- *
- * PCD
- * |PWT PAT
- * || slot
- * 00 0 WB : _PAGE_CACHE_MODE_WB
- * 01 1 WT : _PAGE_CACHE_MODE_WT
- * 10 2 UC-: _PAGE_CACHE_MODE_UC_MINUS
- * 11 3 UC : _PAGE_CACHE_MODE_UC
- *
- * NOTE: When WC or WP is used, it is redirected to UC- per
- * the default setup in __cachemode2pte_tbl[].
- */
- pat = PAT(0, WB) | PAT(1, WT) | PAT(2, UC_MINUS) | PAT(3, UC) |
- PAT(4, WB) | PAT(5, WT) | PAT(6, UC_MINUS) | PAT(7, UC);
+ pat_disable_init();
+ return;
+ }
- } else if ((c->x86_vendor == X86_VENDOR_INTEL) &&
- (((c->x86 == 0x6) && (c->x86_model <= 0xd)) ||
- ((c->x86 == 0xf) && (c->x86_model <= 0x6)))) {
+ if ((c->x86_vendor == X86_VENDOR_INTEL) &&
+ (((c->x86 == 0x6) && (c->x86_model <= 0xd)) ||
+ ((c->x86 == 0xf) && (c->x86_model <= 0x6)))) {
/*
* PAT support with the lower four entries. Intel Pentium 2,
* 3, M, and 4 are affected by PAT errata, which makes the
next prev parent reply other threads:[~2016-03-11 3:53 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-11 4:45 [PATCH 0/2] Refactor MTRR and PAT initializations Toshi Kani
2016-03-11 4:45 ` Toshi Kani [this message]
2016-03-11 9:12 ` [PATCH 1/2] x86/mm/pat: Change pat_disable() to emulate PAT table Borislav Petkov
2016-03-11 16:27 ` Toshi Kani
2016-03-11 15:54 ` Borislav Petkov
2016-03-11 19:28 ` Toshi Kani
2016-03-12 11:55 ` Borislav Petkov
2016-03-14 21:37 ` Toshi Kani
2016-03-15 11:00 ` Borislav Petkov
2016-03-15 22:02 ` Toshi Kani
2016-03-15 0:29 ` Luis R. Rodriguez
2016-03-15 3:11 ` Toshi Kani
2016-03-15 11:01 ` Borislav Petkov
2016-03-15 15:43 ` Toshi Kani
2016-03-15 15:47 ` Borislav Petkov
2016-03-15 17:11 ` Toshi Kani
2016-03-15 16:33 ` Borislav Petkov
2016-03-15 21:31 ` Luis R. Rodriguez
2016-03-11 4:45 ` [PATCH 2/2] x86/mtrr: Refactor PAT initialization code Toshi Kani
2016-03-11 9:01 ` Ingo Molnar
2016-03-11 9:13 ` Ingo Molnar
2016-03-11 18:34 ` Toshi Kani
2016-03-12 16:18 ` Ingo Molnar
2016-03-14 19:47 ` Toshi Kani
2016-03-14 22:50 ` Luis R. Rodriguez
2016-03-15 0:37 ` Toshi Kani
2016-03-15 15:56 ` Borislav Petkov
2016-03-16 15:44 ` Joe Lawrence
2016-03-11 9:24 ` Borislav Petkov
2016-03-11 18:57 ` Toshi Kani
2016-03-11 22:17 ` Luis R. Rodriguez
2016-03-11 23:56 ` Toshi Kani
2016-03-11 23:34 ` Luis R. Rodriguez
2016-03-12 1:16 ` Toshi Kani
2016-03-15 0:15 ` Luis R. Rodriguez
2016-03-15 23:48 ` Toshi Kani
2016-03-15 23:29 ` Luis R. Rodriguez
2016-03-17 21:56 ` Toshi Kani
2016-03-18 0:06 ` Luis R. Rodriguez
2016-03-18 21:35 ` Toshi Kani
2016-03-29 17:14 ` Luis R. Rodriguez
2016-03-29 21:46 ` Toshi Kani
2016-03-29 22:12 ` Luis R. Rodriguez
2016-03-30 0:16 ` Toshi Kani
2016-03-29 23:43 ` Luis R. Rodriguez
2016-03-30 1:07 ` Toshi Kani
2016-03-30 0:34 ` Luis R. Rodriguez
2016-04-09 2:04 ` Luis R. Rodriguez
2016-04-11 14:30 ` Toshi Kani
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