From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754611AbcDAF2e (ORCPT ); Fri, 1 Apr 2016 01:28:34 -0400 Received: from mail-bn1on0095.outbound.protection.outlook.com ([157.56.110.95]:43472 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752039AbcDAF2c (ORCPT ); Fri, 1 Apr 2016 01:28:32 -0400 Authentication-Results: spf=none (sender IP is 165.204.84.222) smtp.mailfrom=amd.com; 8bytes.org; dkim=none (message not signed) header.d=none;8bytes.org; dmarc=permerror action=none header.from=amd.com; X-WSS-ID: 0O4XWJ9-08-O0P-02 X-M-MSG: From: Wan Zongshun To: Joerg Roedel , CC: Suravee Suthikulpanit , Borislav Petkov , Ray Huang , , , Subject: [PATCH V3 1/9] iommu/amd: Adding Extended Feature Register check for PC support Date: Fri, 1 Apr 2016 09:05:57 -0400 Message-ID: <1459515965-2865-2-git-send-email-vincent.wan@amd.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1459515965-2865-1-git-send-email-vincent.wan@amd.com> References: <1459515965-2865-1-git-send-email-vincent.wan@amd.com> MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:165.204.84.222;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(6009001)(2980300002)(428002)(199003)(189002)(48376002)(229853001)(5001770100001)(86362001)(5003940100001)(50466002)(36756003)(77096005)(81166005)(106466001)(19580405001)(19580395003)(92566002)(87936001)(47776003)(105586002)(5003600100002)(53416004)(101416001)(2906002)(1220700001)(1096002)(5008740100001)(4326007)(586003)(189998001)(2950100001)(50226001)(76176999)(50986999)(33646002);DIR:OUT;SFP:1101;SCL:1;SRVR:CY1PR12MB0853;H:atltwp02.amd.com;FPR:;SPF:None;MLV:sfv;A:1;MX:1;LANG:en; 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This should be used to determine the IOMMU performance support instead of relying on the PNCounters and PNBanks. Note also that the PNCouters and PNBanks bits in the IOMMU attributes field of IVHD headers type 11h are incorrectly programmed on some systems. So, we should not rely on it to determine the performance counter/banks size. Instead, these values should be read from the MMIO Offset 0030h IOMMU Extended Feature Register. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd_iommu_init.c | 32 ++++++++++++++++++++++++-------- 1 file changed, 24 insertions(+), 8 deletions(-) diff --git a/drivers/iommu/amd_iommu_init.c b/drivers/iommu/amd_iommu_init.c index bf4959f..dff1e01 100644 --- a/drivers/iommu/amd_iommu_init.c +++ b/drivers/iommu/amd_iommu_init.c @@ -99,7 +99,11 @@ struct ivhd_header { u64 mmio_phys; u16 pci_seg; u16 info; - u32 efr; + u32 efr_attr; + + /* Following only valid on IVHD type 11h and 40h */ + u64 efr_reg; /* Exact copy of MMIO_EXT_FEATURES */ + u64 res; } __attribute__((packed)); /* @@ -1078,13 +1082,25 @@ static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h) iommu->pci_seg = h->pci_seg; iommu->mmio_phys = h->mmio_phys; - /* Check if IVHD EFR contains proper max banks/counters */ - if ((h->efr != 0) && - ((h->efr & (0xF << 13)) != 0) && - ((h->efr & (0x3F << 17)) != 0)) { - iommu->mmio_phys_end = MMIO_REG_END_OFFSET; - } else { - iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET; + switch (h->type) { + case 0x10: + /* Check if IVHD EFR contains proper max banks/counters */ + if ((h->efr_attr != 0) && + ((h->efr_attr & (0xF << 13)) != 0) && + ((h->efr_attr & (0x3F << 17)) != 0)) + iommu->mmio_phys_end = MMIO_REG_END_OFFSET; + else + iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET; + break; + case 0x11: + case 0x40: + if (h->efr_reg & (1 << 9)) + iommu->mmio_phys_end = MMIO_REG_END_OFFSET; + else + iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET; + break; + default: + return -EINVAL; } iommu->mmio_base = iommu_map_mmio_space(iommu->mmio_phys, -- 1.9.1