From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755921AbcDDQW5 (ORCPT ); Mon, 4 Apr 2016 12:22:57 -0400 Received: from mirror2.csie.ntu.edu.tw ([140.112.30.76]:49434 "EHLO wens.csie.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754853AbcDDQWw (ORCPT ); Mon, 4 Apr 2016 12:22:52 -0400 From: Chen-Yu Tsai To: Maxime Ripard , Florian Fainelli , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala Cc: Chen-Yu Tsai , netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, LABBE Corentin Subject: [PATCH RFC 1/5] net: phy: sun8i-h3-ephy: Add bindings for Allwinner H3 Ethernet PHY Date: Tue, 5 Apr 2016 00:22:30 +0800 Message-Id: <1459786954-12649-2-git-send-email-wens@csie.org> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1459786954-12649-1-git-send-email-wens@csie.org> References: <1459786954-12649-1-git-send-email-wens@csie.org> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The Allwinner H3 SoC incorporates an Ethernet PHY. This is enabled and configured through a memory mapped hardware register. This same register also configures the MAC interface mode and TX clock source. Also covered by the register, but not supported in these bindings, are TX/RX clock delay chains and inverters, and an RMII module. Signed-off-by: Chen-Yu Tsai --- .../bindings/net/allwinner,sun8i-h3-ephy.txt | 44 ++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/allwinner,sun8i-h3-ephy.txt diff --git a/Documentation/devicetree/bindings/net/allwinner,sun8i-h3-ephy.txt b/Documentation/devicetree/bindings/net/allwinner,sun8i-h3-ephy.txt new file mode 100644 index 000000000000..146f227e6d88 --- /dev/null +++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-h3-ephy.txt @@ -0,0 +1,44 @@ +* Allwinner H3 E(thernet) PHY + +The Allwinner H3 integrates an MII ethernet PHY. As with external PHYs, +before it can be configured over the MDIO bus and used, certain hardware +features must be configured, such as the PHY address and LED polarity. +The PHY must also be powered on and brought out of reset. + +This is accomplished with regulators and pull-up/downs for external PHYs. +For this internal PHY, a hardware register is programmed. + +The same hardware register also contains clock and interface controls +for the MAC. This is also present in earlier SoCs, and is covered by +"allwinner,sun7i-a20-gmac-clk". The controls in the H3 are slightly +different due to the inclusion of what appears to be an RMII-MII +bridge. + +Required properties: +- compatible: should be "allwinner,sun8i-h3-ephy" +- reg: address and length of the register set for the device +- clocks: A phandle to the reference clock for this device +- resets: A phandle to the reset control for this device + +Ethernet PHY related properties: +- allwinner,ephy-addr: the MDIO bus address the PHY should respond to. + If this is not set, the external PHY is used, and + everything else in this section is ignored. +- allwinner,leds-active-low: LEDs are active low. Without this, LEDs are + active high. + +Ethernet MAC clock related properties: +- #clock-cells: should be 0 +- clock-output-names: "mac_tx" + +Example: + +ethernet-phy@01c00030 { + compatible = "allwinner,sun8i-h3-ephy"; + reg = <0x01c00030 0x4>; + clocks = <&bus_gates 128>; + resets = <&ahb_rst 66>; + allwinner,ephy-addr = <0x1>; + #clock-cells = <0>; + clock-output-names = "mac_tx"; +}; -- 2.7.0