From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752961AbcDOIxT (ORCPT ); Fri, 15 Apr 2016 04:53:19 -0400 Received: from mail-bl2nam02on0085.outbound.protection.outlook.com ([104.47.38.85]:53607 "EHLO NAM02-BL2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751591AbcDOIxM (ORCPT ); Fri, 15 Apr 2016 04:53:12 -0400 Authentication-Results: spf=pass (sender IP is 149.199.60.83) smtp.mailfrom=xilinx.com; vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=bestguesspass action=none header.from=xilinx.com; From: Kedareswara rao Appana To: , , , , , , , , , , , , , , CC: , , , Subject: [PATCH v6 1/2] Documentation: DT: dma: Add Xilinx zynqmp dma device tree binding documentation Date: Fri, 15 Apr 2016 14:22:53 +0530 Message-ID: <1460710374-25077-1-git-send-email-appanad@xilinx.com> X-Mailer: git-send-email 2.1.2 X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.0.0.1202-22262.001 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:149.199.60.83;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(6009001)(2980300002)(438002)(199003)(189002)(47776003)(50986999)(48376002)(36386004)(63266004)(11100500001)(87936001)(4326007)(4001450100002)(6806005)(229853001)(45336002)(1220700001)(42186005)(92566002)(33646002)(19580395003)(189998001)(575784001)(86362001)(2906002)(50226001)(90966002)(52956003)(5003940100001)(551934003)(5001770100001)(19580405001)(1096002)(81166005)(5008740100001)(46386002)(36756003)(103686003)(586003)(106466001)(50466002)(2201001)(921003)(107986001)(1121003)(2101003)(83996005);DIR:OUT;SFP:1101;SCL:1;SRVR:CY1NAM02HT051;H:xsj-pvapsmtpgw01;FPR:;SPF:Pass;MLV:nov;A:1;MX:1;PTR:unknown-60-83.xilinx.com;LANG:en; MIME-Version: 1.0 Content-Type: text/plain X-MS-Office365-Filtering-Correlation-Id: 1f0b1272-7434-4422-5dc3-08d3650b5e8d X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:(8251501002);SRVR:CY1NAM02HT051; X-Microsoft-Antispam-PRVS: <96747ffafdc149ac84d428f2e5259927@CY1NAM02HT051.eop-nam02.prod.protection.outlook.com> X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(9101521026)(601004)(2401047)(13017025)(13023025)(13018025)(13024025)(8121501046)(13015025)(5005006)(3002001)(10201501046)(6055026);SRVR:CY1NAM02HT051;BCL:0;PCL:0;RULEID:;SRVR:CY1NAM02HT051; X-Forefront-PRVS: 0913EA1D60 X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Apr 2016 08:53:08.6748 (UTC) X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.60.83];Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1NAM02HT051 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Device-tree binding documentation for Xilinx zynqmp dma engine used in Zynq UltraScale+ MPSoC. Signed-off-by: Punnaiah Choudary Kalluri Signed-off-by: Kedareswara rao Appana --- Changes in v6: - Removed desc-axi-cache/dst-axi-cache/src-axi-cache properties from the binding doc as it allow broken combinations when dma-coherent is set as suggested by Rob. - Fixed minor comments given by Rob related coding(lower case DT node name). Changes in v5: - Use dma-coherent flag for coherent transfers as suggested by rob. - Removed unnecessary properties from binding doc as suggested by Rob. Changes in v4: - None Changes in v3: - None Changes in v2: - None. .../devicetree/bindings/dma/xilinx/zynqmp_dma.txt | 44 ++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt diff --git a/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt new file mode 100644 index 0000000..f0f0b54 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt @@ -0,0 +1,44 @@ +Xilinx ZynqMP DMA engine, it does support memory to memory transfers, +memory to device and device to memory transfers. It also has flow +control and rate control support for slave/peripheral dma access. + +Required properties: +- compatible : Should be "xlnx,zynqmp-dma-1.0" +- reg : Memory map for gdma/adma module access. +- interrupt-parent : Interrupt controller the interrupt is routed through +- interrupts : Should contain DMA channel interrupt. +- xlnx,bus-width : Axi buswidth in bits. Should contain 128 or 64 +- clock-names : List of input clocks "clk_main", "clk_apb" + (see clock bindings for details) + +Optional properties: +- xlnx,include-sg : Indicates the controller to operate in simple or + scatter gather dma mode +- xlnx,ratectrl : Scheduling interval in terms of clock cycles for + source AXI transaction +- xlnx,overfetch : Tells whether the channel is allowed to over + fetch the data +- xlnx,src-issue : Number of AXI outstanding transactions on source side +- xlnx,src-burst-len : AXI length for data read. Support only power of + 2 byte values. +- xlnx,dst-burst-len : AXI length for data write. Support only power of + 2 byte values. +- dma-coherent : Present if dma operations are coherent. + +Example: +++++++++ +fpd_dma_chan1: dma@fd500000 { + compatible = "xlnx,zynqmp-dma-1.0"; + reg = <0x0 0xFD500000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 117 4>; + clock-names = "clk_main", "clk_apb"; + xlnx,bus-width = <128>; + xlnx,include-sg; + xlnx,overfetch; + dma-coherent; + xlnx,ratectrl = <0>; + xlnx,src-issue = <16>; + xlnx,src-burst-len = <4>; + xlnx,dst-burst-len = <4>; +}; -- 2.1.2