From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751123AbcEHTGn (ORCPT ); Sun, 8 May 2016 15:06:43 -0400 Received: from mail.kernel.org ([198.145.29.136]:36805 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751054AbcEHTGi (ORCPT ); Sun, 8 May 2016 15:06:38 -0400 From: Krzysztof Kozlowski To: Kukjin Kim , Krzysztof Kozlowski , Sylwester Nawrocki , Tomasz Figa , Michael Turquette , Stephen Boyd , linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Cc: Javier Martinez Canillas , Krzysztof Kozlowski Subject: [PATCH v2 03/22] ARM: dts: exynos: Add fin_pll node for clock driver Date: Sun, 8 May 2016 21:05:48 +0200 Message-Id: <1462734367-5619-4-git-send-email-krzk@kernel.org> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1462734367-5619-1-git-send-email-krzk@kernel.org> References: <1462734367-5619-1-git-send-email-krzk@kernel.org> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org For consistency between Exynos5410 and Exynos542x/5800 switch to similar way of defining fin_pll/oscclk. Add a node early, before implementing this in driver to preserve bisectability. Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5410-smdk5410.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts b/arch/arm/boot/dts/exynos5410-smdk5410.dts index 0f6429e1b75c..d7d658deeff4 100644 --- a/arch/arm/boot/dts/exynos5410-smdk5410.dts +++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts @@ -31,6 +31,13 @@ #clock-cells = <0>; }; + fixed-rate-clocks { + oscclk { + compatible = "samsung,exynos5420-oscclk"; + clock-frequency = <24000000>; + }; + }; + firmware@02037000 { compatible = "samsung,secure-firmware"; reg = <0x02037000 0x1000>; -- 2.5.0