From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932463AbcEMVrk (ORCPT ); Fri, 13 May 2016 17:47:40 -0400 Received: from mail-pf0-f179.google.com ([209.85.192.179]:33754 "EHLO mail-pf0-f179.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932102AbcEMVrj (ORCPT ); Fri, 13 May 2016 17:47:39 -0400 From: Brian Norris To: Heiko Stuebner Cc: , , , Doug Anderson , Shawn Lin , Brian Norris , Brian Norris Subject: [PATCH v3 1/2] ARM64: dts: rockchip: add sdhci/emmc for rk3399 Date: Fri, 13 May 2016 14:47:24 -0700 Message-Id: <1463176045-109748-1-git-send-email-briannorris@chromium.org> X-Mailer: git-send-email 2.8.0.rc3.226.g39d4020 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add description for the SDHCI v5.1 eMMC controller on rk3399. Fix it to 200 MHz, to support all supported timing modes. Note that 'rockchip,rk3399-sdhci-5.1' is not documented; we presumably have a compliant Arasan controller, but let's have a rockchip property as the canonical backup/precautionary measure. Per Heiko's previous suggestion, let's not clutter the arasan doc with it. Signed-off-by: Brian Norris Reviewed-by: Doug Anderson Reviewed-by: Shawn Lin --- v3: * correct emmc_phy reg length to 0x24 v2: * improved commit message * assign eMMC clock to 200 MHz arch/arm64/boot/dts/rockchip/rk3399.dtsi | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 46f325a143b0..99078f5ebeb9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -215,6 +215,19 @@ status = "disabled"; }; + sdhci: sdhci@fe330000 { + compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; + reg = <0x0 0xfe330000 0x0 0x10000>; + interrupts = ; + clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; + clock-names = "clk_xin", "clk_ahb"; + assigned-clocks = <&cru SCLK_EMMC>; + assigned-clock-rates = <200000000>; + phys = <&emmc_phy>; + phy-names = "phy_arasan"; + status = "disabled"; + }; + usb_host0_ehci: usb@fe380000 { compatible = "generic-ehci"; reg = <0x0 0xfe380000 0x0 0x20000>; @@ -481,8 +494,18 @@ }; grf: syscon@ff770000 { - compatible = "rockchip,rk3399-grf", "syscon"; + compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; reg = <0x0 0xff770000 0x0 0x10000>; + + #address-cells = <1>; + #size-cells = <1>; + + emmc_phy: phy@f780 { + compatible = "rockchip,rk3399-emmc-phy"; + reg = <0xf780 0x24>; + #phy-cells = <0>; + status = "disabled"; + }; }; watchdog@ff840000 { -- 2.8.0.rc3.226.g39d4020