From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932486AbcEQFIB (ORCPT ); Tue, 17 May 2016 01:08:01 -0400 Received: from smtpout.microchip.com ([198.175.253.82]:41902 "EHLO email.microchip.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S932369AbcEQFH6 (ORCPT ); Tue, 17 May 2016 01:07:58 -0400 From: Purna Chandra Mandal To: CC: , Ralf Baechle , Purna Chandra Mandal , Michael Turquette , Stephen Boyd , Subject: [PATCH 02/11] clk: microchip: Initialize SOSC clock rate for PIC32MZDA. Date: Tue, 17 May 2016 10:35:51 +0530 Message-ID: <1463461560-9629-2-git-send-email-purna.mandal@microchip.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1463461560-9629-1-git-send-email-purna.mandal@microchip.com> References: <1463461560-9629-1-git-send-email-purna.mandal@microchip.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Optional SOSC is an external fixed clock running at 32768HZ. So Initialize SOSC rate as per PIC32MZDA datasheet. Signed-off-by: Purna Chandra Mandal --- Note: Please pull this complete series through the MIPS tree. --- drivers/clk/microchip/clk-pic32mzda.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/microchip/clk-pic32mzda.c b/drivers/clk/microchip/clk-pic32mzda.c index 020a29a..210694b 100644 --- a/drivers/clk/microchip/clk-pic32mzda.c +++ b/drivers/clk/microchip/clk-pic32mzda.c @@ -118,6 +118,7 @@ static const struct pic32_sec_osc_data sosc_clk = { .status_reg = 0x1d0, .enable_mask = BIT(1), .status_mask = BIT(4), + .fixed_rate = 32768, .init_data = { .name = "sosc_clk", .parent_names = NULL, -- 1.8.3.1