From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756082AbcETNvP (ORCPT ); Fri, 20 May 2016 09:51:15 -0400 Received: from smtp137.dfw.emailsrvr.com ([67.192.241.137]:42744 "EHLO smtp137.dfw.emailsrvr.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933343AbcETNt7 (ORCPT ); Fri, 20 May 2016 09:49:59 -0400 X-Auth-ID: abbotti@mev.co.uk X-Sender-Id: abbotti@mev.co.uk From: Ian Abbott To: devel@driverdev.osuosl.org Cc: Greg Kroah-Hartman , Ian Abbott , H Hartley Sweeten , linux-kernel@vger.kernel.org Subject: [PATCH 17/20] staging: comedi: drivers: add PLX PCI 9080 DMATHR register values Date: Fri, 20 May 2016 14:49:19 +0100 Message-Id: <1463752162-15181-18-git-send-email-abbotti@mev.co.uk> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1463752162-15181-1-git-send-email-abbotti@mev.co.uk> References: <1463752162-15181-1-git-send-email-abbotti@mev.co.uk> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add macros in "plx9080.h" that define values for the DMATHR register values. Use the prefix `PLX_DMATHR_` for the macros. Make use of the `BIT(x)` and `GENMASK(h,l)` macros to define the values. Signed-off-by: Ian Abbott --- drivers/staging/comedi/drivers/plx9080.h | 41 ++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/drivers/staging/comedi/drivers/plx9080.h b/drivers/staging/comedi/drivers/plx9080.h index 9e76342..50d0b1b 100644 --- a/drivers/staging/comedi/drivers/plx9080.h +++ b/drivers/staging/comedi/drivers/plx9080.h @@ -544,6 +544,47 @@ struct plx_dma_desc { #define PLX_REG_DMATHR 0x00b0 /* + * DMA Threshold constraints: + * (C0PLAF + 1) + (C0PLAE + 1) <= 32 + * (C0LPAF + 1) + (C0LPAE + 1) <= 32 + * (C1PLAF + 1) + (C1PLAE + 1) <= 16 + * (C1LPAF + 1) + (C1LPAE + 1) <= 16 + */ + +/* DMA Channel 0 PCI-to-Local Almost Full (divided by 2, minus 1) */ +#define PLX_DMATHR_C0PLAF(x) (BIT(0) * ((x) & 0xf)) +#define PLX_DMATHR_C0PLAF_MASK GENMASK(3, 0) +#define PLX_DMATHR_C0PLAF_SHIFT 0 +/* DMA Channel 0 Local-to-PCI Almost Empty (divided by 2, minus 1) */ +#define PLX_DMATHR_C0LPAE(x) (BIT(4) * ((x) & 0xf)) +#define PLX_DMATHR_C0LPAE_MASK GENMASK(7, 4) +#define PLX_DMATHR_C0LPAE_SHIFT 4 +/* DMA Channel 0 Local-to-PCI Almost Full (divided by 2, minus 1) */ +#define PLX_DMATHR_C0LPAF(x) (BIT(8) * ((x) & 0xf)) +#define PLX_DMATHR_C0LPAF_MASK GENMASK(11, 8) +#define PLX_DMATHR_C0LPAF_SHIFT 8 +/* DMA Channel 0 PCI-to-Local Almost Empty (divided by 2, minus 1) */ +#define PLX_DMATHR_C0PLAE(x) (BIT(12) * ((x) & 0xf)) +#define PLX_DMATHR_C0PLAE_MASK GENMASK(15, 12) +#define PLX_DMATHR_C0PLAE_SHIFT 12 +/* DMA Channel 1 PCI-to-Local Almost Full (divided by 2, minus 1) */ +#define PLX_DMATHR_C1PLAF(x) (BIT(16) * ((x) & 0xf)) +#define PLX_DMATHR_C1PLAF_MASK GENMASK(19, 16) +#define PLX_DMATHR_C1PLAF_SHIFT 16 +/* DMA Channel 1 Local-to-PCI Almost Empty (divided by 2, minus 1) */ +#define PLX_DMATHR_C1LPAE(x) (BIT(20) * ((x) & 0xf)) +#define PLX_DMATHR_C1LPAE_MASK GENMASK(23, 20) +#define PLX_DMATHR_C1LPAE_SHIFT 20 +/* DMA Channel 1 Local-to-PCI Almost Full (divided by 2, minus 1) */ +#define PLX_DMATHR_C1LPAF(x) (BIT(24) * ((x) & 0xf)) +#define PLX_DMATHR_C1LPAF_MASK GENMASK(27, 24) +#define PLX_DMATHR_C1LPAF_SHIFT 24 +/* DMA Channel 1 PCI-to-Local Almost Empty (divided by 2, minus 1) */ +#define PLX_DMATHR_C1PLAE(x) (BIT(28) * ((x) & 0xf)) +#define PLX_DMATHR_C1PLAE_MASK GENMASK(31, 28) +#define PLX_DMATHR_C1PLAE_SHIFT 28 + +/* * Messaging Queue Registers OPLFIS, OPLFIM, IQP, OQP, MQCR, QBAR, IFHPR, * IFTPR, IPHPR, IPTPR, OFHPR, OFTPR, OPHPR, OPTPR, and QSR have been omitted. * They are used by the I2O feature. (IQP and OQP occupy the usual offsets of -- 2.8.1