* [PATCH 00/20] staging: comedi: re-do drivers/plx9080.h
@ 2016-05-20 13:49 Ian Abbott
2016-05-20 13:49 ` [PATCH 01/20] staging: comedi: plx9080.h: correct LRNG_IO_MASK and LMAP_IO_MASK Ian Abbott
` (19 more replies)
0 siblings, 20 replies; 28+ messages in thread
From: Ian Abbott @ 2016-05-20 13:49 UTC (permalink / raw)
To: devel; +Cc: Greg Kroah-Hartman, Ian Abbott, H Hartley Sweeten, linux-kernel
Re-do "drivers/staging/comedi/drivers/plx9080.h". It mostly contains
defines for register offsets and values for the PLX PCI 9080 PCI
interface chip. To make it easier to follow, base the macro names for
register offsets on the register names from the PLX PCI 9080 data book.
Base the macro names used to construct register values on the names of
the corresponding registers. Make use of the `BIT(x)` and
`GENMASK(h,l)` macros to define register values and masks. Add
kerneldoc comments for structs and inline functions. Add `#include`
directives to declare things used within the code.
01) staging: comedi: plx9080.h: correct LRNG_IO_MASK and LMAP_IO_MASK
02) staging: comedi: plx9080.h: remove Power-Up Test Suite stuff
03) staging: comedi: drivers: rename PLX PCI 9080 register offsets
04) staging: comedi: drivers: re-do macros for PLX PCI 9080 LASxRR
values
05) staging: comedi: drivers: re-do macros for PLX PCI 9080 LASxBA
values
06) staging: comedi: drivers: re-do PLX PCI 9080 MARBR register values
07) staging: comedi: drivers: re-do PLX PCI 9080 BIGEND register values
08) staging: comedi: drivers: re-do PLX PCI 9080 LBRDx register values
09) staging: comedi: drivers: re-do PLX PCI 9080 DMPBAM register values
10) staging: comedi: drivers: re-do PLX PCI 9080 DMCFGA register values
11) staging: comedi: drivers: re-do PLX PCI 9080 INTCSR register values
12) staging: comedi: drivers: re-do PLX PCI 9080 CNTRL register values
13) staging: comedi: plx9080.h: add hard-coded PCIHIDR register value
14) staging: comedi: drivers: re-do PLX PCI 9080 DMAMODEx register
values
15) staging: comedi: drivers: re-do PLX PCI 9080 DMADPRx register values
16) staging: comedi: drivers: re-do PLX PCI 9080 DMACSRx register values
17) staging: comedi: drivers: add PLX PCI 9080 DMATHR register values
18) staging: comedi: plx9080.h: tidy up some comments
19) staging: comedi: plx9080.h: Add kerneldoc comments
20) staging: comedi: plx9080.h: include headers for declarations
drivers/staging/comedi/drivers/cb_pcidas64.c | 209 +++---
drivers/staging/comedi/drivers/gsc_hpdi.c | 87 ++-
drivers/staging/comedi/drivers/plx9080.h | 957 ++++++++++++++++-----------
drivers/staging/comedi/drivers/rtd520.c | 5 +-
4 files changed, 726 insertions(+), 532 deletions(-)
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 01/20] staging: comedi: plx9080.h: correct LRNG_IO_MASK and LMAP_IO_MASK
2016-05-20 13:49 [PATCH 00/20] staging: comedi: re-do drivers/plx9080.h Ian Abbott
@ 2016-05-20 13:49 ` Ian Abbott
2016-05-20 13:49 ` [PATCH 02/20] staging: comedi: plx9080.h: remove Power-Up Test Suite stuff Ian Abbott
` (18 subsequent siblings)
19 siblings, 0 replies; 28+ messages in thread
From: Ian Abbott @ 2016-05-20 13:49 UTC (permalink / raw)
To: devel; +Cc: Greg Kroah-Hartman, Ian Abbott, H Hartley Sweeten, linux-kernel
For the PLX local address space range registers, LAS0RR and LAS1RR, bit
0 indicates whether the local address space will be mapped to memory
space or I/O space. If mapped to I/O space, bit 1 must be set to 0, and
bits 31 to 2 form the address decoding mask, which should be -2^N mod
2^32 for a range of length 2^N.
The `LRNG_IO_MASK` macro is supposed to specify the address decoding
bits for I/O space. It currently has the value `0xfffffffa`, but should
be `0xfffffffc`, or possibly `0xfffffffe` (it doesn't really matter,
since bit 1 is required to be set to 0). Change it to `0xfffffffc`.
Similarly, for the PLX local address space local base address (remap)
registers, LAS0BA and LAS1BA, bits 31 to 2, masked with the
corresponding "range" register form the local base address for the local
address space. The `LMAP_IO_MASK` macro is supposed to mask the valid
bits for I/O space. Change its value from `0xfffffffa` to `0xfffffffc`
to match `LRNG_IO_MASK`.
Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
---
drivers/staging/comedi/drivers/plx9080.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/staging/comedi/drivers/plx9080.h b/drivers/staging/comedi/drivers/plx9080.h
index 8d1aee00b1..7d6311c 100644
--- a/drivers/staging/comedi/drivers/plx9080.h
+++ b/drivers/staging/comedi/drivers/plx9080.h
@@ -60,7 +60,7 @@ struct plx_dma_desc {
/* bits that specify range for memory io */
#define LRNG_MEM_MASK 0xfffffff0
/* bits that specify range for normal io */
-#define LRNG_IO_MASK 0xfffffffa
+#define LRNG_IO_MASK 0xfffffffc
/* L, Local Addr Space 0 Remap Register */
#define PLX_LAS0MAP_REG 0x0004
/* L, Local Addr Space 1 Remap Register */
@@ -69,7 +69,7 @@ struct plx_dma_desc {
/* bits that specify decode for memory io */
#define LMAP_MEM_MASK 0xfffffff0
/* bits that specify decode bits for normal io */
-#define LMAP_IO_MASK 0xfffffffa
+#define LMAP_IO_MASK 0xfffffffc
/*
* Mode/Arbitration Register.
--
2.8.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 02/20] staging: comedi: plx9080.h: remove Power-Up Test Suite stuff
2016-05-20 13:49 [PATCH 00/20] staging: comedi: re-do drivers/plx9080.h Ian Abbott
2016-05-20 13:49 ` [PATCH 01/20] staging: comedi: plx9080.h: correct LRNG_IO_MASK and LMAP_IO_MASK Ian Abbott
@ 2016-05-20 13:49 ` Ian Abbott
2016-05-20 13:49 ` [PATCH 03/20] staging: comedi: drivers: rename PLX PCI 9080 register offsets Ian Abbott
` (17 subsequent siblings)
19 siblings, 0 replies; 28+ messages in thread
From: Ian Abbott @ 2016-05-20 13:49 UTC (permalink / raw)
To: devel; +Cc: Greg Kroah-Hartman, Ian Abbott, H Hartley Sweeten, linux-kernel
The defines related to the Power-Up Test Suite (PUTS) are just cruft that
has nothing to do with the PLX PCI-9080 chip. They seem to have been
inherited from "drivers/net/plx9060.h" in the kernel 2.2.16 sources for
use by the "wanxl" driver. Remove them.
Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
---
drivers/staging/comedi/drivers/plx9080.h | 120 -------------------------------
1 file changed, 120 deletions(-)
diff --git a/drivers/staging/comedi/drivers/plx9080.h b/drivers/staging/comedi/drivers/plx9080.h
index 7d6311c..3759a19 100644
--- a/drivers/staging/comedi/drivers/plx9080.h
+++ b/drivers/staging/comedi/drivers/plx9080.h
@@ -294,126 +294,6 @@ enum bigend_bits {
#define PLX_PREFETCH 32
-/*
- * The PCI Interface, via the PCI-9060 Chip, has up to eight (8) Mailbox
- * Registers. The PUTS (Power-Up Test Suite) handles the board-side
- * interface/interaction using the first 4 registers. Specifications for
- * the use of the full PUTS' command and status interface is contained
- * within a separate SBE PUTS Manual. The Host-Side Device Driver only
- * uses a subset of the full PUTS interface.
- */
-
-/*****************************************/
-/*** MAILBOX #(-1) - MEM ACCESS STS ***/
-/*****************************************/
-
-#define MBX_STS_VALID 0x57584744 /* 'WXGD' */
-#define MBX_STS_DILAV 0x44475857 /* swapped = 'DGXW' */
-
-/*****************************************/
-/*** MAILBOX #0 - PUTS STATUS ***/
-/*****************************************/
-
-#define MBX_STS_MASK 0x000000ff /* PUTS Status Register bits */
-#define MBX_STS_TMASK 0x0000000f /* register bits for TEST number */
-
-#define MBX_STS_PCIRESET 0x00000100 /* Host issued PCI reset request */
-#define MBX_STS_BUSY 0x00000080 /* PUTS is in progress */
-#define MBX_STS_ERROR 0x00000040 /* PUTS has failed */
-/*
- * Undefined -> status in transition. We are in process of changing bits;
- * we SET Error bit before RESET of Busy bit
- */
-#define MBX_STS_RESERVED 0x000000c0
-
-#define MBX_RESERVED_5 0x00000020 /* FYI: reserved/unused bit */
-#define MBX_RESERVED_4 0x00000010 /* FYI: reserved/unused bit */
-
-/******************************************/
-/*** MAILBOX #1 - PUTS COMMANDS ***/
-/******************************************/
-
-/*
- * Any attempt to execute an unimplement command results in the PUTS
- * interface executing a NOOP and continuing as if the offending command
- * completed normally. Note: this supplies a simple method to interrogate
- * mailbox command processing functionality.
- */
-
-#define MBX_CMD_MASK 0xffff0000 /* PUTS Command Register bits */
-
-#define MBX_CMD_ABORTJ 0x85000000 /* abort and jump */
-#define MBX_CMD_RESETP 0x86000000 /* reset and pause at start */
-#define MBX_CMD_PAUSE 0x87000000 /* pause immediately */
-#define MBX_CMD_PAUSEC 0x88000000 /* pause on completion */
-#define MBX_CMD_RESUME 0x89000000 /* resume operation */
-#define MBX_CMD_STEP 0x8a000000 /* single step tests */
-
-#define MBX_CMD_BSWAP 0x8c000000 /* identify byte swap scheme */
-#define MBX_CMD_BSWAP_0 0x8c000000 /* use scheme 0 */
-#define MBX_CMD_BSWAP_1 0x8c000001 /* use scheme 1 */
-
-/* setup host memory access window size */
-#define MBX_CMD_SETHMS 0x8d000000
-/* setup host memory access base address */
-#define MBX_CMD_SETHBA 0x8e000000
-/* perform memory setup and continue (IE. Done) */
-#define MBX_CMD_MGO 0x8f000000
-#define MBX_CMD_NOOP 0xFF000000 /* dummy, illegal command */
-
-/*****************************************/
-/*** MAILBOX #2 - MEMORY SIZE ***/
-/*****************************************/
-
-#define MBX_MEMSZ_MASK 0xffff0000 /* PUTS Memory Size Register bits */
-
-#define MBX_MEMSZ_128KB 0x00020000 /* 128 kilobyte board */
-#define MBX_MEMSZ_256KB 0x00040000 /* 256 kilobyte board */
-#define MBX_MEMSZ_512KB 0x00080000 /* 512 kilobyte board */
-#define MBX_MEMSZ_1MB 0x00100000 /* 1 megabyte board */
-#define MBX_MEMSZ_2MB 0x00200000 /* 2 megabyte board */
-#define MBX_MEMSZ_4MB 0x00400000 /* 4 megabyte board */
-#define MBX_MEMSZ_8MB 0x00800000 /* 8 megabyte board */
-#define MBX_MEMSZ_16MB 0x01000000 /* 16 megabyte board */
-
-/***************************************/
-/*** MAILBOX #2 - BOARD TYPE ***/
-/***************************************/
-
-#define MBX_BTYPE_MASK 0x0000ffff /* PUTS Board Type Register */
-/* PUTS Board Family Register */
-#define MBX_BTYPE_FAMILY_MASK 0x0000ff00
-#define MBX_BTYPE_SUBTYPE_MASK 0x000000ff /* PUTS Board Subtype */
-
-#define MBX_BTYPE_PLX9060 0x00000100 /* PLX family type */
-#define MBX_BTYPE_PLX9080 0x00000300 /* PLX wanXL100s family type */
-
-#define MBX_BTYPE_WANXL_4 0x00000104 /* wanXL400, 4-port */
-#define MBX_BTYPE_WANXL_2 0x00000102 /* wanXL200, 2-port */
-#define MBX_BTYPE_WANXL_1s 0x00000301 /* wanXL100s, 1-port */
-#define MBX_BTYPE_WANXL_1t 0x00000401 /* wanXL100T1, 1-port */
-
-/*****************************************/
-/*** MAILBOX #3 - SHMQ MAILBOX ***/
-/*****************************************/
-
-#define MBX_SMBX_MASK 0x000000ff /* PUTS SHMQ Mailbox bits */
-
-/***************************************/
-/*** GENERIC HOST-SIDE DRIVER ***/
-/***************************************/
-
-#define MBX_ERR 0
-#define MBX_OK 1
-
-/* mailbox check routine - type of testing */
-#define MBXCHK_STS 0x00 /* check for PUTS status */
-#define MBXCHK_NOWAIT 0x01 /* dont care about PUTS status */
-
-/* system allocates this many bytes for address mapping mailbox space */
-#define MBX_ADDR_SPACE_360 0x80 /* wanXL100s/200/400 */
-#define MBX_ADDR_MASK_360 (MBX_ADDR_SPACE_360 - 1)
-
static inline int plx9080_abort_dma(void __iomem *iobase, unsigned int channel)
{
void __iomem *dma_cs_addr;
--
2.8.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 03/20] staging: comedi: drivers: rename PLX PCI 9080 register offsets
2016-05-20 13:49 [PATCH 00/20] staging: comedi: re-do drivers/plx9080.h Ian Abbott
2016-05-20 13:49 ` [PATCH 01/20] staging: comedi: plx9080.h: correct LRNG_IO_MASK and LMAP_IO_MASK Ian Abbott
2016-05-20 13:49 ` [PATCH 02/20] staging: comedi: plx9080.h: remove Power-Up Test Suite stuff Ian Abbott
@ 2016-05-20 13:49 ` Ian Abbott
2016-05-20 16:21 ` Hartley Sweeten
2016-05-20 13:49 ` [PATCH 04/20] staging: comedi: drivers: re-do macros for PLX PCI 9080 LASxRR values Ian Abbott
` (16 subsequent siblings)
19 siblings, 1 reply; 28+ messages in thread
From: Ian Abbott @ 2016-05-20 13:49 UTC (permalink / raw)
To: devel; +Cc: Greg Kroah-Hartman, Ian Abbott, H Hartley Sweeten, linux-kernel
Rename the macros in "plx9080.h" that define the offsets of registers,
following the pattern `PLX_REG_<NAME>`, where `<NAME>` is the register
name from the PLX PCI 9080 Data Book.
Add defines for the "Mailbox" registers, and add parameterized macros
for the mailbox registers and the DMA control registers. Make use of
the parameterized versions of the macros where it seems appropriate.
The registers for supporting the I2O (Intelligent Input/Output) feature
are largely left undefined, just defining enough to allow the I2O
feature to be disabled.
Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
---
drivers/staging/comedi/drivers/cb_pcidas64.c | 96 ++++++---------
drivers/staging/comedi/drivers/gsc_hpdi.c | 39 +++---
drivers/staging/comedi/drivers/plx9080.h | 177 +++++++++++++++++++--------
drivers/staging/comedi/drivers/rtd520.c | 4 +-
4 files changed, 185 insertions(+), 131 deletions(-)
diff --git a/drivers/staging/comedi/drivers/cb_pcidas64.c b/drivers/staging/comedi/drivers/cb_pcidas64.c
index c773b8c..d9468db 100644
--- a/drivers/staging/comedi/drivers/cb_pcidas64.c
+++ b/drivers/staging/comedi/drivers/cb_pcidas64.c
@@ -1238,7 +1238,7 @@ static void disable_plx_interrupts(struct comedi_device *dev)
devpriv->plx_intcsr_bits = 0;
writel(devpriv->plx_intcsr_bits,
- devpriv->plx9080_iobase + PLX_INTRCS_REG);
+ devpriv->plx9080_iobase + PLX_REG_INTCSR);
}
static void disable_ai_interrupts(struct comedi_device *dev)
@@ -1291,14 +1291,14 @@ static void init_plx9080(struct comedi_device *dev)
void __iomem *plx_iobase = devpriv->plx9080_iobase;
devpriv->plx_control_bits =
- readl(devpriv->plx9080_iobase + PLX_CONTROL_REG);
+ readl(devpriv->plx9080_iobase + PLX_REG_CNTRL);
#ifdef __BIG_ENDIAN
bits = BIGEND_DMA0 | BIGEND_DMA1;
#else
bits = 0;
#endif
- writel(bits, devpriv->plx9080_iobase + PLX_BIGEND_REG);
+ writel(bits, devpriv->plx9080_iobase + PLX_REG_BIGEND);
disable_plx_interrupts(dev);
@@ -1330,16 +1330,16 @@ static void init_plx9080(struct comedi_device *dev)
bits |= PLX_LOCAL_BUS_32_WIDE_BITS;
else /* localspace0 bus is 16 bits wide */
bits |= PLX_LOCAL_BUS_16_WIDE_BITS;
- writel(bits, plx_iobase + PLX_DMA1_MODE_REG);
+ writel(bits, plx_iobase + PLX_REG_DMAMODE1);
if (ao_cmd_is_supported(board))
- writel(bits, plx_iobase + PLX_DMA0_MODE_REG);
+ writel(bits, plx_iobase + PLX_REG_DMAMODE0);
/* enable interrupts on plx 9080 */
devpriv->plx_intcsr_bits |=
ICS_AERR | ICS_PERR | ICS_PIE | ICS_PLIE | ICS_PAIE | ICS_LIE |
ICS_DMA0_E | ICS_DMA1_E;
writel(devpriv->plx_intcsr_bits,
- devpriv->plx9080_iobase + PLX_INTRCS_REG);
+ devpriv->plx9080_iobase + PLX_REG_INTCSR);
}
static void disable_ai_pacing(struct comedi_device *dev)
@@ -1615,7 +1615,7 @@ static void i2c_set_sda(struct comedi_device *dev, int state)
struct pcidas64_private *devpriv = dev->private;
static const int data_bit = CTL_EE_W;
void __iomem *plx_control_addr = devpriv->plx9080_iobase +
- PLX_CONTROL_REG;
+ PLX_REG_CNTRL;
if (state) {
/* set data line high */
@@ -1636,7 +1636,7 @@ static void i2c_set_scl(struct comedi_device *dev, int state)
struct pcidas64_private *devpriv = dev->private;
static const int clock_bit = CTL_USERO;
void __iomem *plx_control_addr = devpriv->plx9080_iobase +
- PLX_CONTROL_REG;
+ PLX_REG_CNTRL;
if (state) {
/* set clock line high */
@@ -2367,14 +2367,8 @@ static inline void dma_start_sync(struct comedi_device *dev,
/* spinlock for plx dma control/status reg */
spin_lock_irqsave(&dev->spinlock, flags);
- if (channel)
- writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT |
- PLX_CLEAR_DMA_INTR_BIT,
- devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
- else
- writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT |
- PLX_CLEAR_DMA_INTR_BIT,
- devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
+ writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT | PLX_CLEAR_DMA_INTR_BIT,
+ devpriv->plx9080_iobase + PLX_REG_DMACSR(channel));
spin_unlock_irqrestore(&dev->spinlock, flags);
}
@@ -2552,21 +2546,17 @@ static inline void load_first_dma_descriptor(struct comedi_device *dev,
* block. Initializing them to zero seems to fix the problem.
*/
if (dma_channel) {
- writel(0,
- devpriv->plx9080_iobase + PLX_DMA1_TRANSFER_SIZE_REG);
- writel(0, devpriv->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG);
- writel(0,
- devpriv->plx9080_iobase + PLX_DMA1_LOCAL_ADDRESS_REG);
+ writel(0, devpriv->plx9080_iobase + PLX_REG_DMASIZ1);
+ writel(0, devpriv->plx9080_iobase + PLX_REG_DMAPADR1);
+ writel(0, devpriv->plx9080_iobase + PLX_REG_DMALADR1);
writel(descriptor_bits,
- devpriv->plx9080_iobase + PLX_DMA1_DESCRIPTOR_REG);
+ devpriv->plx9080_iobase + PLX_REG_DMADPR1);
} else {
- writel(0,
- devpriv->plx9080_iobase + PLX_DMA0_TRANSFER_SIZE_REG);
- writel(0, devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
- writel(0,
- devpriv->plx9080_iobase + PLX_DMA0_LOCAL_ADDRESS_REG);
+ writel(0, devpriv->plx9080_iobase + PLX_REG_DMASIZ0);
+ writel(0, devpriv->plx9080_iobase + PLX_REG_DMAPADR0);
+ writel(0, devpriv->plx9080_iobase + PLX_REG_DMALADR0);
writel(descriptor_bits,
- devpriv->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
+ devpriv->plx9080_iobase + PLX_REG_DMADPR0);
}
}
@@ -2803,12 +2793,7 @@ static void drain_dma_buffers(struct comedi_device *dev, unsigned int channel)
int num_samples = 0;
void __iomem *pci_addr_reg;
- if (channel)
- pci_addr_reg =
- devpriv->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG;
- else
- pci_addr_reg =
- devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
+ pci_addr_reg = devpriv->plx9080_iobase + PLX_REG_DMAPADR(channel);
/* loop until we have read all the full buffers */
for (j = 0, next_transfer_addr = readl(pci_addr_reg);
@@ -2850,10 +2835,10 @@ static void handle_ai_interrupt(struct comedi_device *dev,
}
/* spin lock makes sure no one else changes plx dma control reg */
spin_lock_irqsave(&dev->spinlock, flags);
- dma1_status = readb(devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
+ dma1_status = readb(devpriv->plx9080_iobase + PLX_REG_DMACSR1);
if (plx_status & ICS_DMA1_A) { /* dma chan 1 interrupt */
writeb((dma1_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
- devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
+ devpriv->plx9080_iobase + PLX_REG_DMACSR1);
if (dma1_status & PLX_DMA_EN_BIT)
drain_dma_buffers(dev, 1);
@@ -2902,12 +2887,12 @@ static int last_ao_dma_load_completed(struct comedi_device *dev)
unsigned short dma_status;
buffer_index = prev_ao_dma_index(dev);
- dma_status = readb(devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
+ dma_status = readb(devpriv->plx9080_iobase + PLX_REG_DMACSR0);
if ((dma_status & PLX_DMA_DONE_BIT) == 0)
return 0;
transfer_address =
- readl(devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
+ readl(devpriv->plx9080_iobase + PLX_REG_DMAPADR0);
if (transfer_address != devpriv->ao_buffer_bus_addr[buffer_index])
return 0;
@@ -2931,8 +2916,7 @@ static void restart_ao_dma(struct comedi_device *dev)
struct pcidas64_private *devpriv = dev->private;
unsigned int dma_desc_bits;
- dma_desc_bits =
- readl(devpriv->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
+ dma_desc_bits = readl(devpriv->plx9080_iobase + PLX_REG_DMADPR0);
dma_desc_bits &= ~PLX_END_OF_CHAIN_BIT;
load_first_dma_descriptor(dev, 0, dma_desc_bits);
@@ -2994,8 +2978,7 @@ static void load_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd)
struct pcidas64_private *devpriv = dev->private;
unsigned int num_bytes;
unsigned int next_transfer_addr;
- void __iomem *pci_addr_reg =
- devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
+ void __iomem *pci_addr_reg = devpriv->plx9080_iobase + PLX_REG_DMAPADR0;
unsigned int buffer_index;
do {
@@ -3030,15 +3013,16 @@ static void handle_ao_interrupt(struct comedi_device *dev,
/* spin lock makes sure no one else changes plx dma control reg */
spin_lock_irqsave(&dev->spinlock, flags);
- dma0_status = readb(devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
+ dma0_status = readb(devpriv->plx9080_iobase + PLX_REG_DMACSR0);
if (plx_status & ICS_DMA0_A) { /* dma chan 0 interrupt */
if ((dma0_status & PLX_DMA_EN_BIT) &&
- !(dma0_status & PLX_DMA_DONE_BIT))
+ !(dma0_status & PLX_DMA_DONE_BIT)) {
writeb(PLX_DMA_EN_BIT | PLX_CLEAR_DMA_INTR_BIT,
- devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
- else
+ devpriv->plx9080_iobase + PLX_REG_DMACSR0);
+ } else {
writeb(PLX_CLEAR_DMA_INTR_BIT,
- devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
+ devpriv->plx9080_iobase + PLX_REG_DMACSR0);
+ }
spin_unlock_irqrestore(&dev->spinlock, flags);
if (dma0_status & PLX_DMA_EN_BIT) {
load_ao_dma(dev, cmd);
@@ -3069,7 +3053,7 @@ static irqreturn_t handle_interrupt(int irq, void *d)
uint32_t plx_status;
uint32_t plx_bits;
- plx_status = readl(devpriv->plx9080_iobase + PLX_INTRCS_REG);
+ plx_status = readl(devpriv->plx9080_iobase + PLX_REG_INTCSR);
status = readw(devpriv->main_iobase + HW_STATUS_REG);
/*
@@ -3085,8 +3069,8 @@ static irqreturn_t handle_interrupt(int irq, void *d)
/* clear possible plx9080 interrupt sources */
if (plx_status & ICS_LDIA) { /* clear local doorbell interrupt */
- plx_bits = readl(devpriv->plx9080_iobase + PLX_DBR_OUT_REG);
- writel(plx_bits, devpriv->plx9080_iobase + PLX_DBR_OUT_REG);
+ plx_bits = readl(devpriv->plx9080_iobase + PLX_REG_L2PDBELL);
+ writel(plx_bits, devpriv->plx9080_iobase + PLX_REG_L2PDBELL);
}
return IRQ_HANDLED;
@@ -3725,7 +3709,7 @@ static uint16_t read_eeprom(struct comedi_device *dev, uint8_t address)
unsigned int bitstream = (read_command << 8) | address;
unsigned int bit;
void __iomem * const plx_control_addr =
- devpriv->plx9080_iobase + PLX_CONTROL_REG;
+ devpriv->plx9080_iobase + PLX_REG_CNTRL;
uint16_t value;
static const int value_length = 16;
static const int eeprom_udelay = 1;
@@ -3962,7 +3946,7 @@ static int setup_subdevices(struct comedi_device *dev)
/* serial EEPROM, if present */
s = &dev->subdevices[8];
- if (readl(devpriv->plx9080_iobase + PLX_CONTROL_REG) & CTL_EECHK) {
+ if (readl(devpriv->plx9080_iobase + PLX_REG_CNTRL) & CTL_EECHK) {
s->type = COMEDI_SUBD_MEMORY;
s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
s->n_chan = 128;
@@ -4019,15 +4003,15 @@ static int auto_attach(struct comedi_device *dev,
}
/* figure out what local addresses are */
- local_range = readl(devpriv->plx9080_iobase + PLX_LAS0RNG_REG) &
+ local_range = readl(devpriv->plx9080_iobase + PLX_REG_LAS0RR) &
LRNG_MEM_MASK;
- local_decode = readl(devpriv->plx9080_iobase + PLX_LAS0MAP_REG) &
+ local_decode = readl(devpriv->plx9080_iobase + PLX_REG_LAS0BA) &
local_range & LMAP_MEM_MASK;
devpriv->local0_iobase = ((uint32_t)devpriv->main_phys_iobase &
~local_range) | local_decode;
- local_range = readl(devpriv->plx9080_iobase + PLX_LAS1RNG_REG) &
+ local_range = readl(devpriv->plx9080_iobase + PLX_REG_LAS1RR) &
LRNG_MEM_MASK;
- local_decode = readl(devpriv->plx9080_iobase + PLX_LAS1MAP_REG) &
+ local_decode = readl(devpriv->plx9080_iobase + PLX_REG_LAS1BA) &
local_range & LMAP_MEM_MASK;
devpriv->local1_iobase = ((uint32_t)devpriv->dio_counter_phys_iobase &
~local_range) | local_decode;
diff --git a/drivers/staging/comedi/drivers/gsc_hpdi.c b/drivers/staging/comedi/drivers/gsc_hpdi.c
index 63b5cbc..e2831e1 100644
--- a/drivers/staging/comedi/drivers/gsc_hpdi.c
+++ b/drivers/staging/comedi/drivers/gsc_hpdi.c
@@ -158,10 +158,7 @@ static void gsc_hpdi_drain_dma(struct comedi_device *dev, unsigned int channel)
unsigned int size;
unsigned int next;
- if (channel)
- next = readl(devpriv->plx9080_mmio + PLX_DMA1_PCI_ADDRESS_REG);
- else
- next = readl(devpriv->plx9080_mmio + PLX_DMA0_PCI_ADDRESS_REG);
+ next = readl(devpriv->plx9080_mmio + PLX_REG_DMAPADR(channel));
idx = devpriv->dma_desc_index;
start = le32_to_cpu(devpriv->dma_desc[idx].pci_start_addr);
@@ -201,7 +198,7 @@ static irqreturn_t gsc_hpdi_interrupt(int irq, void *d)
if (!dev->attached)
return IRQ_NONE;
- plx_status = readl(devpriv->plx9080_mmio + PLX_INTRCS_REG);
+ plx_status = readl(devpriv->plx9080_mmio + PLX_REG_INTCSR);
if ((plx_status & (ICS_DMA0_A | ICS_DMA1_A | ICS_LIA)) == 0)
return IRQ_NONE;
@@ -213,11 +210,11 @@ static irqreturn_t gsc_hpdi_interrupt(int irq, void *d)
/* spin lock makes sure no one else changes plx dma control reg */
spin_lock_irqsave(&dev->spinlock, flags);
- dma0_status = readb(devpriv->plx9080_mmio + PLX_DMA0_CS_REG);
+ dma0_status = readb(devpriv->plx9080_mmio + PLX_REG_DMACSR0);
if (plx_status & ICS_DMA0_A) {
/* dma chan 0 interrupt */
writeb((dma0_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
- devpriv->plx9080_mmio + PLX_DMA0_CS_REG);
+ devpriv->plx9080_mmio + PLX_REG_DMACSR0);
if (dma0_status & PLX_DMA_EN_BIT)
gsc_hpdi_drain_dma(dev, 0);
@@ -226,19 +223,19 @@ static irqreturn_t gsc_hpdi_interrupt(int irq, void *d)
/* spin lock makes sure no one else changes plx dma control reg */
spin_lock_irqsave(&dev->spinlock, flags);
- dma1_status = readb(devpriv->plx9080_mmio + PLX_DMA1_CS_REG);
+ dma1_status = readb(devpriv->plx9080_mmio + PLX_REG_DMACSR1);
if (plx_status & ICS_DMA1_A) {
/* XXX */ /* dma chan 1 interrupt */
writeb((dma1_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
- devpriv->plx9080_mmio + PLX_DMA1_CS_REG);
+ devpriv->plx9080_mmio + PLX_REG_DMACSR1);
}
spin_unlock_irqrestore(&dev->spinlock, flags);
/* clear possible plx9080 interrupt sources */
if (plx_status & ICS_LDIA) {
/* clear local doorbell interrupt */
- plx_bits = readl(devpriv->plx9080_mmio + PLX_DBR_OUT_REG);
- writel(plx_bits, devpriv->plx9080_mmio + PLX_DBR_OUT_REG);
+ plx_bits = readl(devpriv->plx9080_mmio + PLX_REG_L2PDBELL);
+ writel(plx_bits, devpriv->plx9080_mmio + PLX_REG_L2PDBELL);
}
if (hpdi_board_status & RX_OVERRUN_BIT) {
@@ -307,19 +304,19 @@ static int gsc_hpdi_cmd(struct comedi_device *dev,
* occasionally cause problems with transfer of first dma
* block. Initializing them to zero seems to fix the problem.
*/
- writel(0, devpriv->plx9080_mmio + PLX_DMA0_TRANSFER_SIZE_REG);
- writel(0, devpriv->plx9080_mmio + PLX_DMA0_PCI_ADDRESS_REG);
- writel(0, devpriv->plx9080_mmio + PLX_DMA0_LOCAL_ADDRESS_REG);
+ writel(0, devpriv->plx9080_mmio + PLX_REG_DMASIZ0);
+ writel(0, devpriv->plx9080_mmio + PLX_REG_DMAPADR0);
+ writel(0, devpriv->plx9080_mmio + PLX_REG_DMALADR0);
/* give location of first dma descriptor */
bits = devpriv->dma_desc_phys_addr | PLX_DESC_IN_PCI_BIT |
PLX_INTR_TERM_COUNT | PLX_XFER_LOCAL_TO_PCI;
- writel(bits, devpriv->plx9080_mmio + PLX_DMA0_DESCRIPTOR_REG);
+ writel(bits, devpriv->plx9080_mmio + PLX_REG_DMADPR0);
/* enable dma transfer */
spin_lock_irqsave(&dev->spinlock, flags);
writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT | PLX_CLEAR_DMA_INTR_BIT,
- devpriv->plx9080_mmio + PLX_DMA0_CS_REG);
+ devpriv->plx9080_mmio + PLX_REG_DMACSR0);
spin_unlock_irqrestore(&dev->spinlock, flags);
if (cmd->stop_src == TRIG_COUNT)
@@ -538,7 +535,7 @@ static int gsc_hpdi_init(struct comedi_device *dev)
plx_intcsr_bits =
ICS_AERR | ICS_PERR | ICS_PIE | ICS_PLIE | ICS_PAIE | ICS_LIE |
ICS_DMA0_E;
- writel(plx_intcsr_bits, devpriv->plx9080_mmio + PLX_INTRCS_REG);
+ writel(plx_intcsr_bits, devpriv->plx9080_mmio + PLX_REG_INTCSR);
return 0;
}
@@ -554,9 +551,9 @@ static void gsc_hpdi_init_plx9080(struct comedi_device *dev)
#else
bits = 0;
#endif
- writel(bits, devpriv->plx9080_mmio + PLX_BIGEND_REG);
+ writel(bits, devpriv->plx9080_mmio + PLX_REG_BIGEND);
- writel(0, devpriv->plx9080_mmio + PLX_INTRCS_REG);
+ writel(0, devpriv->plx9080_mmio + PLX_REG_INTCSR);
gsc_hpdi_abort_dma(dev, 0);
gsc_hpdi_abort_dma(dev, 1);
@@ -584,7 +581,7 @@ static void gsc_hpdi_init_plx9080(struct comedi_device *dev)
/* enable local burst mode */
bits |= PLX_DMA_LOCAL_BURST_EN_BIT;
bits |= PLX_LOCAL_BUS_32_WIDE_BITS;
- writel(bits, plx_iobase + PLX_DMA0_MODE_REG);
+ writel(bits, plx_iobase + PLX_REG_DMAMODE0);
}
static int gsc_hpdi_auto_attach(struct comedi_device *dev,
@@ -680,7 +677,7 @@ static void gsc_hpdi_detach(struct comedi_device *dev)
free_irq(dev->irq, dev);
if (devpriv) {
if (devpriv->plx9080_mmio) {
- writel(0, devpriv->plx9080_mmio + PLX_INTRCS_REG);
+ writel(0, devpriv->plx9080_mmio + PLX_REG_INTCSR);
iounmap(devpriv->plx9080_mmio);
}
if (dev->mmio)
diff --git a/drivers/staging/comedi/drivers/plx9080.h b/drivers/staging/comedi/drivers/plx9080.h
index 3759a19..92d2480 100644
--- a/drivers/staging/comedi/drivers/plx9080.h
+++ b/drivers/staging/comedi/drivers/plx9080.h
@@ -36,7 +36,7 @@ struct plx_dma_desc {
__le32 transfer_size;
/*
* address of next descriptor (quad word aligned), plus some
- * additional bits (see PLX_DMA0_DESCRIPTOR_REG)
+ * additional bits (see PLX_REG_DMADPR)
*/
__le32 next;
};
@@ -49,10 +49,11 @@ struct plx_dma_desc {
**
**********************************************************************/
-/* L, Local Addr Space 0 Range Register */
-#define PLX_LAS0RNG_REG 0x0000
-/* L, Local Addr Space 1 Range Register */
-#define PLX_LAS1RNG_REG 0x00f0
+/* Local Address Space 0 Range Register */
+#define PLX_REG_LAS0RR 0x0000
+/* Local Address Space 1 Range Register */
+#define PLX_REG_LAS1RR 0x00f0
+
#define LRNG_IO 0x00000001 /* Map to: 1=I/O, 0=Mem */
#define LRNG_ANY32 0x00000000 /* Locate anywhere in 32 bit */
#define LRNG_LT1MB 0x00000002 /* Locate in 1st meg */
@@ -61,21 +62,23 @@ struct plx_dma_desc {
#define LRNG_MEM_MASK 0xfffffff0
/* bits that specify range for normal io */
#define LRNG_IO_MASK 0xfffffffc
-/* L, Local Addr Space 0 Remap Register */
-#define PLX_LAS0MAP_REG 0x0004
-/* L, Local Addr Space 1 Remap Register */
-#define PLX_LAS1MAP_REG 0x00f4
+
+/* Local Address Space 0 Local Base Address (Remap) Register */
+#define PLX_REG_LAS0BA 0x0004
+/* Local Address Space 1 Local Base Address (Remap) Register */
+#define PLX_REG_LAS1BA 0x00f4
+
#define LMAP_EN 0x00000001 /* Enable slave decode */
/* bits that specify decode for memory io */
#define LMAP_MEM_MASK 0xfffffff0
/* bits that specify decode bits for normal io */
#define LMAP_IO_MASK 0xfffffffc
-/*
- * Mode/Arbitration Register.
- */
-#define PLX_MARB_REG 0x8 /* L, Local Arbitration Register */
-#define PLX_DMAARB_REG 0xac
+/* Mode/Arbitration Register */
+#define PLX_REG_MARBR 0x0008
+/* DMA Arbitration Register (alias of MARBR). */
+#define PLX_REG_DMAARB 0x00ac
+
enum marb_bits {
MARB_LLT_MASK = 0x000000ff, /* Local Bus Latency Timer */
MARB_LPT_MASK = 0x0000ff00, /* Local Bus Pause Timer */
@@ -97,7 +100,9 @@ enum marb_bits {
MARB_USE_SUBSYSTEM_IDS = 0x20000000,
};
-#define PLX_BIGEND_REG 0xc
+/* Big/Little Endian Descriptor Register */
+#define PLX_REG_BIGEND 0x000c
+
enum bigend_bits {
/* use big endian ordering for configuration register accesses */
BIGEND_CONFIG = 0x1,
@@ -119,11 +124,16 @@ enum bigend_bits {
** This expansion ROM code is executed by the host CPU at boot time.
** For this reason no bit definitions are provided here.
*/
-#define PLX_ROMRNG_REG 0x0010 /* L, Expn ROM Space Range Register */
-/* L, Local Addr Space Range Register */
-#define PLX_ROMMAP_REG 0x0014
+/* Expansion ROM Range Register */
+#define PLX_REG_EROMRR 0x0010
+/* Expansion ROM Local Base Address (Remap) Register */
+#define PLX_REG_EROMBA 0x0014
+
+/* Local Address Space 0/Expansion ROM Bus Region Descriptor Register */
+#define PLX_REG_LBRD0 0x0018
+/* Local Address Space 1 Bus Region Descriptor Register */
+#define PLX_REG_LBRD1 0x00f8
-#define PLX_REGION0_REG 0x0018 /* L, Local Bus Region 0 Descriptor */
#define RGN_WIDTH 0x00000002 /* Local bus width bits */
#define RGN_8BITS 0x00000000 /* 08 bit Local Bus */
#define RGN_16BITS 0x00000001 /* 16 bit Local Bus */
@@ -149,15 +159,18 @@ enum bigend_bits {
#define RGN_THROT 0x08000000 /* De-assert TRDY when FIFO full */
#define RGN_TRD 0xF0000000 /* Target Ready Delay /8 */
-#define PLX_REGION1_REG 0x00f8 /* L, Local Bus Region 1 Descriptor */
+/* Local Range Register for Direct Master to PCI */
+#define PLX_REG_DMRR 0x001c
-#define PLX_DMRNG_REG 0x001C /* L, Direct Master Range Register */
+/* Local Bus Base Address Register for Direct Master to PCI Memory */
+#define PLX_REG_DMLBAM 0x0020
-#define PLX_LBAPMEM_REG 0x0020 /* L, Lcl Base Addr for PCI mem space */
+/* Local Base Address Register for Direct Master to PCI IO/CFG */
+#define PLX_REG_DMLBAI 0x0024
-#define PLX_LBAPIO_REG 0x0024 /* L, Lcl Base Addr for PCI I/O space */
+/* PCI Base Address (Remap) Register for Direct Master to PCI Memory */
+#define PLX_REG_DMPBAM 0x0028
-#define PLX_DMMAP_REG 0x0028 /* L, Direct Master Remap Register */
#define DMM_MAE 0x00000001 /* Direct Mstr Memory Acc Enable */
#define DMM_IAE 0x00000002 /* Direct Mstr I/O Acc Enable */
#define DMM_LCK 0x00000004 /* LOCK Input Enable */
@@ -173,7 +186,9 @@ enum bigend_bits {
#define DMM_PAF7 0x000000D0 /* Programmable Almost fill level */
#define DMM_MAP 0xFFFF0000 /* Remap Address Bits */
-#define PLX_CAR_REG 0x002C /* L, Configuration Address Register */
+/* PCI Configuration Address Register for Direct Master to PCI IO/CFG */
+#define PLX_REG_DMCFGA 0x002c
+
#define CAR_CT0 0x00000000 /* Config Type 0 */
#define CAR_CT1 0x00000001 /* Config Type 1 */
#define CAR_REG 0x000000FC /* Register Number Bits */
@@ -182,11 +197,38 @@ enum bigend_bits {
#define CAR_BUS 0x00FF0000 /* Bus Number Bits */
#define CAR_CFG 0x80000000 /* Config Spc Access Enable */
-#define PLX_DBR_IN_REG 0x0060 /* L, PCI to Local Doorbell Register */
-
-#define PLX_DBR_OUT_REG 0x0064 /* L, Local to PCI Doorbell Register */
+/*
+ * Mailbox Register N (N <= 7)
+ *
+ * Note that if the I2O feature is enabled (QSR[0] is set), Mailbox Register 0
+ * is replaced by the Inbound Queue Port, and Mailbox Register 1 is replaced
+ * by the Outbound Queue Port. However, Mailbox Register 0 and 1 are always
+ * accessible at alternative offsets if the I2O feature is enabled.
+ */
+#define PLX_REG_MBOX(n) (0x0040 + (n) * 4)
+#define PLX_REG_MBOX0 PLX_REG_MBOX(0)
+#define PLX_REG_MBOX1 PLX_REG_MBOX(1)
+#define PLX_REG_MBOX2 PLX_REG_MBOX(2)
+#define PLX_REG_MBOX3 PLX_REG_MBOX(3)
+#define PLX_REG_MBOX4 PLX_REG_MBOX(4)
+#define PLX_REG_MBOX5 PLX_REG_MBOX(5)
+#define PLX_REG_MBOX6 PLX_REG_MBOX(6)
+#define PLX_REG_MBOX7 PLX_REG_MBOX(7)
+
+/* Alternative offsets for Mailbox Registers 0 and 1 (in case I2O is enabled) */
+#define PLX_REG_ALT_MBOX(n) ((n) < 2 ? 0x0078 + (n) * 4 : PLX_REG_MBOX(n))
+#define PLX_REG_ALT_MBOX0 PLX_REG_ALT_MBOX(0)
+#define PLX_REG_ALT_MBOX1 PLX_REG_ALT_MBOX(1)
+
+/* PCI-to-Local Doorbell Register */
+#define PLX_REG_P2LDBELL 0x0060
+
+/* Local-to-PCI Doorbell Register */
+#define PLX_REG_L2PDBELL 0x0064
+
+/* Interrupt Control/Status Register */
+#define PLX_REG_INTCSR 0x0068
-#define PLX_INTRCS_REG 0x0068 /* L, Interrupt Control/Status Reg */
#define ICS_AERR 0x00000001 /* Assert LSERR on ABORT */
#define ICS_PERR 0x00000002 /* Assert LSERR on Parity Error */
#define ICS_SERR 0x00000004 /* Generate PCI SERR# */
@@ -214,7 +256,12 @@ enum bigend_bits {
/* mailbox x is active */
#define ICS_MBIA(x) (0x10000000 << ((x) & 0x3))
-#define PLX_CONTROL_REG 0x006C /* L, EEPROM Cntl & PCI Cmd Codes */
+/*
+ * Serial EEPROM Control, PCI Command Codes, User I/O Control,
+ * Init Control Register
+ */
+#define PLX_REG_CNTRL 0x006c
+
#define CTL_RDMA 0x0000000E /* DMA Read Command */
#define CTL_WDMA 0x00000070 /* DMA Write Command */
#define CTL_RMEM 0x00000600 /* Memory Read Command */
@@ -230,12 +277,17 @@ enum bigend_bits {
#define CTL_RESET 0x40000000 /* !! Adapter Reset !! */
#define CTL_READY 0x80000000 /* Local Init Done */
-#define PLX_ID_REG 0x70 /* hard-coded plx vendor and device ids */
+/* PCI Permanent Configuration ID Register (hard-coded PLX vendor and device) */
+#define PLX_REG_PCIHIDR 0x0070
+
+/* PCI Permanent Revision ID Register (hard-coded silicon revision) (8-bit). */
+#define PLX_REG_PCIHREV 0x0074
-#define PLX_REVISION_REG 0x74 /* silicon revision */
+/* DMA Channel N Mode Register (N <= 1) */
+#define PLX_REG_DMAMODE(n) ((n) ? PLX_REG_DMAMODE1 : PLX_REG_DMAMODE0)
+#define PLX_REG_DMAMODE0 0x0080
+#define PLX_REG_DMAMODE1 0x0094
-#define PLX_DMA0_MODE_REG 0x80 /* dma channel 0 mode register */
-#define PLX_DMA1_MODE_REG 0x94 /* dma channel 0 mode register */
#define PLX_LOCAL_BUS_16_WIDE_BITS 0x1
#define PLX_LOCAL_BUS_32_WIDE_BITS 0x3
#define PLX_LOCAL_BUS_WIDTH_MASK 0x3
@@ -254,20 +306,26 @@ enum bigend_bits {
/* routes dma interrupt to pci bus (instead of local bus) */
#define PLX_DMA_INTR_PCI_BIT 0x20000
-/* pci address that dma transfers start at */
-#define PLX_DMA0_PCI_ADDRESS_REG 0x84
-#define PLX_DMA1_PCI_ADDRESS_REG 0x98
+/* DMA Channel N PCI Address Register (N <= 1) */
+#define PLX_REG_DMAPADR(n) ((n) ? PLX_REG_DMAPADR1 : PLX_REG_DMAPADR0)
+#define PLX_REG_DMAPADR0 0x0084
+#define PLX_REG_DMAPADR1 0x0098
+
+/* DMA Channel N Local Address Register (N <= 1) */
+#define PLX_REG_DMALADR(n) ((n) ? PLX_REG_DMALADR1 : PLX_REG_DMALADR0)
+#define PLX_REG_DMALADR0 0x0088
+#define PLX_REG_DMALADR1 0x009c
-/* local address that dma transfers start at */
-#define PLX_DMA0_LOCAL_ADDRESS_REG 0x88
-#define PLX_DMA1_LOCAL_ADDRESS_REG 0x9c
+/* DMA Channel N Transfer Size (Bytes) Register (N <= 1) (first 23 bits) */
+#define PLX_REG_DMASIZ(n) ((n) ? PLX_REG_DMASIZ1 : PLX_REG_DMASIZ0)
+#define PLX_REG_DMASIZ0 0x008c
+#define PLX_REG_DMASIZ1 0x00a0
-/* number of bytes to transfer (first 23 bits) */
-#define PLX_DMA0_TRANSFER_SIZE_REG 0x8c
-#define PLX_DMA1_TRANSFER_SIZE_REG 0xa0
+/* DMA Channel N Descriptor Pointer Register (N <= 1) */
+#define PLX_REG_DMADPR(n) ((n) ? PLX_REG_DMADPR1 : PLX_REG_DMADPR0)
+#define PLX_REG_DMADPR0 0x0090
+#define PLX_REG_DMADPR1 0x00a4
-#define PLX_DMA0_DESCRIPTOR_REG 0x90 /* descriptor pointer register */
-#define PLX_DMA1_DESCRIPTOR_REG 0xa4
/* descriptor is located in pci space (not local space) */
#define PLX_DESC_IN_PCI_BIT 0x1
#define PLX_END_OF_CHAIN_BIT 0x2 /* end of chain bit */
@@ -276,15 +334,33 @@ enum bigend_bits {
/* transfer from local to pci bus (not pci to local) */
#define PLX_XFER_LOCAL_TO_PCI 0x8
-#define PLX_DMA0_CS_REG 0xa8 /* command status register */
-#define PLX_DMA1_CS_REG 0xa9
+/* DMA Channel N Command/Status Register (N <= 1) (8-bit) */
+#define PLX_REG_DMACSR(n) ((n) ? PLX_REG_DMACSR1 : PLX_REG_DMACSR0)
+#define PLX_REG_DMACSR0 0x00a8
+#define PLX_REG_DMACSR1 0x00a9
+
#define PLX_DMA_EN_BIT 0x1 /* enable dma channel */
#define PLX_DMA_START_BIT 0x2 /* start dma transfer */
#define PLX_DMA_ABORT_BIT 0x4 /* abort dma transfer */
#define PLX_CLEAR_DMA_INTR_BIT 0x8 /* clear dma interrupt */
#define PLX_DMA_DONE_BIT 0x10 /* transfer done status bit */
-#define PLX_DMA0_THRESHOLD_REG 0xb0 /* command status register */
+/* DMA Threshold Register */
+#define PLX_REG_DMATHR 0x00b0
+
+/*
+ * Messaging Queue Registers OPLFIS, OPLFIM, IQP, OQP, MQCR, QBAR, IFHPR,
+ * IFTPR, IPHPR, IPTPR, OFHPR, OFTPR, OPHPR, OPTPR, and QSR have been omitted.
+ * They are used by the I2O feature. (IQP and OQP occupy the usual offsets of
+ * the MBOX0 and MBOX1 registers if the I2O feature is enabled, but MBOX0 and
+ * MBOX1 are accessible via alternative offsets.
+ */
+
+/* Queue Status/Control Register */
+#define PLX_REG_QSR 0x00e8
+
+/* Value of QSR after reset - disables I2O feature completely. */
+#define PLX_QSR_VALUE_AFTER_RESET 0x00000050
/*
* Accesses near the end of memory can cause the PLX chip
@@ -301,10 +377,7 @@ static inline int plx9080_abort_dma(void __iomem *iobase, unsigned int channel)
const int timeout = 10000;
unsigned int i;
- if (channel)
- dma_cs_addr = iobase + PLX_DMA1_CS_REG;
- else
- dma_cs_addr = iobase + PLX_DMA0_CS_REG;
+ dma_cs_addr = iobase + PLX_REG_DMACSR(channel);
/* abort dma transfer if necessary */
dma_status = readb(dma_cs_addr);
diff --git a/drivers/staging/comedi/drivers/rtd520.c b/drivers/staging/comedi/drivers/rtd520.c
index 9b6c567..5a4464e 100644
--- a/drivers/staging/comedi/drivers/rtd520.c
+++ b/drivers/staging/comedi/drivers/rtd520.c
@@ -1175,7 +1175,7 @@ static void rtd_reset(struct comedi_device *dev)
writel(0, dev->mmio + LAS0_BOARD_RESET);
usleep_range(100, 1000); /* needed? */
- writel(0, devpriv->lcfg + PLX_INTRCS_REG);
+ writel(0, devpriv->lcfg + PLX_REG_INTCSR);
writew(0, dev->mmio + LAS0_IT);
writew(~0, dev->mmio + LAS0_CLEAR);
readw(dev->mmio + LAS0_CLEAR);
@@ -1316,7 +1316,7 @@ static int rtd_auto_attach(struct comedi_device *dev,
devpriv->fifosz = ret;
if (dev->irq)
- writel(ICS_PIE | ICS_PLIE, devpriv->lcfg + PLX_INTRCS_REG);
+ writel(ICS_PIE | ICS_PLIE, devpriv->lcfg + PLX_REG_INTCSR);
return 0;
}
--
2.8.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 04/20] staging: comedi: drivers: re-do macros for PLX PCI 9080 LASxRR values
2016-05-20 13:49 [PATCH 00/20] staging: comedi: re-do drivers/plx9080.h Ian Abbott
` (2 preceding siblings ...)
2016-05-20 13:49 ` [PATCH 03/20] staging: comedi: drivers: rename PLX PCI 9080 register offsets Ian Abbott
@ 2016-05-20 13:49 ` Ian Abbott
2016-05-20 16:37 ` Hartley Sweeten
2016-05-20 13:49 ` [PATCH 05/20] staging: comedi: drivers: re-do macros for PLX PCI 9080 LASxBA values Ian Abbott
` (15 subsequent siblings)
19 siblings, 1 reply; 28+ messages in thread
From: Ian Abbott @ 2016-05-20 13:49 UTC (permalink / raw)
To: devel; +Cc: Greg Kroah-Hartman, Ian Abbott, H Hartley Sweeten, linux-kernel
Rename the macros for the PLX PCI 9080 LAS0RR and LAS1RR registers in
"plx9080.h", using the prefix `PLX_LASRR_`. Make use of the `BIT(x)`
and `GENMASK(h,l)` macros to define the values.
Define a macro `PLX_LASRR_PREFETCH` for the "prefetchable memory" bit in
this register, and define a macro `PLX_LASRR_MLOC_MASK` to mask the PCI
memory location control bits.
Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
---
drivers/staging/comedi/drivers/cb_pcidas64.c | 4 ++--
drivers/staging/comedi/drivers/plx9080.h | 18 ++++++++++--------
2 files changed, 12 insertions(+), 10 deletions(-)
diff --git a/drivers/staging/comedi/drivers/cb_pcidas64.c b/drivers/staging/comedi/drivers/cb_pcidas64.c
index d9468db..59d81e8 100644
--- a/drivers/staging/comedi/drivers/cb_pcidas64.c
+++ b/drivers/staging/comedi/drivers/cb_pcidas64.c
@@ -4004,13 +4004,13 @@ static int auto_attach(struct comedi_device *dev,
/* figure out what local addresses are */
local_range = readl(devpriv->plx9080_iobase + PLX_REG_LAS0RR) &
- LRNG_MEM_MASK;
+ PLX_LASRR_MEM_MASK;
local_decode = readl(devpriv->plx9080_iobase + PLX_REG_LAS0BA) &
local_range & LMAP_MEM_MASK;
devpriv->local0_iobase = ((uint32_t)devpriv->main_phys_iobase &
~local_range) | local_decode;
local_range = readl(devpriv->plx9080_iobase + PLX_REG_LAS1RR) &
- LRNG_MEM_MASK;
+ PLX_LASRR_MEM_MASK;
local_decode = readl(devpriv->plx9080_iobase + PLX_REG_LAS1BA) &
local_range & LMAP_MEM_MASK;
devpriv->local1_iobase = ((uint32_t)devpriv->dio_counter_phys_iobase &
diff --git a/drivers/staging/comedi/drivers/plx9080.h b/drivers/staging/comedi/drivers/plx9080.h
index 92d2480..8788117 100644
--- a/drivers/staging/comedi/drivers/plx9080.h
+++ b/drivers/staging/comedi/drivers/plx9080.h
@@ -54,14 +54,16 @@ struct plx_dma_desc {
/* Local Address Space 1 Range Register */
#define PLX_REG_LAS1RR 0x00f0
-#define LRNG_IO 0x00000001 /* Map to: 1=I/O, 0=Mem */
-#define LRNG_ANY32 0x00000000 /* Locate anywhere in 32 bit */
-#define LRNG_LT1MB 0x00000002 /* Locate in 1st meg */
-#define LRNG_ANY64 0x00000004 /* Locate anywhere in 64 bit */
-/* bits that specify range for memory io */
-#define LRNG_MEM_MASK 0xfffffff0
-/* bits that specify range for normal io */
-#define LRNG_IO_MASK 0xfffffffc
+#define PLX_LASRR_IO BIT(0) /* Map to: 1=I/O, 0=Mem */
+#define PLX_LASRR_ANY32 (BIT(1) * 0) /* Locate anywhere in 32 bit */
+#define PLX_LASRR_LT1MB (BIT(1) * 1) /* Locate in 1st meg */
+#define PLX_LASRR_ANY64 (BIT(1) * 2) /* Locate anywhere in 64 bit */
+#define PLX_LASRR_MLOC_MASK GENMASK(2, 1) /* Memory location bits */
+#define PLX_LASRR_PREFETCH BIT(3) /* Memory is prefetchable */
+/* bits that specify range for memory space decode bits */
+#define PLX_LASRR_MEM_MASK GENMASK(31, 4)
+/* bits that specify range for i/o space decode bits */
+#define PLX_LASRR_IO_MASK GENMASK(31, 2)
/* Local Address Space 0 Local Base Address (Remap) Register */
#define PLX_REG_LAS0BA 0x0004
--
2.8.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 05/20] staging: comedi: drivers: re-do macros for PLX PCI 9080 LASxBA values
2016-05-20 13:49 [PATCH 00/20] staging: comedi: re-do drivers/plx9080.h Ian Abbott
` (3 preceding siblings ...)
2016-05-20 13:49 ` [PATCH 04/20] staging: comedi: drivers: re-do macros for PLX PCI 9080 LASxRR values Ian Abbott
@ 2016-05-20 13:49 ` Ian Abbott
2016-05-20 13:49 ` [PATCH 06/20] staging: comedi: drivers: re-do PLX PCI 9080 MARBR register values Ian Abbott
` (14 subsequent siblings)
19 siblings, 0 replies; 28+ messages in thread
From: Ian Abbott @ 2016-05-20 13:49 UTC (permalink / raw)
To: devel; +Cc: Greg Kroah-Hartman, Ian Abbott, H Hartley Sweeten, linux-kernel
Replace the existing macros in "plx9080.h" that define values for the
LAS0BA and LAS1BA registers. Use the prefix `PLX_LASBA_` for the
macros. Make use of the `BIT(x)` and `GENMASK(h,l)` macros to define
the macros.
Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
---
drivers/staging/comedi/drivers/cb_pcidas64.c | 4 ++--
drivers/staging/comedi/drivers/plx9080.h | 10 +++++-----
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/staging/comedi/drivers/cb_pcidas64.c b/drivers/staging/comedi/drivers/cb_pcidas64.c
index 59d81e8..f997c1f 100644
--- a/drivers/staging/comedi/drivers/cb_pcidas64.c
+++ b/drivers/staging/comedi/drivers/cb_pcidas64.c
@@ -4006,13 +4006,13 @@ static int auto_attach(struct comedi_device *dev,
local_range = readl(devpriv->plx9080_iobase + PLX_REG_LAS0RR) &
PLX_LASRR_MEM_MASK;
local_decode = readl(devpriv->plx9080_iobase + PLX_REG_LAS0BA) &
- local_range & LMAP_MEM_MASK;
+ local_range & PLX_LASBA_MEM_MASK;
devpriv->local0_iobase = ((uint32_t)devpriv->main_phys_iobase &
~local_range) | local_decode;
local_range = readl(devpriv->plx9080_iobase + PLX_REG_LAS1RR) &
PLX_LASRR_MEM_MASK;
local_decode = readl(devpriv->plx9080_iobase + PLX_REG_LAS1BA) &
- local_range & LMAP_MEM_MASK;
+ local_range & PLX_LASBA_MEM_MASK;
devpriv->local1_iobase = ((uint32_t)devpriv->dio_counter_phys_iobase &
~local_range) | local_decode;
diff --git a/drivers/staging/comedi/drivers/plx9080.h b/drivers/staging/comedi/drivers/plx9080.h
index 8788117..140135c 100644
--- a/drivers/staging/comedi/drivers/plx9080.h
+++ b/drivers/staging/comedi/drivers/plx9080.h
@@ -70,11 +70,11 @@ struct plx_dma_desc {
/* Local Address Space 1 Local Base Address (Remap) Register */
#define PLX_REG_LAS1BA 0x00f4
-#define LMAP_EN 0x00000001 /* Enable slave decode */
-/* bits that specify decode for memory io */
-#define LMAP_MEM_MASK 0xfffffff0
-/* bits that specify decode bits for normal io */
-#define LMAP_IO_MASK 0xfffffffc
+#define PLX_LASBA_EN BIT(0) /* Enable slave decode */
+/* bits that specify local base address for memory space */
+#define PLX_LASBA_MEM_MASK GENMASK(31, 4)
+/* bits that specify local base address for i/o space */
+#define PLX_LASBA_IO_MASK GENMASK(31, 2)
/* Mode/Arbitration Register */
#define PLX_REG_MARBR 0x0008
--
2.8.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 06/20] staging: comedi: drivers: re-do PLX PCI 9080 MARBR register values
2016-05-20 13:49 [PATCH 00/20] staging: comedi: re-do drivers/plx9080.h Ian Abbott
` (4 preceding siblings ...)
2016-05-20 13:49 ` [PATCH 05/20] staging: comedi: drivers: re-do macros for PLX PCI 9080 LASxBA values Ian Abbott
@ 2016-05-20 13:49 ` Ian Abbott
2016-05-20 13:49 ` [PATCH 07/20] staging: comedi: drivers: re-do PLX PCI 9080 BIGEND " Ian Abbott
` (13 subsequent siblings)
19 siblings, 0 replies; 28+ messages in thread
From: Ian Abbott @ 2016-05-20 13:49 UTC (permalink / raw)
To: devel; +Cc: Greg Kroah-Hartman, Ian Abbott, H Hartley Sweeten, linux-kernel
Replace `enum marb_bits` in "plx9080.h" with a bunch of macros defining
values for the MARBR and DMAARB registers (which are the same
Mode/Arbitation register at two different offsets). Use the prefix
`PLX_MARBR_` for the macros. Make use of the `BIT(x)` and
`GENMASK(h,l)` macros to define the values.
Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
---
drivers/staging/comedi/drivers/plx9080.h | 60 +++++++++++++++++++++-----------
1 file changed, 40 insertions(+), 20 deletions(-)
diff --git a/drivers/staging/comedi/drivers/plx9080.h b/drivers/staging/comedi/drivers/plx9080.h
index 140135c..0bcdbad 100644
--- a/drivers/staging/comedi/drivers/plx9080.h
+++ b/drivers/staging/comedi/drivers/plx9080.h
@@ -81,26 +81,46 @@ struct plx_dma_desc {
/* DMA Arbitration Register (alias of MARBR). */
#define PLX_REG_DMAARB 0x00ac
-enum marb_bits {
- MARB_LLT_MASK = 0x000000ff, /* Local Bus Latency Timer */
- MARB_LPT_MASK = 0x0000ff00, /* Local Bus Pause Timer */
- MARB_LTEN = 0x00010000, /* Latency Timer Enable */
- MARB_LPEN = 0x00020000, /* Pause Timer Enable */
- MARB_BREQ = 0x00040000, /* Local Bus BREQ Enable */
- MARB_DMA_PRIORITY_MASK = 0x00180000,
- /* local bus direct slave give up bus mode */
- MARB_LBDS_GIVE_UP_BUS_MODE = 0x00200000,
- /* direct slave LLOCKo# enable */
- MARB_DS_LLOCK_ENABLE = 0x00400000,
- MARB_PCI_REQUEST_MODE = 0x00800000,
- MARB_PCIV21_MODE = 0x01000000, /* pci specification v2.1 mode */
- MARB_PCI_READ_NO_WRITE_MODE = 0x02000000,
- MARB_PCI_READ_WITH_WRITE_FLUSH_MODE = 0x04000000,
- /* gate local bus latency timer with BREQ */
- MARB_GATE_TIMER_WITH_BREQ = 0x08000000,
- MARB_PCI_READ_NO_FLUSH_MODE = 0x10000000,
- MARB_USE_SUBSYSTEM_IDS = 0x20000000,
-};
+/* Local Bus Latency Timer */
+#define PLX_MARBR_LT(x) (BIT(0) * ((x) & 0xff))
+#define PLX_MARBR_LT_MASK GENMASK(7, 0)
+#define PLX_MARBR_LT_SHIFT 0
+/* Local Bus Pause Timer */
+#define PLX_MARBR_PT(x) (BIT(8) * ((x) & 0xff))
+#define PLX_MARBR_PT_MASK GENMASK(15, 8)
+#define PLX_MARBR_PT_SHIFT 8
+/* Local Bus Latency Timer Enable */
+#define PLX_MARBR_LTEN BIT(16)
+/* Local Bus Pause Timer Enable */
+#define PLX_MARBR_PTEN BIT(17)
+/* Local Bus BREQ Enable */
+#define PLX_MARBR_BREQEN BIT(18)
+/* DMA Channel Priority */
+#define PLX_MARBR_PRIO_ROT (BIT(19) * 0) /* Rotational priority */
+#define PLX_MARBR_PRIO_DMA0 (BIT(19) * 1) /* DMA channel 0 has priority */
+#define PLX_MARBR_PRIO_DMA1 (BIT(19) * 2) /* DMA channel 1 has priority */
+#define PLX_MARBR_PRIO_MASK GENMASK(20, 19)
+/* Local Bus Direct Slave Give Up Bus Mode */
+#define PLX_MARBR_DSGUBM BIT(21)
+/* Direct Slace LLOCKo# Enable */
+#define PLX_MARBR_DSLLOCKOEN BIT(22)
+/* PCI Request Mode */
+#define PLX_MARBR_PCIREQM BIT(23)
+/* PCI Specification v2.1 Mode */
+#define PLX_MARBR_PCIV21M BIT(24)
+/* PCI Read No Write Mode */
+#define PLX_MARBR_PCIRNWM BIT(25)
+/* PCI Read with Write Flush Mode */
+#define PLX_MARBR_PCIRWFM BIT(26)
+/* Gate Local Bus Latency Timer with BREQ */
+#define PLX_MARBR_GLTBREQ BIT(27)
+/* PCI Read No Flush Mode */
+#define PLX_MARBR_PCIRNFM BIT(28)
+/*
+ * Make reads from PCI Configuration register 0 return Subsystem ID and
+ * Subsystem Vendor ID instead of Device ID and Vendor ID
+ */
+#define PLX_MARBR_SUBSYSIDS BIT(29)
/* Big/Little Endian Descriptor Register */
#define PLX_REG_BIGEND 0x000c
--
2.8.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 07/20] staging: comedi: drivers: re-do PLX PCI 9080 BIGEND register values
2016-05-20 13:49 [PATCH 00/20] staging: comedi: re-do drivers/plx9080.h Ian Abbott
` (5 preceding siblings ...)
2016-05-20 13:49 ` [PATCH 06/20] staging: comedi: drivers: re-do PLX PCI 9080 MARBR register values Ian Abbott
@ 2016-05-20 13:49 ` Ian Abbott
2016-05-20 13:49 ` [PATCH 08/20] staging: comedi: drivers: re-do PLX PCI 9080 LBRDx " Ian Abbott
` (12 subsequent siblings)
19 siblings, 0 replies; 28+ messages in thread
From: Ian Abbott @ 2016-05-20 13:49 UTC (permalink / raw)
To: devel; +Cc: Greg Kroah-Hartman, Ian Abbott, H Hartley Sweeten, linux-kernel
Replace `enum bigend_bits` in "plx9080.h" with a bunch of macros
defining values for the BIGEND register. Use the prefix `PLX_BIGEND_`
for the macro names. Make use of the `BIT(x)` and `GENMASK(h,l)` macros
to define the values.
Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
---
drivers/staging/comedi/drivers/cb_pcidas64.c | 2 +-
drivers/staging/comedi/drivers/gsc_hpdi.c | 2 +-
drivers/staging/comedi/drivers/plx9080.h | 33 +++++++++++++++-------------
3 files changed, 20 insertions(+), 17 deletions(-)
diff --git a/drivers/staging/comedi/drivers/cb_pcidas64.c b/drivers/staging/comedi/drivers/cb_pcidas64.c
index f997c1f..4a8e88a 100644
--- a/drivers/staging/comedi/drivers/cb_pcidas64.c
+++ b/drivers/staging/comedi/drivers/cb_pcidas64.c
@@ -1294,7 +1294,7 @@ static void init_plx9080(struct comedi_device *dev)
readl(devpriv->plx9080_iobase + PLX_REG_CNTRL);
#ifdef __BIG_ENDIAN
- bits = BIGEND_DMA0 | BIGEND_DMA1;
+ bits = PLX_BIGEND_DMA0 | PLX_BIGEND_DMA1;
#else
bits = 0;
#endif
diff --git a/drivers/staging/comedi/drivers/gsc_hpdi.c b/drivers/staging/comedi/drivers/gsc_hpdi.c
index e2831e1..536bebe 100644
--- a/drivers/staging/comedi/drivers/gsc_hpdi.c
+++ b/drivers/staging/comedi/drivers/gsc_hpdi.c
@@ -547,7 +547,7 @@ static void gsc_hpdi_init_plx9080(struct comedi_device *dev)
void __iomem *plx_iobase = devpriv->plx9080_mmio;
#ifdef __BIG_ENDIAN
- bits = BIGEND_DMA0 | BIGEND_DMA1;
+ bits = PLX_BIGEND_DMA0 | PLX_BIGEND_DMA1;
#else
bits = 0;
#endif
diff --git a/drivers/staging/comedi/drivers/plx9080.h b/drivers/staging/comedi/drivers/plx9080.h
index 0bcdbad..84dd366 100644
--- a/drivers/staging/comedi/drivers/plx9080.h
+++ b/drivers/staging/comedi/drivers/plx9080.h
@@ -125,21 +125,24 @@ struct plx_dma_desc {
/* Big/Little Endian Descriptor Register */
#define PLX_REG_BIGEND 0x000c
-enum bigend_bits {
- /* use big endian ordering for configuration register accesses */
- BIGEND_CONFIG = 0x1,
- BIGEND_DIRECT_MASTER = 0x2,
- BIGEND_DIRECT_SLAVE_LOCAL0 = 0x4,
- BIGEND_ROM = 0x8,
- /*
- * use byte lane consisting of most significant bits instead of
- * least significant
- */
- BIGEND_BYTE_LANE = 0x10,
- BIGEND_DIRECT_SLAVE_LOCAL1 = 0x20,
- BIGEND_DMA1 = 0x40,
- BIGEND_DMA0 = 0x80,
-};
+/* Configuration Register Big Endian Mode */
+#define PLX_BIGEND_CONFIG BIT(0)
+/* Direct Master Big Endian Mode */
+#define PLX_BIGEND_DM BIT(1)
+/* Direct Slave Address Space 0 Big Endian Mode */
+#define PLX_BIGEND_DSAS0 BIT(2)
+/* Direct Slave Expansion ROM Big Endian Mode */
+#define PLX_BIGEND_EROM BIT(3)
+/* Big Endian Byte Lane Mode - use most significant byte lanes */
+#define PLX_BIGEND_BEBLM BIT(4)
+/* Direct Slave Address Space 1 Big Endian Mode */
+#define PLX_BIGEND_DSAS1 BIT(5)
+/* DMA Channel 1 Big Endian Mode */
+#define PLX_BIGEND_DMA1 BIT(6)
+/* DMA Channel 0 Big Endian Mode */
+#define PLX_BIGEND_DMA0 BIT(7)
+/* DMA Channel N Big Endian Mode (N <= 1) */
+#define PLX_BIGEND_DMA(n) ((n) ? PLX_BIGEND_DMA1 : PLX_BIGEND_DMA0)
/*
** Note: The Expansion ROM stuff is only relevant to the PC environment.
--
2.8.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 08/20] staging: comedi: drivers: re-do PLX PCI 9080 LBRDx register values
2016-05-20 13:49 [PATCH 00/20] staging: comedi: re-do drivers/plx9080.h Ian Abbott
` (6 preceding siblings ...)
2016-05-20 13:49 ` [PATCH 07/20] staging: comedi: drivers: re-do PLX PCI 9080 BIGEND " Ian Abbott
@ 2016-05-20 13:49 ` Ian Abbott
2016-05-20 13:49 ` [PATCH 09/20] staging: comedi: drivers: re-do PLX PCI 9080 DMPBAM " Ian Abbott
` (11 subsequent siblings)
19 siblings, 0 replies; 28+ messages in thread
From: Ian Abbott @ 2016-05-20 13:49 UTC (permalink / raw)
To: devel; +Cc: Greg Kroah-Hartman, Ian Abbott, H Hartley Sweeten, linux-kernel
Replace the existing macros in "plx9080.h" that define values for the
LBRD0 and LBRD1 registers. Use the prefix `PLX_LBRD_` for macros that
apply to both registers, `PLX_LBRD0_` for macros that apply only to the
LBRD0 register, and `PLX_LBRD1_` for macros that apply only to the LBRD1
register. Make use of the `BIT(x)` and `GENMASK(h,l)` macros to define
the values.
Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
---
drivers/staging/comedi/drivers/plx9080.h | 80 ++++++++++++++++++++++----------
1 file changed, 56 insertions(+), 24 deletions(-)
diff --git a/drivers/staging/comedi/drivers/plx9080.h b/drivers/staging/comedi/drivers/plx9080.h
index 84dd366..93b2e89 100644
--- a/drivers/staging/comedi/drivers/plx9080.h
+++ b/drivers/staging/comedi/drivers/plx9080.h
@@ -159,30 +159,62 @@ struct plx_dma_desc {
/* Local Address Space 1 Bus Region Descriptor Register */
#define PLX_REG_LBRD1 0x00f8
-#define RGN_WIDTH 0x00000002 /* Local bus width bits */
-#define RGN_8BITS 0x00000000 /* 08 bit Local Bus */
-#define RGN_16BITS 0x00000001 /* 16 bit Local Bus */
-#define RGN_32BITS 0x00000002 /* 32 bit Local Bus */
-#define RGN_MWS 0x0000003C /* Memory Access Wait States */
-#define RGN_0MWS 0x00000000
-#define RGN_1MWS 0x00000004
-#define RGN_2MWS 0x00000008
-#define RGN_3MWS 0x0000000C
-#define RGN_4MWS 0x00000010
-#define RGN_6MWS 0x00000018
-#define RGN_8MWS 0x00000020
-#define RGN_MRE 0x00000040 /* Memory Space Ready Input Enable */
-#define RGN_MBE 0x00000080 /* Memory Space Bterm Input Enable */
-#define RGN_READ_PREFETCH_DISABLE 0x00000100
-#define RGN_ROM_PREFETCH_DISABLE 0x00000200
-#define RGN_READ_PREFETCH_COUNT_ENABLE 0x00000400
-#define RGN_RWS 0x003C0000 /* Expn ROM Wait States */
-#define RGN_RRE 0x00400000 /* ROM Space Ready Input Enable */
-#define RGN_RBE 0x00800000 /* ROM Space Bterm Input Enable */
-#define RGN_MBEN 0x01000000 /* Memory Space Burst Enable */
-#define RGN_RBEN 0x04000000 /* ROM Space Burst Enable */
-#define RGN_THROT 0x08000000 /* De-assert TRDY when FIFO full */
-#define RGN_TRD 0xF0000000 /* Target Ready Delay /8 */
+/* Memory Space Local Bus Width */
+#define PLX_LBRD_MSWIDTH8 (BIT(0) * 0) /* 8 bits wide */
+#define PLX_LBRD_MSWIDTH16 (BIT(0) * 1) /* 16 bits wide */
+#define PLX_LBRD_MSWIDTH32 (BIT(0) * 2) /* 32 bits wide */
+#define PLX_LBRD_MSWIDTH32A (BIT(0) * 3) /* 32 bits wide */
+#define PLX_LBRD_MSWIDTH_MASK GENMASK(1, 0)
+#define PLX_LBRD_MSWIDTH_SHIFT 0
+/* Memory Space Internal Wait States */
+#define PLX_LBRD_MSIWS(x) (BIT(2) * ((x) & 0xf))
+#define PLX_LBRD_MSIWS_MASK GENMASK(5, 2)
+#define PLX_LBRD_MSIWS_SHIFT 2
+/* Memory Space Ready Input Enable */
+#define PLX_LBRD_MSREADYIEN BIT(6)
+/* Memory Space BTERM# Input Enable */
+#define PLX_LBRD_MSBTERMIEN BIT(7)
+/* Memory Space 0 Prefetch Disable (LBRD0 only) */
+#define PLX_LBRD0_MSPREDIS BIT(8)
+/* Memory Space 1 Burst Enable (LBRD1 only) */
+#define PLX_LBRD1_MSBURSTEN BIT(8)
+/* Expansion ROM Space Prefetch Disable (LBRD0 only) */
+#define PLX_LBRD0_EROMPREDIS BIT(9)
+/* Memory Space 1 Prefetch Disable (LBRD1 only) */
+#define PLX_LBRD1_MSPREDIS BIT(9)
+/* Read Prefetch Count Enable */
+#define PLX_LBRD_RPFCOUNTEN BIT(10)
+/* Prefetch Counter */
+#define PLX_LBRD_PFCOUNT(x) (BIT(11) * ((x) & 0xf))
+#define PLX_LBRD_PFCOUNT_MASK GENMASK(14, 11)
+#define PLX_LBRD_PFCOUNT_SHIFT 11
+/* Expansion ROM Space Local Bus Width (LBRD0 only) */
+#define PLX_LBRD0_EROMWIDTH8 (BIT(16) * 0) /* 8 bits wide */
+#define PLX_LBRD0_EROMWIDTH16 (BIT(16) * 1) /* 16 bits wide */
+#define PLX_LBRD0_EROMWIDTH32 (BIT(16) * 2) /* 32 bits wide */
+#define PLX_LBRD0_EROMWIDTH32A (BIT(16) * 3) /* 32 bits wide */
+#define PLX_LBRD0_EROMWIDTH_MASK GENMASK(17, 16)
+#define PLX_LBRD0_EROMWIDTH_SHIFT 16
+/* Expansion ROM Space Internal Wait States (LBRD0 only) */
+#define PLX_LBRD0_EROMIWS(x) (BIT(18) * ((x) & 0xf))
+#define PLX_LBRD0_EROMIWS_MASK GENMASK(21, 18)
+#define PLX_LBRD0_EROMIWS_SHIFT 18
+/* Expansion ROM Space Ready Input Enable (LBDR0 only) */
+#define PLX_LBRD0_EROMREADYIEN BIT(22)
+/* Expansion ROM Space BTERM# Input Enable (LBRD0 only) */
+#define PLX_LBRD0_EROMBTERMIEN BIT(23)
+/* Memory Space 0 Burst Enable (LBRD0 only) */
+#define PLX_LBRD0_MSBURSTEN BIT(24)
+/* Extra Long Load From Serial EEPROM (LBRD0 only) */
+#define PLX_LBRD0_EELONGLOAD BIT(25)
+/* Expansion ROM Space Burst Enable (LBRD0 only) */
+#define PLX_LBRD0_EROMBURSTEN BIT(26)
+/* Direct Slave PCI Write Mode - assert TRDY# when FIFO full (LBRD0 only) */
+#define PLX_LBRD0_DSWMTRDY BIT(27)
+/* PCI Target Retry Delay Clocks / 8 (LBRD0 only) */
+#define PLX_LBRD0_TRDELAY(x) (BIT(28) * ((x) & 0xF))
+#define PLX_LBRD0_TRDELAY_MASK GENMASK(31, 28)
+#define PLX_LBRD0_TRDELAY_SHIFT 28
/* Local Range Register for Direct Master to PCI */
#define PLX_REG_DMRR 0x001c
--
2.8.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 09/20] staging: comedi: drivers: re-do PLX PCI 9080 DMPBAM register values
2016-05-20 13:49 [PATCH 00/20] staging: comedi: re-do drivers/plx9080.h Ian Abbott
` (7 preceding siblings ...)
2016-05-20 13:49 ` [PATCH 08/20] staging: comedi: drivers: re-do PLX PCI 9080 LBRDx " Ian Abbott
@ 2016-05-20 13:49 ` Ian Abbott
2016-05-20 13:49 ` [PATCH 10/20] staging: comedi: drivers: re-do PLX PCI 9080 DMCFGA " Ian Abbott
` (10 subsequent siblings)
19 siblings, 0 replies; 28+ messages in thread
From: Ian Abbott @ 2016-05-20 13:49 UTC (permalink / raw)
To: devel; +Cc: Greg Kroah-Hartman, Ian Abbott, H Hartley Sweeten, linux-kernel
Replace the existing macros in "plx9080.h" that define values for the
DMPBAM register. Use the prefix `PLX_DMPBAM_` for the macros. Make use
of the `BIT(x)` and `GENMASK(h,l)` macros to define the values.
Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
---
drivers/staging/comedi/drivers/plx9080.h | 48 ++++++++++++++++++++++----------
1 file changed, 34 insertions(+), 14 deletions(-)
diff --git a/drivers/staging/comedi/drivers/plx9080.h b/drivers/staging/comedi/drivers/plx9080.h
index 93b2e89..ab90837 100644
--- a/drivers/staging/comedi/drivers/plx9080.h
+++ b/drivers/staging/comedi/drivers/plx9080.h
@@ -228,20 +228,40 @@ struct plx_dma_desc {
/* PCI Base Address (Remap) Register for Direct Master to PCI Memory */
#define PLX_REG_DMPBAM 0x0028
-#define DMM_MAE 0x00000001 /* Direct Mstr Memory Acc Enable */
-#define DMM_IAE 0x00000002 /* Direct Mstr I/O Acc Enable */
-#define DMM_LCK 0x00000004 /* LOCK Input Enable */
-#define DMM_PF4 0x00000008 /* Prefetch 4 Mode Enable */
-#define DMM_THROT 0x00000010 /* Assert IRDY when read FIFO full */
-#define DMM_PAF0 0x00000000 /* Programmable Almost fill level */
-#define DMM_PAF1 0x00000020 /* Programmable Almost fill level */
-#define DMM_PAF2 0x00000040 /* Programmable Almost fill level */
-#define DMM_PAF3 0x00000060 /* Programmable Almost fill level */
-#define DMM_PAF4 0x00000080 /* Programmable Almost fill level */
-#define DMM_PAF5 0x000000A0 /* Programmable Almost fill level */
-#define DMM_PAF6 0x000000C0 /* Programmable Almost fill level */
-#define DMM_PAF7 0x000000D0 /* Programmable Almost fill level */
-#define DMM_MAP 0xFFFF0000 /* Remap Address Bits */
+/* Direct Master Memory Access Enable */
+#define PLX_DMPBAM_MEMACCEN BIT(0)
+/* Direct Master I/O Access Enable */
+#define PLX_DMPBAM_IOACCEN BIT(1)
+/* LLOCK# Input Enable */
+#define PLX_DMPBAM_LLOCKIEN BIT(2)
+/* Direct Master Read Prefetch Size Control (bits 12, 3) */
+#define PLX_DMPBAM_RPSIZECONT ((BIT(12) * 0) | (BIT(3) * 0))
+#define PLX_DMPBAM_RPSIZE4 ((BIT(12) * 0) | (BIT(3) * 1))
+#define PLX_DMPBAM_RPSIZE8 ((BIT(12) * 1) | (BIT(3) * 0))
+#define PLX_DMPBAM_RPSIZE16 ((BIT(12) * 1) | (BIT(3) * 1))
+#define PLX_DMPBAM_RPSIZE_MASK (BIT(12) | BIT(3))
+/* Direct Master PCI Read Mode - deassert IRDY when FIFO full */
+#define PLX_DMPBAM_RMIRDY BIT(4)
+/* Programmable Almost Full Level (bits 10, 8:5) */
+#define PLX_DMPBAM_PAFL(x) ((BIT(10) * !!((x) & 0x10)) | \
+ (BIT(5) * ((x) & 0xf)))
+#define PLX_DMPBAM_TO_PAFL(v) ((((BIT(10) & (v)) >> 1) | \
+ (GENMASK(8, 5) & (v))) >> 5)
+#define PLX_DMPBAM_PAFL_MASK (BIT(10) | GENMASK(8, 5))
+/* Write And Invalidate Mode */
+#define PLX_DMPBAM_WIM BIT(9)
+/* Direct Master Prefetch Limit */
+#define PLX_DBPBAM_PFLIMIT BIT(11)
+/* I/O Remap Select */
+#define PLX_DMPBAM_IOREMAPSEL BIT(13)
+/* Direct Master Write Delay */
+#define PLX_DMPBAM_WDELAYNONE (BIT(14) * 0)
+#define PLX_DMPBAM_WDELAY4 (BIT(14) * 1)
+#define PLX_DMPBAM_WDELAY8 (BIT(14) * 2)
+#define PLX_DMPBAM_WDELAY16 (BIT(14) * 3)
+#define PLX_DMPBAM_WDELAY_MASK GENMASK(15, 14)
+/* Remap of Local-to-PCI Space Into PCI Address Space */
+#define PLX_DMPBAM_REMAP_MASK GENMASK(31, 16)
/* PCI Configuration Address Register for Direct Master to PCI IO/CFG */
#define PLX_REG_DMCFGA 0x002c
--
2.8.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 10/20] staging: comedi: drivers: re-do PLX PCI 9080 DMCFGA register values
2016-05-20 13:49 [PATCH 00/20] staging: comedi: re-do drivers/plx9080.h Ian Abbott
` (8 preceding siblings ...)
2016-05-20 13:49 ` [PATCH 09/20] staging: comedi: drivers: re-do PLX PCI 9080 DMPBAM " Ian Abbott
@ 2016-05-20 13:49 ` Ian Abbott
2016-05-20 13:49 ` [PATCH 11/20] staging: comedi: drivers: re-do PLX PCI 9080 INTCSR " Ian Abbott
` (9 subsequent siblings)
19 siblings, 0 replies; 28+ messages in thread
From: Ian Abbott @ 2016-05-20 13:49 UTC (permalink / raw)
To: devel; +Cc: Greg Kroah-Hartman, Ian Abbott, H Hartley Sweeten, linux-kernel
Replace the existing macros in "plx9080.h" that define values for the
DMCFGA register. Use the prefix `PLX_DMCFGA_` for the macros. Make use
of the `BIT(x)` and `GENMASK(h,l)` macros to define the values.
Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
---
drivers/staging/comedi/drivers/plx9080.h | 29 ++++++++++++++++++++++-------
1 file changed, 22 insertions(+), 7 deletions(-)
diff --git a/drivers/staging/comedi/drivers/plx9080.h b/drivers/staging/comedi/drivers/plx9080.h
index ab90837..e544327 100644
--- a/drivers/staging/comedi/drivers/plx9080.h
+++ b/drivers/staging/comedi/drivers/plx9080.h
@@ -266,13 +266,28 @@ struct plx_dma_desc {
/* PCI Configuration Address Register for Direct Master to PCI IO/CFG */
#define PLX_REG_DMCFGA 0x002c
-#define CAR_CT0 0x00000000 /* Config Type 0 */
-#define CAR_CT1 0x00000001 /* Config Type 1 */
-#define CAR_REG 0x000000FC /* Register Number Bits */
-#define CAR_FUN 0x00000700 /* Function Number Bits */
-#define CAR_DEV 0x0000F800 /* Device Number Bits */
-#define CAR_BUS 0x00FF0000 /* Bus Number Bits */
-#define CAR_CFG 0x80000000 /* Config Spc Access Enable */
+/* Congiguration Type */
+#define PLX_DMCFGA_TYPE0 (BIT(0) * 0)
+#define PLX_DMCFGA_TYPE1 (BIT(0) * 1)
+#define PLX_DMCFGA_TYPE_MASK GENMASK(1, 0)
+/* Register Number */
+#define PLX_DMCFGA_REGNUM(x) (BIT(2) * ((x) & 0x3f))
+#define PLX_DMCFGA_REGNUM_MASK GENMASK(7, 2)
+#define PLX_DMCFGA_REGNUM_SHIFT 2
+/* Function Number */
+#define PLX_DMCFGA_FUNCNUM(x) (BIT(8) * ((x) & 0x7))
+#define PLX_DMCFGA_FUNCNUM_MASK GENMASK(10, 8)
+#define PLX_DMCFGA_FUNCNUM_SHIFT 8
+/* Device Number */
+#define PLX_DMCFGA_DEVNUM(x) (BIT(11) * ((x) & 0x1f))
+#define PLX_DMCFGA_DEVNUM_MASK GENMASK(15, 11)
+#define PLX_DMCFGA_DEVNUM_SHIFT 11
+/* Bus Number */
+#define PLX_DMCFGA_BUSNUM(x) (BIT(16) * ((x) & 0xff))
+#define PLX_DMCFGA_BUSNUM_MASK GENMASK(23, 16)
+#define PLX_DMCFGA_BUSNUM_SHIFT 16
+/* Configuration Enable */
+#define PLX_DMCFGA_CONFIGEN BIT(31)
/*
* Mailbox Register N (N <= 7)
--
2.8.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 11/20] staging: comedi: drivers: re-do PLX PCI 9080 INTCSR register values
2016-05-20 13:49 [PATCH 00/20] staging: comedi: re-do drivers/plx9080.h Ian Abbott
` (9 preceding siblings ...)
2016-05-20 13:49 ` [PATCH 10/20] staging: comedi: drivers: re-do PLX PCI 9080 DMCFGA " Ian Abbott
@ 2016-05-20 13:49 ` Ian Abbott
2016-05-20 13:49 ` [PATCH 12/20] staging: comedi: drivers: re-do PLX PCI 9080 CNTRL " Ian Abbott
` (8 subsequent siblings)
19 siblings, 0 replies; 28+ messages in thread
From: Ian Abbott @ 2016-05-20 13:49 UTC (permalink / raw)
To: devel; +Cc: Greg Kroah-Hartman, Ian Abbott, H Hartley Sweeten, linux-kernel
Replace the existing macros in "plx9080.h" that define values for the
INTCSR register. Use the prefix `PLX_INTCSR_` for the macros. Make use
of the `BIT(x)` and `GENMASK(h,l)` macros to define the values.
Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
---
drivers/staging/comedi/drivers/cb_pcidas64.c | 14 +++--
drivers/staging/comedi/drivers/gsc_hpdi.c | 14 +++--
drivers/staging/comedi/drivers/plx9080.h | 91 ++++++++++++++++++++--------
drivers/staging/comedi/drivers/rtd520.c | 3 +-
4 files changed, 83 insertions(+), 39 deletions(-)
diff --git a/drivers/staging/comedi/drivers/cb_pcidas64.c b/drivers/staging/comedi/drivers/cb_pcidas64.c
index 4a8e88a..6b3f4dc 100644
--- a/drivers/staging/comedi/drivers/cb_pcidas64.c
+++ b/drivers/staging/comedi/drivers/cb_pcidas64.c
@@ -1336,8 +1336,9 @@ static void init_plx9080(struct comedi_device *dev)
/* enable interrupts on plx 9080 */
devpriv->plx_intcsr_bits |=
- ICS_AERR | ICS_PERR | ICS_PIE | ICS_PLIE | ICS_PAIE | ICS_LIE |
- ICS_DMA0_E | ICS_DMA1_E;
+ PLX_INTCSR_LSEABORTEN | PLX_INTCSR_LSEPARITYEN | PLX_INTCSR_PIEN |
+ PLX_INTCSR_PLIEN | PLX_INTCSR_PABORTIEN | PLX_INTCSR_LIOEN |
+ PLX_INTCSR_DMA0IEN | PLX_INTCSR_DMA1IEN;
writel(devpriv->plx_intcsr_bits,
devpriv->plx9080_iobase + PLX_REG_INTCSR);
}
@@ -2836,7 +2837,7 @@ static void handle_ai_interrupt(struct comedi_device *dev,
/* spin lock makes sure no one else changes plx dma control reg */
spin_lock_irqsave(&dev->spinlock, flags);
dma1_status = readb(devpriv->plx9080_iobase + PLX_REG_DMACSR1);
- if (plx_status & ICS_DMA1_A) { /* dma chan 1 interrupt */
+ if (plx_status & PLX_INTCSR_DMA1IA) { /* dma chan 1 interrupt */
writeb((dma1_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
devpriv->plx9080_iobase + PLX_REG_DMACSR1);
@@ -3014,7 +3015,7 @@ static void handle_ao_interrupt(struct comedi_device *dev,
/* spin lock makes sure no one else changes plx dma control reg */
spin_lock_irqsave(&dev->spinlock, flags);
dma0_status = readb(devpriv->plx9080_iobase + PLX_REG_DMACSR0);
- if (plx_status & ICS_DMA0_A) { /* dma chan 0 interrupt */
+ if (plx_status & PLX_INTCSR_DMA0IA) { /* dma chan 0 interrupt */
if ((dma0_status & PLX_DMA_EN_BIT) &&
!(dma0_status & PLX_DMA_DONE_BIT)) {
writeb(PLX_DMA_EN_BIT | PLX_CLEAR_DMA_INTR_BIT,
@@ -3067,8 +3068,9 @@ static irqreturn_t handle_interrupt(int irq, void *d)
handle_ai_interrupt(dev, status, plx_status);
handle_ao_interrupt(dev, status, plx_status);
- /* clear possible plx9080 interrupt sources */
- if (plx_status & ICS_LDIA) { /* clear local doorbell interrupt */
+ /* clear possible plx9080 interrupt sources */
+ if (plx_status & PLX_INTCSR_LDBIA) {
+ /* clear local doorbell interrupt */
plx_bits = readl(devpriv->plx9080_iobase + PLX_REG_L2PDBELL);
writel(plx_bits, devpriv->plx9080_iobase + PLX_REG_L2PDBELL);
}
diff --git a/drivers/staging/comedi/drivers/gsc_hpdi.c b/drivers/staging/comedi/drivers/gsc_hpdi.c
index 536bebe..e288798 100644
--- a/drivers/staging/comedi/drivers/gsc_hpdi.c
+++ b/drivers/staging/comedi/drivers/gsc_hpdi.c
@@ -199,7 +199,8 @@ static irqreturn_t gsc_hpdi_interrupt(int irq, void *d)
return IRQ_NONE;
plx_status = readl(devpriv->plx9080_mmio + PLX_REG_INTCSR);
- if ((plx_status & (ICS_DMA0_A | ICS_DMA1_A | ICS_LIA)) == 0)
+ if ((plx_status &
+ (PLX_INTCSR_DMA0IA | PLX_INTCSR_DMA1IA | PLX_INTCSR_PLIA)) == 0)
return IRQ_NONE;
hpdi_intr_status = readl(dev->mmio + INTERRUPT_STATUS_REG);
@@ -211,7 +212,7 @@ static irqreturn_t gsc_hpdi_interrupt(int irq, void *d)
/* spin lock makes sure no one else changes plx dma control reg */
spin_lock_irqsave(&dev->spinlock, flags);
dma0_status = readb(devpriv->plx9080_mmio + PLX_REG_DMACSR0);
- if (plx_status & ICS_DMA0_A) {
+ if (plx_status & PLX_INTCSR_DMA0IA) {
/* dma chan 0 interrupt */
writeb((dma0_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
devpriv->plx9080_mmio + PLX_REG_DMACSR0);
@@ -224,7 +225,7 @@ static irqreturn_t gsc_hpdi_interrupt(int irq, void *d)
/* spin lock makes sure no one else changes plx dma control reg */
spin_lock_irqsave(&dev->spinlock, flags);
dma1_status = readb(devpriv->plx9080_mmio + PLX_REG_DMACSR1);
- if (plx_status & ICS_DMA1_A) {
+ if (plx_status & PLX_INTCSR_DMA1IA) {
/* XXX */ /* dma chan 1 interrupt */
writeb((dma1_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
devpriv->plx9080_mmio + PLX_REG_DMACSR1);
@@ -232,7 +233,7 @@ static irqreturn_t gsc_hpdi_interrupt(int irq, void *d)
spin_unlock_irqrestore(&dev->spinlock, flags);
/* clear possible plx9080 interrupt sources */
- if (plx_status & ICS_LDIA) {
+ if (plx_status & PLX_INTCSR_LDBIA) {
/* clear local doorbell interrupt */
plx_bits = readl(devpriv->plx9080_mmio + PLX_REG_L2PDBELL);
writel(plx_bits, devpriv->plx9080_mmio + PLX_REG_L2PDBELL);
@@ -533,8 +534,9 @@ static int gsc_hpdi_init(struct comedi_device *dev)
/* enable interrupts */
plx_intcsr_bits =
- ICS_AERR | ICS_PERR | ICS_PIE | ICS_PLIE | ICS_PAIE | ICS_LIE |
- ICS_DMA0_E;
+ PLX_INTCSR_LSEABORTEN | PLX_INTCSR_LSEPARITYEN | PLX_INTCSR_PIEN |
+ PLX_INTCSR_PLIEN | PLX_INTCSR_PABORTIEN | PLX_INTCSR_LIOEN |
+ PLX_INTCSR_DMA0IEN;
writel(plx_intcsr_bits, devpriv->plx9080_mmio + PLX_REG_INTCSR);
return 0;
diff --git a/drivers/staging/comedi/drivers/plx9080.h b/drivers/staging/comedi/drivers/plx9080.h
index e544327..e9f1b9c 100644
--- a/drivers/staging/comedi/drivers/plx9080.h
+++ b/drivers/staging/comedi/drivers/plx9080.h
@@ -321,32 +321,71 @@ struct plx_dma_desc {
/* Interrupt Control/Status Register */
#define PLX_REG_INTCSR 0x0068
-#define ICS_AERR 0x00000001 /* Assert LSERR on ABORT */
-#define ICS_PERR 0x00000002 /* Assert LSERR on Parity Error */
-#define ICS_SERR 0x00000004 /* Generate PCI SERR# */
-#define ICS_MBIE 0x00000008 /* mailbox interrupt enable */
-#define ICS_PIE 0x00000100 /* PCI Interrupt Enable */
-#define ICS_PDIE 0x00000200 /* PCI Doorbell Interrupt Enable */
-#define ICS_PAIE 0x00000400 /* PCI Abort Interrupt Enable */
-#define ICS_PLIE 0x00000800 /* PCI Local Int Enable */
-#define ICS_RAE 0x00001000 /* Retry Abort Enable */
-#define ICS_PDIA 0x00002000 /* PCI Doorbell Interrupt Active */
-#define ICS_PAIA 0x00004000 /* PCI Abort Interrupt Active */
-#define ICS_LIA 0x00008000 /* Local Interrupt Active */
-#define ICS_LIE 0x00010000 /* Local Interrupt Enable */
-#define ICS_LDIE 0x00020000 /* Local Doorbell Int Enable */
-#define ICS_DMA0_E 0x00040000 /* DMA #0 Interrupt Enable */
-#define ICS_DMA1_E 0x00080000 /* DMA #1 Interrupt Enable */
-#define ICS_LDIA 0x00100000 /* Local Doorbell Int Active */
-#define ICS_DMA0_A 0x00200000 /* DMA #0 Interrupt Active */
-#define ICS_DMA1_A 0x00400000 /* DMA #1 Interrupt Active */
-#define ICS_BIA 0x00800000 /* BIST Interrupt Active */
-#define ICS_TA_DM 0x01000000 /* Target Abort - Direct Master */
-#define ICS_TA_DMA0 0x02000000 /* Target Abort - DMA #0 */
-#define ICS_TA_DMA1 0x04000000 /* Target Abort - DMA #1 */
-#define ICS_TA_RA 0x08000000 /* Target Abort - Retry Timeout */
-/* mailbox x is active */
-#define ICS_MBIA(x) (0x10000000 << ((x) & 0x3))
+/* Enable Local Bus LSERR# when PCI Bus Target Abort or Master Abort occurs */
+#define PLX_INTCSR_LSEABORTEN BIT(0)
+/* Enable Local Bus LSERR# when PCI parity error occurs */
+#define PLX_INTCSR_LSEPARITYEN BIT(1)
+/* Generate PCI Bus SERR# when set to 1 */
+#define PLX_INTCSR_GENSERR BIT(2)
+/* Mailbox Interrupt Enable (local bus interrupts on PCI write to MBOX0-3) */
+#define PLX_INTCSR_MBIEN BIT(3)
+/* PCI Interrupt Enable */
+#define PLX_INTCSR_PIEN BIT(8)
+/* PCI Doorbell Interrupt Enable */
+#define PLX_INTCSR_PDBIEN BIT(9)
+/* PCI Abort Interrupt Enable */
+#define PLX_INTCSR_PABORTIEN BIT(10)
+/* PCI Local Interrupt Enable */
+#define PLX_INTCSR_PLIEN BIT(11)
+/* Retry Abort Enable (for diagnostic purposes only) */
+#define PLX_INTCSR_RAEN BIT(12)
+/* PCI Doorbell Interrupt Active (read-only) */
+#define PLX_INTCSR_PDBIA BIT(13)
+/* PCI Abort Interrupt Active (read-only) */
+#define PLX_INTCSR_PABORTIA BIT(14)
+/* Local Interrupt (LINTi#) Active (read-only) */
+#define PLX_INTCSR_PLIA BIT(15)
+/* Local Interrupt Output (LINTo#) Enable */
+#define PLX_INTCSR_LIOEN BIT(16)
+/* Local Doorbell Interrupt Enable */
+#define PLX_INTCSR_LDBIEN BIT(17)
+/* DMA Channel 0 Interrupt Enable */
+#define PLX_INTCSR_DMA0IEN BIT(18)
+/* DMA Channel 1 Interrupt Enable */
+#define PLX_INTCSR_DMA1IEN BIT(19)
+/* DMA Channel N Interrupt Enable (N <= 1) */
+#define PLX_INTCSR_DMAIEN(n) ((n) ? PLX_INTCSR_DMA1IEN : PLX_INTCSR_DMA0IEN)
+/* Local Doorbell Interrupt Active (read-only) */
+#define PLX_INTCSR_LDBIA BIT(20)
+/* DMA Channel 0 Interrupt Active (read-only) */
+#define PLX_INTCSR_DMA0IA BIT(21)
+/* DMA Channel 1 Interrupt Active (read-only) */
+#define PLX_INTCSR_DMA1IA BIT(22)
+/* DMA Channel N Interrupt Active (N <= 1) (read-only) */
+#define PLX_INTCSR_DMAIA(n) ((n) ? PLX_INTCSR_DMA1IA : PLX_INTCSR_DMA0IA)
+/* BIST Interrupt Active (read-only) */
+#define PLX_INTCSR_BISTIA BIT(23)
+/* Direct Master Not Bus Master During Master Or Target Abort (read-only) */
+#define PLX_INTCSR_ABNOTDM BIT(24)
+/* DMA Channel 0 Not Bus Master During Master Or Target Abort (read-only) */
+#define PLX_INTCSR_ABNOTDMA0 BIT(25)
+/* DMA Channel 1 Not Bus Master During Master Or Target Abort (read-only) */
+#define PLX_INTCSR_ABNOTDMA1 BIT(26)
+/* DMA Channel N Not Bus Master During Master Or Target Abort (read-only) */
+#define PLX_INTCSR_ABNOTDMA(n) ((n) ? PLX_INTCSR_ABNOTDMA1 \
+ : PLX_INTCSR_ABNOTDMA0)
+/* Target Abort Not Generated After 256 Master Retries (read-only) */
+#define PLX_INTCSR_ABNOTRETRY BIT(27)
+/* PCI Wrote Mailbox 0 (enabled if bit 3 set) (read-only) */
+#define PLX_INTCSR_MB0IA BIT(28)
+/* PCI Wrote Mailbox 1 (enabled if bit 3 set) (read-only) */
+#define PLX_INTCSR_MB1IA BIT(29)
+/* PCI Wrote Mailbox 2 (enabled if bit 3 set) (read-only) */
+#define PLX_INTCSR_MB2IA BIT(30)
+/* PCI Wrote Mailbox 3 (enabled if bit 3 set) (read-only) */
+#define PLX_INTCSR_MB3IA BIT(31)
+/* PCI Wrote Mailbox N (N <= 3) (enabled if bit 3 set) (read-only) */
+#define PLX_INTCSR_MBIA(n) BIT(28 + (n))
/*
* Serial EEPROM Control, PCI Command Codes, User I/O Control,
diff --git a/drivers/staging/comedi/drivers/rtd520.c b/drivers/staging/comedi/drivers/rtd520.c
index 5a4464e..b472427 100644
--- a/drivers/staging/comedi/drivers/rtd520.c
+++ b/drivers/staging/comedi/drivers/rtd520.c
@@ -1316,7 +1316,8 @@ static int rtd_auto_attach(struct comedi_device *dev,
devpriv->fifosz = ret;
if (dev->irq)
- writel(ICS_PIE | ICS_PLIE, devpriv->lcfg + PLX_REG_INTCSR);
+ writel(PLX_INTCSR_PIEN | PLX_INTCSR_PLIEN,
+ devpriv->lcfg + PLX_REG_INTCSR);
return 0;
}
--
2.8.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 12/20] staging: comedi: drivers: re-do PLX PCI 9080 CNTRL register values
2016-05-20 13:49 [PATCH 00/20] staging: comedi: re-do drivers/plx9080.h Ian Abbott
` (10 preceding siblings ...)
2016-05-20 13:49 ` [PATCH 11/20] staging: comedi: drivers: re-do PLX PCI 9080 INTCSR " Ian Abbott
@ 2016-05-20 13:49 ` Ian Abbott
2016-05-20 13:49 ` [PATCH 13/20] staging: comedi: plx9080.h: add hard-coded PCIHIDR register value Ian Abbott
` (7 subsequent siblings)
19 siblings, 0 replies; 28+ messages in thread
From: Ian Abbott @ 2016-05-20 13:49 UTC (permalink / raw)
To: devel; +Cc: Greg Kroah-Hartman, Ian Abbott, H Hartley Sweeten, linux-kernel
Replace the existing macros in "plx9080.h" that define values for the
CNTRL register. Use the prefix `PLX_CNTRL_` for the macros. Make use
of the `BIT(x)` and `GENMASK(h,l)` macros to define the values.
Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
---
drivers/staging/comedi/drivers/cb_pcidas64.c | 31 +++++++-------
drivers/staging/comedi/drivers/plx9080.h | 63 +++++++++++++++++++++-------
2 files changed, 65 insertions(+), 29 deletions(-)
diff --git a/drivers/staging/comedi/drivers/cb_pcidas64.c b/drivers/staging/comedi/drivers/cb_pcidas64.c
index 6b3f4dc..dfb2ae8 100644
--- a/drivers/staging/comedi/drivers/cb_pcidas64.c
+++ b/drivers/staging/comedi/drivers/cb_pcidas64.c
@@ -1614,7 +1614,7 @@ static const int i2c_low_udelay = 10;
static void i2c_set_sda(struct comedi_device *dev, int state)
{
struct pcidas64_private *devpriv = dev->private;
- static const int data_bit = CTL_EE_W;
+ static const int data_bit = PLX_CNTRL_EEWB;
void __iomem *plx_control_addr = devpriv->plx9080_iobase +
PLX_REG_CNTRL;
@@ -1635,7 +1635,7 @@ static void i2c_set_sda(struct comedi_device *dev, int state)
static void i2c_set_scl(struct comedi_device *dev, int state)
{
struct pcidas64_private *devpriv = dev->private;
- static const int clock_bit = CTL_USERO;
+ static const int clock_bit = PLX_CNTRL_USERO;
void __iomem *plx_control_addr = devpriv->plx9080_iobase +
PLX_REG_CNTRL;
@@ -1708,7 +1708,7 @@ static void i2c_write(struct comedi_device *dev, unsigned int address,
*/
/* make sure we dont send anything to eeprom */
- devpriv->plx_control_bits &= ~CTL_EE_CS;
+ devpriv->plx_control_bits &= ~PLX_CNTRL_EECS;
i2c_stop(dev);
i2c_start(dev);
@@ -3717,13 +3717,13 @@ static uint16_t read_eeprom(struct comedi_device *dev, uint8_t address)
static const int eeprom_udelay = 1;
udelay(eeprom_udelay);
- devpriv->plx_control_bits &= ~CTL_EE_CLK & ~CTL_EE_CS;
+ devpriv->plx_control_bits &= ~PLX_CNTRL_EESK & ~PLX_CNTRL_EECS;
/* make sure we don't send anything to the i2c bus on 4020 */
- devpriv->plx_control_bits |= CTL_USERO;
+ devpriv->plx_control_bits |= PLX_CNTRL_USERO;
writel(devpriv->plx_control_bits, plx_control_addr);
/* activate serial eeprom */
udelay(eeprom_udelay);
- devpriv->plx_control_bits |= CTL_EE_CS;
+ devpriv->plx_control_bits |= PLX_CNTRL_EECS;
writel(devpriv->plx_control_bits, plx_control_addr);
/* write read command and desired memory address */
@@ -3731,16 +3731,16 @@ static uint16_t read_eeprom(struct comedi_device *dev, uint8_t address)
/* set bit to be written */
udelay(eeprom_udelay);
if (bitstream & bit)
- devpriv->plx_control_bits |= CTL_EE_W;
+ devpriv->plx_control_bits |= PLX_CNTRL_EEWB;
else
- devpriv->plx_control_bits &= ~CTL_EE_W;
+ devpriv->plx_control_bits &= ~PLX_CNTRL_EEWB;
writel(devpriv->plx_control_bits, plx_control_addr);
/* clock in bit */
udelay(eeprom_udelay);
- devpriv->plx_control_bits |= CTL_EE_CLK;
+ devpriv->plx_control_bits |= PLX_CNTRL_EESK;
writel(devpriv->plx_control_bits, plx_control_addr);
udelay(eeprom_udelay);
- devpriv->plx_control_bits &= ~CTL_EE_CLK;
+ devpriv->plx_control_bits &= ~PLX_CNTRL_EESK;
writel(devpriv->plx_control_bits, plx_control_addr);
}
/* read back value from eeprom memory location */
@@ -3748,19 +3748,19 @@ static uint16_t read_eeprom(struct comedi_device *dev, uint8_t address)
for (bit = 1 << (value_length - 1); bit; bit >>= 1) {
/* clock out bit */
udelay(eeprom_udelay);
- devpriv->plx_control_bits |= CTL_EE_CLK;
+ devpriv->plx_control_bits |= PLX_CNTRL_EESK;
writel(devpriv->plx_control_bits, plx_control_addr);
udelay(eeprom_udelay);
- devpriv->plx_control_bits &= ~CTL_EE_CLK;
+ devpriv->plx_control_bits &= ~PLX_CNTRL_EESK;
writel(devpriv->plx_control_bits, plx_control_addr);
udelay(eeprom_udelay);
- if (readl(plx_control_addr) & CTL_EE_R)
+ if (readl(plx_control_addr) & PLX_CNTRL_EERB)
value |= bit;
}
/* deactivate eeprom serial input */
udelay(eeprom_udelay);
- devpriv->plx_control_bits &= ~CTL_EE_CS;
+ devpriv->plx_control_bits &= ~PLX_CNTRL_EECS;
writel(devpriv->plx_control_bits, plx_control_addr);
return value;
@@ -3948,7 +3948,8 @@ static int setup_subdevices(struct comedi_device *dev)
/* serial EEPROM, if present */
s = &dev->subdevices[8];
- if (readl(devpriv->plx9080_iobase + PLX_REG_CNTRL) & CTL_EECHK) {
+ if (readl(devpriv->plx9080_iobase + PLX_REG_CNTRL) &
+ PLX_CNTRL_EEPRESENT) {
s->type = COMEDI_SUBD_MEMORY;
s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
s->n_chan = 128;
diff --git a/drivers/staging/comedi/drivers/plx9080.h b/drivers/staging/comedi/drivers/plx9080.h
index e9f1b9c..4ad9464 100644
--- a/drivers/staging/comedi/drivers/plx9080.h
+++ b/drivers/staging/comedi/drivers/plx9080.h
@@ -393,20 +393,55 @@ struct plx_dma_desc {
*/
#define PLX_REG_CNTRL 0x006c
-#define CTL_RDMA 0x0000000E /* DMA Read Command */
-#define CTL_WDMA 0x00000070 /* DMA Write Command */
-#define CTL_RMEM 0x00000600 /* Memory Read Command */
-#define CTL_WMEM 0x00007000 /* Memory Write Command */
-#define CTL_USERO 0x00010000 /* USERO output pin control bit */
-#define CTL_USERI 0x00020000 /* USERI input pin bit */
-#define CTL_EE_CLK 0x01000000 /* EEPROM Clock line */
-#define CTL_EE_CS 0x02000000 /* EEPROM Chip Select */
-#define CTL_EE_W 0x04000000 /* EEPROM Write bit */
-#define CTL_EE_R 0x08000000 /* EEPROM Read bit */
-#define CTL_EECHK 0x10000000 /* EEPROM Present bit */
-#define CTL_EERLD 0x20000000 /* EEPROM Reload Register */
-#define CTL_RESET 0x40000000 /* !! Adapter Reset !! */
-#define CTL_READY 0x80000000 /* Local Init Done */
+/* PCI Read Command Code For DMA */
+#define PLX_CNTRL_CCRDMA(x) (BIT(0) * ((x) & 0xf))
+#define PLX_CNTRL_CCRDMA_MASK GENMASK(3, 0)
+#define PLX_CNTRL_CCRDMA_SHIFT 0
+#define PLX_CNTRL_CCRDMA_NORMAL PLX_CNTRL_CCRDMA(14) /* value after reset */
+/* PCI Write Command Code For DMA 0 */
+#define PLX_CNTRL_CCWDMA(x) (BIT(4) * ((x) & 0xf))
+#define PLX_CNTRL_CCWDMA_MASK GENMASK(7, 4)
+#define PLX_CNTRL_CCWDMA_SHIFT 4
+#define PLX_CNTRL_CCWDMA_NORMAL PLX_CNTRL_CCWDMA(7) /* value after reset */
+/* PCI Memory Read Command Code For Direct Master */
+#define PLX_CNTRL_CCRDM(x) (BIT(8) * ((x) & 0xf))
+#define PLX_CNTRL_CCRDM_MASK GENMASK(11, 8)
+#define PLX_CNTRL_CCRDM_SHIFT 8
+#define PLX_CNTRL_CCRDM_NORMAL PLX_CNTRL_CCRDM(6) /* value after reset */
+/* PCI Memory Write Command Code For Direct Master */
+#define PLX_CNTRL_CCWDM(x) (BIT(12) * ((x) & 0xf))
+#define PLX_CNTRL_CCWDM_MASK GENMASK(15, 12)
+#define PLX_CNTRL_CCWDM_SHIFT 12
+#define PLX_CNTRL_CCWDM_NORMAL PLX_CNTRL_CCWDM(7) /* value after reset */
+/* General Purpose Output (USERO) */
+#define PLX_CNTRL_USERO BIT(16)
+/* General Purpose Input (USERI) (read-only) */
+#define PLX_CNTRL_USERI BIT(17)
+/* Serial EEPROM Clock Output (EESK) */
+#define PLX_CNTRL_EESK BIT(24)
+/* Serial EEPROM Chip Select Output (EECS) */
+#define PLX_CNTRL_EECS BIT(25)
+/* Serial EEPROM Data Write Bit (EEDI (sic)) */
+#define PLX_CNTRL_EEWB BIT(26)
+/* Serial EEPROM Data Read Bit (EEDO (sic)) (read-only) */
+#define PLX_CNTRL_EERB BIT(27)
+/* Serial EEPROM Present (read-only) */
+#define PLX_CNTRL_EEPRESENT BIT(28)
+/* Reload Configuration Registers from EEPROM */
+#define PLX_CNTRL_EERELOAD BIT(29)
+/* PCI Adapter Software Reset (asserts LRESETo#) */
+#define PLX_CNTRL_RESET BIT(30)
+/* Local Init Status (read-only) */
+#define PLX_CNTRL_INITDONE BIT(31)
+/*
+ * Combined command code stuff for convenience.
+ */
+#define PLX_CNTRL_CC_MASK \
+ (PLX_CNTRL_CCRDMA_MASK | PLX_CNTRL_CCWDMA_MASK | \
+ PLX_CNTRL_CCRDM_MASK | PLX_CNTRL_CCWDM_MASK)
+#define PLX_CNTRL_CC_NORMAL \
+ (PLX_CNTRL_CCRDMA_NORMAL | PLX_CNTRL_CCWDMA_NORMAL | \
+ PLX_CNTRL_CCRDM_NORMAL | PLX_CNTRL_CCWDM_NORMAL) /* val after reset */
/* PCI Permanent Configuration ID Register (hard-coded PLX vendor and device) */
#define PLX_REG_PCIHIDR 0x0070
--
2.8.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 13/20] staging: comedi: plx9080.h: add hard-coded PCIHIDR register value
2016-05-20 13:49 [PATCH 00/20] staging: comedi: re-do drivers/plx9080.h Ian Abbott
` (11 preceding siblings ...)
2016-05-20 13:49 ` [PATCH 12/20] staging: comedi: drivers: re-do PLX PCI 9080 CNTRL " Ian Abbott
@ 2016-05-20 13:49 ` Ian Abbott
2016-05-20 13:49 ` [PATCH 14/20] staging: comedi: drivers: re-do PLX PCI 9080 DMAMODEx register values Ian Abbott
` (6 subsequent siblings)
19 siblings, 0 replies; 28+ messages in thread
From: Ian Abbott @ 2016-05-20 13:49 UTC (permalink / raw)
To: devel; +Cc: Greg Kroah-Hartman, Ian Abbott, H Hartley Sweeten, linux-kernel
For the PLX PCI 9080, the read-only PCIHIDR register is hard-coded with
the value `0x908010b5`. Add a macro `PLX_PCIHIDR_9080` that expands to
this value.
Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
---
drivers/staging/comedi/drivers/plx9080.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/staging/comedi/drivers/plx9080.h b/drivers/staging/comedi/drivers/plx9080.h
index 4ad9464..c70af5e 100644
--- a/drivers/staging/comedi/drivers/plx9080.h
+++ b/drivers/staging/comedi/drivers/plx9080.h
@@ -446,6 +446,9 @@ struct plx_dma_desc {
/* PCI Permanent Configuration ID Register (hard-coded PLX vendor and device) */
#define PLX_REG_PCIHIDR 0x0070
+/* Hard-coded ID for PLX PCI 9080 */
+#define PLX_PCIHIDR_9080 0x908010b5
+
/* PCI Permanent Revision ID Register (hard-coded silicon revision) (8-bit). */
#define PLX_REG_PCIHREV 0x0074
--
2.8.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 14/20] staging: comedi: drivers: re-do PLX PCI 9080 DMAMODEx register values
2016-05-20 13:49 [PATCH 00/20] staging: comedi: re-do drivers/plx9080.h Ian Abbott
` (12 preceding siblings ...)
2016-05-20 13:49 ` [PATCH 13/20] staging: comedi: plx9080.h: add hard-coded PCIHIDR register value Ian Abbott
@ 2016-05-20 13:49 ` Ian Abbott
2016-05-20 13:49 ` [PATCH 15/20] staging: comedi: drivers: re-do PLX PCI 9080 DMADPRx " Ian Abbott
` (5 subsequent siblings)
19 siblings, 0 replies; 28+ messages in thread
From: Ian Abbott @ 2016-05-20 13:49 UTC (permalink / raw)
To: devel; +Cc: Greg Kroah-Hartman, Ian Abbott, H Hartley Sweeten, linux-kernel
Replace the existing macros in "plx9080.h" that define values for the
DMAMODE0 and DMAMODE1 registers. Use the prefix `PLX_DMAMODE_` for the
macros. Make use of the `BIT(x)` and `GENMASK(h,l)` macros to define
the values.
Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
---
drivers/staging/comedi/drivers/cb_pcidas64.c | 20 +++++------
drivers/staging/comedi/drivers/gsc_hpdi.c | 16 ++++-----
drivers/staging/comedi/drivers/plx9080.h | 52 +++++++++++++++++++---------
3 files changed, 53 insertions(+), 35 deletions(-)
diff --git a/drivers/staging/comedi/drivers/cb_pcidas64.c b/drivers/staging/comedi/drivers/cb_pcidas64.c
index dfb2ae8..48aca06 100644
--- a/drivers/staging/comedi/drivers/cb_pcidas64.c
+++ b/drivers/staging/comedi/drivers/cb_pcidas64.c
@@ -1308,28 +1308,28 @@ static void init_plx9080(struct comedi_device *dev)
/* configure dma0 mode */
bits = 0;
/* enable ready input, not sure if this is necessary */
- bits |= PLX_DMA_EN_READYIN_BIT;
+ bits |= PLX_DMAMODE_READYIEN;
/* enable bterm, not sure if this is necessary */
- bits |= PLX_EN_BTERM_BIT;
+ bits |= PLX_DMAMODE_BTERMIEN;
/* enable dma chaining */
- bits |= PLX_EN_CHAIN_BIT;
+ bits |= PLX_DMAMODE_CHAINEN;
/* enable interrupt on dma done
* (probably don't need this, since chain never finishes) */
- bits |= PLX_EN_DMA_DONE_INTR_BIT;
+ bits |= PLX_DMAMODE_DONEIEN;
/* don't increment local address during transfers
* (we are transferring from a fixed fifo register) */
- bits |= PLX_LOCAL_ADDR_CONST_BIT;
+ bits |= PLX_DMAMODE_LACONST;
/* route dma interrupt to pci bus */
- bits |= PLX_DMA_INTR_PCI_BIT;
+ bits |= PLX_DMAMODE_INTRPCI;
/* enable demand mode */
- bits |= PLX_DEMAND_MODE_BIT;
+ bits |= PLX_DMAMODE_DEMAND;
/* enable local burst mode */
- bits |= PLX_DMA_LOCAL_BURST_EN_BIT;
+ bits |= PLX_DMAMODE_BURSTEN;
/* 4020 uses 32 bit dma */
if (board->layout == LAYOUT_4020)
- bits |= PLX_LOCAL_BUS_32_WIDE_BITS;
+ bits |= PLX_DMAMODE_WIDTH32;
else /* localspace0 bus is 16 bits wide */
- bits |= PLX_LOCAL_BUS_16_WIDE_BITS;
+ bits |= PLX_DMAMODE_WIDTH16;
writel(bits, plx_iobase + PLX_REG_DMAMODE1);
if (ao_cmd_is_supported(board))
writel(bits, plx_iobase + PLX_REG_DMAMODE0);
diff --git a/drivers/staging/comedi/drivers/gsc_hpdi.c b/drivers/staging/comedi/drivers/gsc_hpdi.c
index e288798..d63dc46 100644
--- a/drivers/staging/comedi/drivers/gsc_hpdi.c
+++ b/drivers/staging/comedi/drivers/gsc_hpdi.c
@@ -563,26 +563,26 @@ static void gsc_hpdi_init_plx9080(struct comedi_device *dev)
/* configure dma0 mode */
bits = 0;
/* enable ready input */
- bits |= PLX_DMA_EN_READYIN_BIT;
+ bits |= PLX_DMAMODE_READYIEN;
/* enable dma chaining */
- bits |= PLX_EN_CHAIN_BIT;
+ bits |= PLX_DMAMODE_CHAINEN;
/*
* enable interrupt on dma done
* (probably don't need this, since chain never finishes)
*/
- bits |= PLX_EN_DMA_DONE_INTR_BIT;
+ bits |= PLX_DMAMODE_DONEIEN;
/*
* don't increment local address during transfers
* (we are transferring from a fixed fifo register)
*/
- bits |= PLX_LOCAL_ADDR_CONST_BIT;
+ bits |= PLX_DMAMODE_LACONST;
/* route dma interrupt to pci bus */
- bits |= PLX_DMA_INTR_PCI_BIT;
+ bits |= PLX_DMAMODE_INTRPCI;
/* enable demand mode */
- bits |= PLX_DEMAND_MODE_BIT;
+ bits |= PLX_DMAMODE_DEMAND;
/* enable local burst mode */
- bits |= PLX_DMA_LOCAL_BURST_EN_BIT;
- bits |= PLX_LOCAL_BUS_32_WIDE_BITS;
+ bits |= PLX_DMAMODE_BURSTEN;
+ bits |= PLX_DMAMODE_WIDTH32;
writel(bits, plx_iobase + PLX_REG_DMAMODE0);
}
diff --git a/drivers/staging/comedi/drivers/plx9080.h b/drivers/staging/comedi/drivers/plx9080.h
index c70af5e..99c075c 100644
--- a/drivers/staging/comedi/drivers/plx9080.h
+++ b/drivers/staging/comedi/drivers/plx9080.h
@@ -457,23 +457,41 @@ struct plx_dma_desc {
#define PLX_REG_DMAMODE0 0x0080
#define PLX_REG_DMAMODE1 0x0094
-#define PLX_LOCAL_BUS_16_WIDE_BITS 0x1
-#define PLX_LOCAL_BUS_32_WIDE_BITS 0x3
-#define PLX_LOCAL_BUS_WIDTH_MASK 0x3
-#define PLX_DMA_EN_READYIN_BIT 0x40 /* enable ready in input */
-#define PLX_EN_BTERM_BIT 0x80 /* enable BTERM# input */
-#define PLX_DMA_LOCAL_BURST_EN_BIT 0x100 /* enable local burst mode */
-#define PLX_EN_CHAIN_BIT 0x200 /* enables chaining */
-/* enables interrupt on dma done */
-#define PLX_EN_DMA_DONE_INTR_BIT 0x400
-/* hold local address constant (don't increment) */
-#define PLX_LOCAL_ADDR_CONST_BIT 0x800
-/* enables demand-mode for dma transfer */
-#define PLX_DEMAND_MODE_BIT 0x1000
-#define PLX_EOT_ENABLE_BIT 0x4000
-#define PLX_STOP_MODE_BIT 0x8000
-/* routes dma interrupt to pci bus (instead of local bus) */
-#define PLX_DMA_INTR_PCI_BIT 0x20000
+/* Local Bus Width */
+#define PLX_DMAMODE_WIDTH8 (BIT(0) * 0) /* 8 bits wide */
+#define PLX_DMAMODE_WIDTH16 (BIT(0) * 1) /* 16 bits wide */
+#define PLX_DMAMODE_WIDTH32 (BIT(0) * 2) /* 32 bits wide */
+#define PLX_DMAMODE_WIDTH32A (BIT(0) * 3) /* 32 bits wide */
+#define PLX_DMAMODE_WIDTH_MASK GENMASK(1, 0)
+#define PLX_DMAMODE_WIDTH_SHIFT 0
+/* Internal Wait States */
+#define PLX_DMAMODE_IWS(x) (BIT(2) * ((x) & 0xf))
+#define PLX_DMAMODE_IWS_MASK GENMASK(5, 2)
+#define PLX_DMAMODE_SHIFT 2
+/* Ready Input Enable */
+#define PLX_DMAMODE_READYIEN BIT(6)
+/* BTERM# Input Enable */
+#define PLX_DMAMODE_BTERMIEN BIT(7)
+/* Local Burst Enable */
+#define PLX_DMAMODE_BURSTEN BIT(8)
+/* Chaining Enable */
+#define PLX_DMAMODE_CHAINEN BIT(9)
+/* Done Interrupt Enable */
+#define PLX_DMAMODE_DONEIEN BIT(10)
+/* Hold Local Address Constant */
+#define PLX_DMAMODE_LACONST BIT(11)
+/* Demand Mode */
+#define PLX_DMAMODE_DEMAND BIT(12)
+/* Write And Invalidate Mode */
+#define PLX_DMAMODE_WINVALIDATE BIT(13)
+/* DMA EOT Enable - enables EOT0# or EOT1# input pin */
+#define PLX_DMAMODE_EOTEN BIT(14)
+/* DMA Stop Data Transfer Mode - 0:BLAST; 1:EOT asserted or DREQ deasserted */
+#define PLX_DMAMODE_STOP BIT(15)
+/* DMA Clear Count Mode - count in descriptor cleared on completion */
+#define PLX_DMAMODE_CLRCOUNT BIT(16)
+/* DMA Channel Interrupt Select - 0:local bus interrupt; 1:PCI interrupt */
+#define PLX_DMAMODE_INTRPCI BIT(17)
/* DMA Channel N PCI Address Register (N <= 1) */
#define PLX_REG_DMAPADR(n) ((n) ? PLX_REG_DMAPADR1 : PLX_REG_DMAPADR0)
--
2.8.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 15/20] staging: comedi: drivers: re-do PLX PCI 9080 DMADPRx register values
2016-05-20 13:49 [PATCH 00/20] staging: comedi: re-do drivers/plx9080.h Ian Abbott
` (13 preceding siblings ...)
2016-05-20 13:49 ` [PATCH 14/20] staging: comedi: drivers: re-do PLX PCI 9080 DMAMODEx register values Ian Abbott
@ 2016-05-20 13:49 ` Ian Abbott
2016-05-20 13:49 ` [PATCH 16/20] staging: comedi: drivers: re-do PLX PCI 9080 DMACSRx " Ian Abbott
` (4 subsequent siblings)
19 siblings, 0 replies; 28+ messages in thread
From: Ian Abbott @ 2016-05-20 13:49 UTC (permalink / raw)
To: devel; +Cc: Greg Kroah-Hartman, Ian Abbott, H Hartley Sweeten, linux-kernel
Replace the existing macros in "plx9080.h" that define values for the
DMADPR0 and DMADPR1 registers. (A little-endian version of the register
value is also placed in the `next` member of `struct plx_dma_desc`.)
Use the prefix `PLX_DMADPR_` for the macros. Make use of the `BIT(x)`
and `GENMASK(h,l)` macros to define the values.
Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
---
drivers/staging/comedi/drivers/cb_pcidas64.c | 22 +++++++++++-----------
drivers/staging/comedi/drivers/gsc_hpdi.c | 8 ++++----
drivers/staging/comedi/drivers/plx9080.h | 17 ++++++++++-------
3 files changed, 25 insertions(+), 22 deletions(-)
diff --git a/drivers/staging/comedi/drivers/cb_pcidas64.c b/drivers/staging/comedi/drivers/cb_pcidas64.c
index 48aca06..a4d10a3 100644
--- a/drivers/staging/comedi/drivers/cb_pcidas64.c
+++ b/drivers/staging/comedi/drivers/cb_pcidas64.c
@@ -1534,8 +1534,8 @@ static int alloc_and_init_dma_members(struct comedi_device *dev)
cpu_to_le32((devpriv->ai_dma_desc_bus_addr +
((i + 1) % ai_dma_ring_count(board)) *
sizeof(devpriv->ai_dma_desc[0])) |
- PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT |
- PLX_XFER_LOCAL_TO_PCI);
+ PLX_DMADPR_DESCPCI | PLX_DMADPR_TCINTR |
+ PLX_DMADPR_XFERL2P);
}
if (ao_cmd_is_supported(board)) {
for (i = 0; i < AO_DMA_RING_COUNT; i++) {
@@ -1549,8 +1549,8 @@ static int alloc_and_init_dma_members(struct comedi_device *dev)
cpu_to_le32((devpriv->ao_dma_desc_bus_addr +
((i + 1) % (AO_DMA_RING_COUNT)) *
sizeof(devpriv->ao_dma_desc[0])) |
- PLX_DESC_IN_PCI_BIT |
- PLX_INTR_TERM_COUNT);
+ PLX_DMADPR_DESCPCI |
+ PLX_DMADPR_TCINTR);
}
}
return 0;
@@ -2634,9 +2634,9 @@ static int ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
/* give location of first dma descriptor */
load_first_dma_descriptor(dev, 1,
devpriv->ai_dma_desc_bus_addr |
- PLX_DESC_IN_PCI_BIT |
- PLX_INTR_TERM_COUNT |
- PLX_XFER_LOCAL_TO_PCI);
+ PLX_DMADPR_DESCPCI |
+ PLX_DMADPR_TCINTR |
+ PLX_DMADPR_XFERL2P);
dma_start_sync(dev, 1);
}
@@ -2918,7 +2918,7 @@ static void restart_ao_dma(struct comedi_device *dev)
unsigned int dma_desc_bits;
dma_desc_bits = readl(devpriv->plx9080_iobase + PLX_REG_DMADPR0);
- dma_desc_bits &= ~PLX_END_OF_CHAIN_BIT;
+ dma_desc_bits &= ~PLX_DMADPR_CHAINEND;
load_first_dma_descriptor(dev, 0, dma_desc_bits);
dma_start_sync(dev, 0);
@@ -2959,14 +2959,14 @@ static unsigned int load_ao_dma_buffer(struct comedi_device *dev,
devpriv->ao_dma_desc[buffer_index].transfer_size = cpu_to_le32(nbytes);
/* set end of chain bit so we catch underruns */
next_bits = le32_to_cpu(devpriv->ao_dma_desc[buffer_index].next);
- next_bits |= PLX_END_OF_CHAIN_BIT;
+ next_bits |= PLX_DMADPR_CHAINEND;
devpriv->ao_dma_desc[buffer_index].next = cpu_to_le32(next_bits);
/*
* clear end of chain bit on previous buffer now that we have set it
* for the last buffer
*/
next_bits = le32_to_cpu(devpriv->ao_dma_desc[prev_buffer_index].next);
- next_bits &= ~PLX_END_OF_CHAIN_BIT;
+ next_bits &= ~PLX_DMADPR_CHAINEND;
devpriv->ao_dma_desc[prev_buffer_index].next = cpu_to_le32(next_bits);
devpriv->ao_dma_index = (buffer_index + 1) % AO_DMA_RING_COUNT;
@@ -3310,7 +3310,7 @@ static int ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
set_dac_select_reg(dev, cmd);
set_dac_interval_regs(dev, cmd);
load_first_dma_descriptor(dev, 0, devpriv->ao_dma_desc_bus_addr |
- PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT);
+ PLX_DMADPR_DESCPCI | PLX_DMADPR_TCINTR);
set_dac_control1_reg(dev, cmd);
s->async->inttrig = ao_inttrig;
diff --git a/drivers/staging/comedi/drivers/gsc_hpdi.c b/drivers/staging/comedi/drivers/gsc_hpdi.c
index d63dc46..f2f1874 100644
--- a/drivers/staging/comedi/drivers/gsc_hpdi.c
+++ b/drivers/staging/comedi/drivers/gsc_hpdi.c
@@ -310,8 +310,8 @@ static int gsc_hpdi_cmd(struct comedi_device *dev,
writel(0, devpriv->plx9080_mmio + PLX_REG_DMALADR0);
/* give location of first dma descriptor */
- bits = devpriv->dma_desc_phys_addr | PLX_DESC_IN_PCI_BIT |
- PLX_INTR_TERM_COUNT | PLX_XFER_LOCAL_TO_PCI;
+ bits = devpriv->dma_desc_phys_addr | PLX_DMADPR_DESCPCI |
+ PLX_DMADPR_TCINTR | PLX_DMADPR_XFERL2P;
writel(bits, devpriv->plx9080_mmio + PLX_REG_DMADPR0);
/* enable dma transfer */
@@ -422,8 +422,8 @@ static int gsc_hpdi_setup_dma_descriptors(struct comedi_device *dev,
{
struct hpdi_private *devpriv = dev->private;
dma_addr_t phys_addr = devpriv->dma_desc_phys_addr;
- u32 next_bits = PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT |
- PLX_XFER_LOCAL_TO_PCI;
+ u32 next_bits = PLX_DMADPR_DESCPCI | PLX_DMADPR_TCINTR |
+ PLX_DMADPR_XFERL2P;
unsigned int offset = 0;
unsigned int idx = 0;
unsigned int i;
diff --git a/drivers/staging/comedi/drivers/plx9080.h b/drivers/staging/comedi/drivers/plx9080.h
index 99c075c..2fe1a4d 100644
--- a/drivers/staging/comedi/drivers/plx9080.h
+++ b/drivers/staging/comedi/drivers/plx9080.h
@@ -513,13 +513,16 @@ struct plx_dma_desc {
#define PLX_REG_DMADPR0 0x0090
#define PLX_REG_DMADPR1 0x00a4
-/* descriptor is located in pci space (not local space) */
-#define PLX_DESC_IN_PCI_BIT 0x1
-#define PLX_END_OF_CHAIN_BIT 0x2 /* end of chain bit */
-/* interrupt when this descriptor's transfer is finished */
-#define PLX_INTR_TERM_COUNT 0x4
-/* transfer from local to pci bus (not pci to local) */
-#define PLX_XFER_LOCAL_TO_PCI 0x8
+/* Descriptor Located In PCI Address Space (not local address space) */
+#define PLX_DMADPR_DESCPCI BIT(0)
+/* End Of Chain */
+#define PLX_DMADPR_CHAINEND BIT(1)
+/* Interrupt After Terminal Count */
+#define PLX_DMADPR_TCINTR BIT(2)
+/* Direction Of Transfer Local Bus To PCI (not PCI to local) */
+#define PLX_DMADPR_XFERL2P BIT(3)
+/* Next Descriptor Address Bits 31:4 (16 byte boundary) */
+#define PLX_DMADPR_NEXT_MASK GENMASK(31, 4)
/* DMA Channel N Command/Status Register (N <= 1) (8-bit) */
#define PLX_REG_DMACSR(n) ((n) ? PLX_REG_DMACSR1 : PLX_REG_DMACSR0)
--
2.8.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 16/20] staging: comedi: drivers: re-do PLX PCI 9080 DMACSRx register values
2016-05-20 13:49 [PATCH 00/20] staging: comedi: re-do drivers/plx9080.h Ian Abbott
` (14 preceding siblings ...)
2016-05-20 13:49 ` [PATCH 15/20] staging: comedi: drivers: re-do PLX PCI 9080 DMADPRx " Ian Abbott
@ 2016-05-20 13:49 ` Ian Abbott
2016-05-20 13:49 ` [PATCH 17/20] staging: comedi: drivers: add PLX PCI 9080 DMATHR " Ian Abbott
` (3 subsequent siblings)
19 siblings, 0 replies; 28+ messages in thread
From: Ian Abbott @ 2016-05-20 13:49 UTC (permalink / raw)
To: devel; +Cc: Greg Kroah-Hartman, Ian Abbott, H Hartley Sweeten, linux-kernel
Replace the existing macros in "plx9080.h" that define values for the
DMACSR0 and DMACSR0 registers. Use the prefix `PLX_DMACSR_` for the
macros. Make use of the `BIT(x)` macro to define the values.
Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
---
drivers/staging/comedi/drivers/cb_pcidas64.c | 22 +++++++++++-----------
drivers/staging/comedi/drivers/gsc_hpdi.c | 8 ++++----
drivers/staging/comedi/drivers/plx9080.h | 23 ++++++++++++++---------
3 files changed, 29 insertions(+), 24 deletions(-)
diff --git a/drivers/staging/comedi/drivers/cb_pcidas64.c b/drivers/staging/comedi/drivers/cb_pcidas64.c
index a4d10a3..1f9c08a 100644
--- a/drivers/staging/comedi/drivers/cb_pcidas64.c
+++ b/drivers/staging/comedi/drivers/cb_pcidas64.c
@@ -2368,7 +2368,7 @@ static inline void dma_start_sync(struct comedi_device *dev,
/* spinlock for plx dma control/status reg */
spin_lock_irqsave(&dev->spinlock, flags);
- writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT | PLX_CLEAR_DMA_INTR_BIT,
+ writeb(PLX_DMACSR_ENABLE | PLX_DMACSR_START | PLX_DMACSR_CLEARINTR,
devpriv->plx9080_iobase + PLX_REG_DMACSR(channel));
spin_unlock_irqrestore(&dev->spinlock, flags);
}
@@ -2838,10 +2838,10 @@ static void handle_ai_interrupt(struct comedi_device *dev,
spin_lock_irqsave(&dev->spinlock, flags);
dma1_status = readb(devpriv->plx9080_iobase + PLX_REG_DMACSR1);
if (plx_status & PLX_INTCSR_DMA1IA) { /* dma chan 1 interrupt */
- writeb((dma1_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
+ writeb((dma1_status & PLX_DMACSR_ENABLE) | PLX_DMACSR_CLEARINTR,
devpriv->plx9080_iobase + PLX_REG_DMACSR1);
- if (dma1_status & PLX_DMA_EN_BIT)
+ if (dma1_status & PLX_DMACSR_ENABLE)
drain_dma_buffers(dev, 1);
}
spin_unlock_irqrestore(&dev->spinlock, flags);
@@ -2889,7 +2889,7 @@ static int last_ao_dma_load_completed(struct comedi_device *dev)
buffer_index = prev_ao_dma_index(dev);
dma_status = readb(devpriv->plx9080_iobase + PLX_REG_DMACSR0);
- if ((dma_status & PLX_DMA_DONE_BIT) == 0)
+ if ((dma_status & PLX_DMACSR_DONE) == 0)
return 0;
transfer_address =
@@ -2903,8 +2903,8 @@ static int last_ao_dma_load_completed(struct comedi_device *dev)
static inline int ao_dma_needs_restart(struct comedi_device *dev,
unsigned short dma_status)
{
- if ((dma_status & PLX_DMA_DONE_BIT) == 0 ||
- (dma_status & PLX_DMA_EN_BIT) == 0)
+ if ((dma_status & PLX_DMACSR_DONE) == 0 ||
+ (dma_status & PLX_DMACSR_ENABLE) == 0)
return 0;
if (last_ao_dma_load_completed(dev))
return 0;
@@ -3016,16 +3016,16 @@ static void handle_ao_interrupt(struct comedi_device *dev,
spin_lock_irqsave(&dev->spinlock, flags);
dma0_status = readb(devpriv->plx9080_iobase + PLX_REG_DMACSR0);
if (plx_status & PLX_INTCSR_DMA0IA) { /* dma chan 0 interrupt */
- if ((dma0_status & PLX_DMA_EN_BIT) &&
- !(dma0_status & PLX_DMA_DONE_BIT)) {
- writeb(PLX_DMA_EN_BIT | PLX_CLEAR_DMA_INTR_BIT,
+ if ((dma0_status & PLX_DMACSR_ENABLE) &&
+ !(dma0_status & PLX_DMACSR_DONE)) {
+ writeb(PLX_DMACSR_ENABLE | PLX_DMACSR_CLEARINTR,
devpriv->plx9080_iobase + PLX_REG_DMACSR0);
} else {
- writeb(PLX_CLEAR_DMA_INTR_BIT,
+ writeb(PLX_DMACSR_CLEARINTR,
devpriv->plx9080_iobase + PLX_REG_DMACSR0);
}
spin_unlock_irqrestore(&dev->spinlock, flags);
- if (dma0_status & PLX_DMA_EN_BIT) {
+ if (dma0_status & PLX_DMACSR_ENABLE) {
load_ao_dma(dev, cmd);
/* try to recover from dma end-of-chain event */
if (ao_dma_needs_restart(dev, dma0_status))
diff --git a/drivers/staging/comedi/drivers/gsc_hpdi.c b/drivers/staging/comedi/drivers/gsc_hpdi.c
index f2f1874..af4b417 100644
--- a/drivers/staging/comedi/drivers/gsc_hpdi.c
+++ b/drivers/staging/comedi/drivers/gsc_hpdi.c
@@ -214,10 +214,10 @@ static irqreturn_t gsc_hpdi_interrupt(int irq, void *d)
dma0_status = readb(devpriv->plx9080_mmio + PLX_REG_DMACSR0);
if (plx_status & PLX_INTCSR_DMA0IA) {
/* dma chan 0 interrupt */
- writeb((dma0_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
+ writeb((dma0_status & PLX_DMACSR_ENABLE) | PLX_DMACSR_CLEARINTR,
devpriv->plx9080_mmio + PLX_REG_DMACSR0);
- if (dma0_status & PLX_DMA_EN_BIT)
+ if (dma0_status & PLX_DMACSR_ENABLE)
gsc_hpdi_drain_dma(dev, 0);
}
spin_unlock_irqrestore(&dev->spinlock, flags);
@@ -227,7 +227,7 @@ static irqreturn_t gsc_hpdi_interrupt(int irq, void *d)
dma1_status = readb(devpriv->plx9080_mmio + PLX_REG_DMACSR1);
if (plx_status & PLX_INTCSR_DMA1IA) {
/* XXX */ /* dma chan 1 interrupt */
- writeb((dma1_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
+ writeb((dma1_status & PLX_DMACSR_ENABLE) | PLX_DMACSR_CLEARINTR,
devpriv->plx9080_mmio + PLX_REG_DMACSR1);
}
spin_unlock_irqrestore(&dev->spinlock, flags);
@@ -316,7 +316,7 @@ static int gsc_hpdi_cmd(struct comedi_device *dev,
/* enable dma transfer */
spin_lock_irqsave(&dev->spinlock, flags);
- writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT | PLX_CLEAR_DMA_INTR_BIT,
+ writeb(PLX_DMACSR_ENABLE | PLX_DMACSR_START | PLX_DMACSR_CLEARINTR,
devpriv->plx9080_mmio + PLX_REG_DMACSR0);
spin_unlock_irqrestore(&dev->spinlock, flags);
diff --git a/drivers/staging/comedi/drivers/plx9080.h b/drivers/staging/comedi/drivers/plx9080.h
index 2fe1a4d..9e76342 100644
--- a/drivers/staging/comedi/drivers/plx9080.h
+++ b/drivers/staging/comedi/drivers/plx9080.h
@@ -529,11 +529,16 @@ struct plx_dma_desc {
#define PLX_REG_DMACSR0 0x00a8
#define PLX_REG_DMACSR1 0x00a9
-#define PLX_DMA_EN_BIT 0x1 /* enable dma channel */
-#define PLX_DMA_START_BIT 0x2 /* start dma transfer */
-#define PLX_DMA_ABORT_BIT 0x4 /* abort dma transfer */
-#define PLX_CLEAR_DMA_INTR_BIT 0x8 /* clear dma interrupt */
-#define PLX_DMA_DONE_BIT 0x10 /* transfer done status bit */
+/* Channel Enable */
+#define PLX_DMACSR_ENABLE BIT(0)
+/* Channel Start - write 1 to start transfer (write-only) */
+#define PLX_DMACSR_START BIT(1)
+/* Channel Abort - write 1 to abort transfer (write-only) */
+#define PLX_DMACSR_ABORT BIT(2)
+/* Clear Interrupt - write 1 to clear DMA Channel Interrupt (write-only) */
+#define PLX_DMACSR_CLEARINTR BIT(3)
+/* Channel Done - transfer complete/inactive (read-only) */
+#define PLX_DMACSR_DONE BIT(4)
/* DMA Threshold Register */
#define PLX_REG_DMATHR 0x00b0
@@ -571,11 +576,11 @@ static inline int plx9080_abort_dma(void __iomem *iobase, unsigned int channel)
/* abort dma transfer if necessary */
dma_status = readb(dma_cs_addr);
- if ((dma_status & PLX_DMA_EN_BIT) == 0)
+ if ((dma_status & PLX_DMACSR_ENABLE) == 0)
return 0;
/* wait to make sure done bit is zero */
- for (i = 0; (dma_status & PLX_DMA_DONE_BIT) && i < timeout; i++) {
+ for (i = 0; (dma_status & PLX_DMACSR_DONE) && i < timeout; i++) {
udelay(1);
dma_status = readb(dma_cs_addr);
}
@@ -583,10 +588,10 @@ static inline int plx9080_abort_dma(void __iomem *iobase, unsigned int channel)
return -ETIMEDOUT;
/* disable and abort channel */
- writeb(PLX_DMA_ABORT_BIT, dma_cs_addr);
+ writeb(PLX_DMACSR_ABORT, dma_cs_addr);
/* wait for dma done bit */
dma_status = readb(dma_cs_addr);
- for (i = 0; (dma_status & PLX_DMA_DONE_BIT) == 0 && i < timeout; i++) {
+ for (i = 0; (dma_status & PLX_DMACSR_DONE) == 0 && i < timeout; i++) {
udelay(1);
dma_status = readb(dma_cs_addr);
}
--
2.8.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 17/20] staging: comedi: drivers: add PLX PCI 9080 DMATHR register values
2016-05-20 13:49 [PATCH 00/20] staging: comedi: re-do drivers/plx9080.h Ian Abbott
` (15 preceding siblings ...)
2016-05-20 13:49 ` [PATCH 16/20] staging: comedi: drivers: re-do PLX PCI 9080 DMACSRx " Ian Abbott
@ 2016-05-20 13:49 ` Ian Abbott
2016-05-20 13:49 ` [PATCH 18/20] staging: comedi: plx9080.h: tidy up some comments Ian Abbott
` (2 subsequent siblings)
19 siblings, 0 replies; 28+ messages in thread
From: Ian Abbott @ 2016-05-20 13:49 UTC (permalink / raw)
To: devel; +Cc: Greg Kroah-Hartman, Ian Abbott, H Hartley Sweeten, linux-kernel
Add macros in "plx9080.h" that define values for the DMATHR register
values. Use the prefix `PLX_DMATHR_` for the macros. Make use of the
`BIT(x)` and `GENMASK(h,l)` macros to define the values.
Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
---
drivers/staging/comedi/drivers/plx9080.h | 41 ++++++++++++++++++++++++++++++++
1 file changed, 41 insertions(+)
diff --git a/drivers/staging/comedi/drivers/plx9080.h b/drivers/staging/comedi/drivers/plx9080.h
index 9e76342..50d0b1b 100644
--- a/drivers/staging/comedi/drivers/plx9080.h
+++ b/drivers/staging/comedi/drivers/plx9080.h
@@ -544,6 +544,47 @@ struct plx_dma_desc {
#define PLX_REG_DMATHR 0x00b0
/*
+ * DMA Threshold constraints:
+ * (C0PLAF + 1) + (C0PLAE + 1) <= 32
+ * (C0LPAF + 1) + (C0LPAE + 1) <= 32
+ * (C1PLAF + 1) + (C1PLAE + 1) <= 16
+ * (C1LPAF + 1) + (C1LPAE + 1) <= 16
+ */
+
+/* DMA Channel 0 PCI-to-Local Almost Full (divided by 2, minus 1) */
+#define PLX_DMATHR_C0PLAF(x) (BIT(0) * ((x) & 0xf))
+#define PLX_DMATHR_C0PLAF_MASK GENMASK(3, 0)
+#define PLX_DMATHR_C0PLAF_SHIFT 0
+/* DMA Channel 0 Local-to-PCI Almost Empty (divided by 2, minus 1) */
+#define PLX_DMATHR_C0LPAE(x) (BIT(4) * ((x) & 0xf))
+#define PLX_DMATHR_C0LPAE_MASK GENMASK(7, 4)
+#define PLX_DMATHR_C0LPAE_SHIFT 4
+/* DMA Channel 0 Local-to-PCI Almost Full (divided by 2, minus 1) */
+#define PLX_DMATHR_C0LPAF(x) (BIT(8) * ((x) & 0xf))
+#define PLX_DMATHR_C0LPAF_MASK GENMASK(11, 8)
+#define PLX_DMATHR_C0LPAF_SHIFT 8
+/* DMA Channel 0 PCI-to-Local Almost Empty (divided by 2, minus 1) */
+#define PLX_DMATHR_C0PLAE(x) (BIT(12) * ((x) & 0xf))
+#define PLX_DMATHR_C0PLAE_MASK GENMASK(15, 12)
+#define PLX_DMATHR_C0PLAE_SHIFT 12
+/* DMA Channel 1 PCI-to-Local Almost Full (divided by 2, minus 1) */
+#define PLX_DMATHR_C1PLAF(x) (BIT(16) * ((x) & 0xf))
+#define PLX_DMATHR_C1PLAF_MASK GENMASK(19, 16)
+#define PLX_DMATHR_C1PLAF_SHIFT 16
+/* DMA Channel 1 Local-to-PCI Almost Empty (divided by 2, minus 1) */
+#define PLX_DMATHR_C1LPAE(x) (BIT(20) * ((x) & 0xf))
+#define PLX_DMATHR_C1LPAE_MASK GENMASK(23, 20)
+#define PLX_DMATHR_C1LPAE_SHIFT 20
+/* DMA Channel 1 Local-to-PCI Almost Full (divided by 2, minus 1) */
+#define PLX_DMATHR_C1LPAF(x) (BIT(24) * ((x) & 0xf))
+#define PLX_DMATHR_C1LPAF_MASK GENMASK(27, 24)
+#define PLX_DMATHR_C1LPAF_SHIFT 24
+/* DMA Channel 1 PCI-to-Local Almost Empty (divided by 2, minus 1) */
+#define PLX_DMATHR_C1PLAE(x) (BIT(28) * ((x) & 0xf))
+#define PLX_DMATHR_C1PLAE_MASK GENMASK(31, 28)
+#define PLX_DMATHR_C1PLAE_SHIFT 28
+
+/*
* Messaging Queue Registers OPLFIS, OPLFIM, IQP, OQP, MQCR, QBAR, IFHPR,
* IFTPR, IPHPR, IPTPR, OFHPR, OFTPR, OPHPR, OPTPR, and QSR have been omitted.
* They are used by the I2O feature. (IQP and OQP occupy the usual offsets of
--
2.8.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 18/20] staging: comedi: plx9080.h: tidy up some comments
2016-05-20 13:49 [PATCH 00/20] staging: comedi: re-do drivers/plx9080.h Ian Abbott
` (16 preceding siblings ...)
2016-05-20 13:49 ` [PATCH 17/20] staging: comedi: drivers: add PLX PCI 9080 DMATHR " Ian Abbott
@ 2016-05-20 13:49 ` Ian Abbott
2016-05-20 13:49 ` [PATCH 19/20] staging: comedi: plx9080.h: Add kerneldoc comments Ian Abbott
2016-05-20 13:49 ` [PATCH 20/20] staging: comedi: plx9080.h: include headers for declarations Ian Abbott
19 siblings, 0 replies; 28+ messages in thread
From: Ian Abbott @ 2016-05-20 13:49 UTC (permalink / raw)
To: devel; +Cc: Greg Kroah-Hartman, Ian Abbott, H Hartley Sweeten, linux-kernel
Use the usual block comment style and remove some excess spaces from
single-line comments. Remove some obvious stuff about register offsets
being zero relative. Remove some text about the original history of the
file, as it bears hardly any resemblance to it now.
Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
---
drivers/staging/comedi/drivers/plx9080.h | 36 +++++++++++---------------------
1 file changed, 12 insertions(+), 24 deletions(-)
diff --git a/drivers/staging/comedi/drivers/plx9080.h b/drivers/staging/comedi/drivers/plx9080.h
index 50d0b1b..d701b15 100644
--- a/drivers/staging/comedi/drivers/plx9080.h
+++ b/drivers/staging/comedi/drivers/plx9080.h
@@ -3,15 +3,6 @@
*
* Copyright (C) 2002,2003 Frank Mori Hess <fmhess@users.sourceforge.net>
*
- * I modified this file from the plx9060.h header for the
- * wanXL device driver in the linux kernel,
- * for the register offsets and bit definitions. Made minor modifications,
- * added plx9080 registers and
- * stripped out stuff that was specifically for the wanXL driver.
- * Note: I've only made sure the definitions are correct as far
- * as I make use of them. There are still various plx9060-isms
- * left in this header file.
- *
********************************************************************
*
* Copyright (C) 1999 RG Studio s.c.
@@ -28,7 +19,7 @@
#ifndef __COMEDI_PLX9080_H
#define __COMEDI_PLX9080_H
-/* descriptor block used for chained dma transfers */
+/* descriptor block used for chained dma transfers */
struct plx_dma_desc {
__le32 pci_start_addr;
__le32 local_start_addr;
@@ -41,13 +32,9 @@ struct plx_dma_desc {
__le32 next;
};
-/**********************************************************************
-** Register Offsets and Bit Definitions
-**
-** Note: All offsets zero relative. IE. Some standard base address
-** must be added to the Register Number to properly access the register.
-**
-**********************************************************************/
+/*
+ * Register Offsets and Bit Definitions
+ */
/* Local Address Space 0 Range Register */
#define PLX_REG_LAS0RR 0x0000
@@ -145,10 +132,11 @@ struct plx_dma_desc {
#define PLX_BIGEND_DMA(n) ((n) ? PLX_BIGEND_DMA1 : PLX_BIGEND_DMA0)
/*
-** Note: The Expansion ROM stuff is only relevant to the PC environment.
-** This expansion ROM code is executed by the host CPU at boot time.
-** For this reason no bit definitions are provided here.
+ * Note: The Expansion ROM stuff is only relevant to the PC environment.
+ * This expansion ROM code is executed by the host CPU at boot time.
+ * For this reason no bit definitions are provided here.
*/
+
/* Expansion ROM Range Register */
#define PLX_REG_EROMRR 0x0010
/* Expansion ROM Local Base Address (Remap) Register */
@@ -615,12 +603,12 @@ static inline int plx9080_abort_dma(void __iomem *iobase, unsigned int channel)
dma_cs_addr = iobase + PLX_REG_DMACSR(channel);
- /* abort dma transfer if necessary */
+ /* abort dma transfer if necessary */
dma_status = readb(dma_cs_addr);
if ((dma_status & PLX_DMACSR_ENABLE) == 0)
return 0;
- /* wait to make sure done bit is zero */
+ /* wait to make sure done bit is zero */
for (i = 0; (dma_status & PLX_DMACSR_DONE) && i < timeout; i++) {
udelay(1);
dma_status = readb(dma_cs_addr);
@@ -628,9 +616,9 @@ static inline int plx9080_abort_dma(void __iomem *iobase, unsigned int channel)
if (i == timeout)
return -ETIMEDOUT;
- /* disable and abort channel */
+ /* disable and abort channel */
writeb(PLX_DMACSR_ABORT, dma_cs_addr);
- /* wait for dma done bit */
+ /* wait for dma done bit */
dma_status = readb(dma_cs_addr);
for (i = 0; (dma_status & PLX_DMACSR_DONE) == 0 && i < timeout; i++) {
udelay(1);
--
2.8.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 19/20] staging: comedi: plx9080.h: Add kerneldoc comments
2016-05-20 13:49 [PATCH 00/20] staging: comedi: re-do drivers/plx9080.h Ian Abbott
` (17 preceding siblings ...)
2016-05-20 13:49 ` [PATCH 18/20] staging: comedi: plx9080.h: tidy up some comments Ian Abbott
@ 2016-05-20 13:49 ` Ian Abbott
2016-05-20 13:49 ` [PATCH 20/20] staging: comedi: plx9080.h: include headers for declarations Ian Abbott
19 siblings, 0 replies; 28+ messages in thread
From: Ian Abbott @ 2016-05-20 13:49 UTC (permalink / raw)
To: devel; +Cc: Greg Kroah-Hartman, Ian Abbott, H Hartley Sweeten, linux-kernel
Document the DMA descriptor `struct plx_dma_desc`, and the DMA abort
function `plx9080_abort_dma()`.
Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
---
drivers/staging/comedi/drivers/plx9080.h | 35 ++++++++++++++++++++++++++------
1 file changed, 29 insertions(+), 6 deletions(-)
diff --git a/drivers/staging/comedi/drivers/plx9080.h b/drivers/staging/comedi/drivers/plx9080.h
index d701b15..f67f9d7 100644
--- a/drivers/staging/comedi/drivers/plx9080.h
+++ b/drivers/staging/comedi/drivers/plx9080.h
@@ -19,16 +19,27 @@
#ifndef __COMEDI_PLX9080_H
#define __COMEDI_PLX9080_H
-/* descriptor block used for chained dma transfers */
+/**
+ * struct plx_dma_desc - DMA descriptor format for PLX PCI 9080
+ * @pci_start_addr: PCI Bus address for transfer (DMAPADR).
+ * @local_start_addr: Local Bus address for transfer (DMALADR).
+ * @transfer_size: Transfer size in bytes (max 8 MiB) (DMASIZ).
+ * @next: Address of next descriptor + flags (DMADPR).
+ *
+ * Describes the format of a scatter-gather DMA descriptor for the PLX
+ * PCI 9080. All members are raw, little-endian register values that
+ * will be transferred by the DMA engine from local or PCI memory into
+ * corresponding registers for the DMA channel.
+ *
+ * The DMA descriptors must be aligned on a 16-byte boundary. Bits 3:0
+ * of @next contain flags describing the address space of the next
+ * descriptor (local or PCI), an "end of chain" marker, an "interrupt on
+ * terminal count" bit, and a data transfer direction.
+ */
struct plx_dma_desc {
__le32 pci_start_addr;
__le32 local_start_addr;
- /* transfer_size is in bytes, only first 23 bits of register are used */
__le32 transfer_size;
- /*
- * address of next descriptor (quad word aligned), plus some
- * additional bits (see PLX_REG_DMADPR)
- */
__le32 next;
};
@@ -594,6 +605,18 @@ struct plx_dma_desc {
#define PLX_PREFETCH 32
+/**
+ * plx9080_abort_dma - Abort a PLX PCI 9080 DMA transfer
+ * @iobase: Remapped base address of configuration registers.
+ * @channel: DMA channel number (0 or 1).
+ *
+ * Aborts the DMA transfer on the channel, which must have been enabled
+ * and started beforehand.
+ *
+ * Return:
+ * %0 on success.
+ * -%ETIMEDOUT if timed out waiting for abort to complete.
+ */
static inline int plx9080_abort_dma(void __iomem *iobase, unsigned int channel)
{
void __iomem *dma_cs_addr;
--
2.8.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 20/20] staging: comedi: plx9080.h: include headers for declarations
2016-05-20 13:49 [PATCH 00/20] staging: comedi: re-do drivers/plx9080.h Ian Abbott
` (18 preceding siblings ...)
2016-05-20 13:49 ` [PATCH 19/20] staging: comedi: plx9080.h: Add kerneldoc comments Ian Abbott
@ 2016-05-20 13:49 ` Ian Abbott
19 siblings, 0 replies; 28+ messages in thread
From: Ian Abbott @ 2016-05-20 13:49 UTC (permalink / raw)
To: devel; +Cc: Greg Kroah-Hartman, Ian Abbott, H Hartley Sweeten, linux-kernel
Add `#include` lines to declare stuff used by "plx9080.h" itself.
Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
---
drivers/staging/comedi/drivers/plx9080.h | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/staging/comedi/drivers/plx9080.h b/drivers/staging/comedi/drivers/plx9080.h
index f67f9d7..0e20cc5 100644
--- a/drivers/staging/comedi/drivers/plx9080.h
+++ b/drivers/staging/comedi/drivers/plx9080.h
@@ -19,6 +19,13 @@
#ifndef __COMEDI_PLX9080_H
#define __COMEDI_PLX9080_H
+#include <linux/compiler.h>
+#include <linux/types.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+
/**
* struct plx_dma_desc - DMA descriptor format for PLX PCI 9080
* @pci_start_addr: PCI Bus address for transfer (DMAPADR).
--
2.8.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* RE: [PATCH 03/20] staging: comedi: drivers: rename PLX PCI 9080 register offsets
2016-05-20 13:49 ` [PATCH 03/20] staging: comedi: drivers: rename PLX PCI 9080 register offsets Ian Abbott
@ 2016-05-20 16:21 ` Hartley Sweeten
2016-05-20 16:30 ` Ian Abbott
0 siblings, 1 reply; 28+ messages in thread
From: Hartley Sweeten @ 2016-05-20 16:21 UTC (permalink / raw)
To: Ian Abbott, devel; +Cc: Greg Kroah-Hartman, linux-kernel
On Friday, May 20, 2016 6:49 AM, Ian Abbott wrote:
> Rename the macros in "plx9080.h" that define the offsets of registers,
> following the pattern `PLX_REG_<NAME>`, where `<NAME>` is the register
> name from the PLX PCI 9080 Data Book.
>
> Add defines for the "Mailbox" registers, and add parameterized macros
> for the mailbox registers and the DMA control registers. Make use of
> the parameterized versions of the macros where it seems appropriate.
>
> The registers for supporting the I2O (Intelligent Input/Output) feature
> are largely left undefined, just defining enough to allow the I2O
> feature to be disabled.
>
> Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
Ian,
Just an comment on your renaming.
You also renamed the registers in the daqbook2000 driver in the
<driver>_REG_<name> format. Personally I prefer the format to be
<driver>_<name>_REG. That way a grep for <driver>_<name> will
return both the register and bit uses.
Currently the <driver>_REG_<name> form is not as common in comedi.
Looks like it's only used in amcc_35933.h and will be in daqboard2000.c.
The <driver>_<name>_REG form is used a lot.
Not a big deal, just a comment.
Hartley
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 03/20] staging: comedi: drivers: rename PLX PCI 9080 register offsets
2016-05-20 16:21 ` Hartley Sweeten
@ 2016-05-20 16:30 ` Ian Abbott
2016-05-20 16:51 ` Hartley Sweeten
0 siblings, 1 reply; 28+ messages in thread
From: Ian Abbott @ 2016-05-20 16:30 UTC (permalink / raw)
To: Hartley Sweeten, devel; +Cc: Greg Kroah-Hartman, linux-kernel
On 20/05/16 17:21, Hartley Sweeten wrote:
> On Friday, May 20, 2016 6:49 AM, Ian Abbott wrote:
>> Rename the macros in "plx9080.h" that define the offsets of registers,
>> following the pattern `PLX_REG_<NAME>`, where `<NAME>` is the register
>> name from the PLX PCI 9080 Data Book.
>>
>> Add defines for the "Mailbox" registers, and add parameterized macros
>> for the mailbox registers and the DMA control registers. Make use of
>> the parameterized versions of the macros where it seems appropriate.
>>
>> The registers for supporting the I2O (Intelligent Input/Output) feature
>> are largely left undefined, just defining enough to allow the I2O
>> feature to be disabled.
>>
>> Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
>
> Ian,
>
> Just an comment on your renaming.
>
> You also renamed the registers in the daqbook2000 driver in the
> <driver>_REG_<name> format. Personally I prefer the format to be
> <driver>_<name>_REG. That way a grep for <driver>_<name> will
> return both the register and bit uses.
>
> Currently the <driver>_REG_<name> form is not as common in comedi.
> Looks like it's only used in amcc_35933.h and will be in daqboard2000.c.
>
> The <driver>_<name>_REG form is used a lot.
>
> Not a big deal, just a comment.
It makes it easier to distinguish the register offsets from the register
values, imho.
--
-=( Ian Abbott @ MEV Ltd. E-mail: <abbotti@mev.co.uk> )=-
-=( Web: http://www.mev.co.uk/ )=-
^ permalink raw reply [flat|nested] 28+ messages in thread
* RE: [PATCH 04/20] staging: comedi: drivers: re-do macros for PLX PCI 9080 LASxRR values
2016-05-20 13:49 ` [PATCH 04/20] staging: comedi: drivers: re-do macros for PLX PCI 9080 LASxRR values Ian Abbott
@ 2016-05-20 16:37 ` Hartley Sweeten
2016-05-20 17:17 ` Ian Abbott
0 siblings, 1 reply; 28+ messages in thread
From: Hartley Sweeten @ 2016-05-20 16:37 UTC (permalink / raw)
To: Ian Abbott, devel; +Cc: Greg Kroah-Hartman, linux-kernel
On Friday, May 20, 2016 6:49 AM, Ian Abbott wrote:
> Rename the macros for the PLX PCI 9080 LAS0RR and LAS1RR registers in
> "plx9080.h", using the prefix `PLX_LASRR_`. Make use of the `BIT(x)`
> and `GENMASK(h,l)` macros to define the values.
>
> Define a macro `PLX_LASRR_PREFETCH` for the "prefetchable memory" bit in
> this register, and define a macro `PLX_LASRR_MLOC_MASK` to mask the PCI
> memory location control bits.
>
> Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
> ---
[snip]
> diff --git a/drivers/staging/comedi/drivers/plx9080.h b/drivers/staging/comedi/drivers/plx9080.h
> index 92d2480..8788117 100644
> --- a/drivers/staging/comedi/drivers/plx9080.h
> +++ b/drivers/staging/comedi/drivers/plx9080.h
> @@ -54,14 +54,16 @@ struct plx_dma_desc {
> /* Local Address Space 1 Range Register */
> #define PLX_REG_LAS1RR 0x00f0
>
> -#define LRNG_IO 0x00000001 /* Map to: 1=I/O, 0=Mem */
> -#define LRNG_ANY32 0x00000000 /* Locate anywhere in 32 bit */
> -#define LRNG_LT1MB 0x00000002 /* Locate in 1st meg */
> -#define LRNG_ANY64 0x00000004 /* Locate anywhere in 64 bit */
> -/* bits that specify range for memory io */
> -#define LRNG_MEM_MASK 0xfffffff0
> -/* bits that specify range for normal io */
> -#define LRNG_IO_MASK 0xfffffffc
> +#define PLX_LASRR_IO BIT(0) /* Map to: 1=I/O, 0=Mem */
> +#define PLX_LASRR_ANY32 (BIT(1) * 0) /* Locate anywhere in 32 bit */
> +#define PLX_LASRR_LT1MB (BIT(1) * 1) /* Locate in 1st meg */
> +#define PLX_LASRR_ANY64 (BIT(1) * 2) /* Locate anywhere in 64 bit */
The (BIT(n) * x) looks ugly.
These bit define the memory space encoding. I would prefer something
like this:
#define PLX_LASSR_MLOC(x) (((x) & 0x3) << 1)
#define PLX_LASSR_MLOC_ANY32 PLX_LASSR_MLOC(0)
#define PLX_LASSR_MLOC_LT1MB PLX_LASSR_MLOC(1)
#define PLX_LASSR_MLOC_ANY64 PLX_LASSR_MLOC(2)
> +#define PLX_LASRR_MLOC_MASK GENMASK(2, 1) /* Memory location bits */
I guess the GENMASK() macro is common but it's currently
not used by any of the comedi code.
Using the macro above, the 'mask' would be:
#define PLX_LASSR_MLOC_MASK PLX_LASSR_MLOC(3)
> +#define PLX_LASRR_PREFETCH BIT(3) /* Memory is prefetchable */
> +/* bits that specify range for memory space decode bits */
> +#define PLX_LASRR_MEM_MASK GENMASK(31, 4)
> +/* bits that specify range for i/o space decode bits */
> +#define PLX_LASRR_IO_MASK GENMASK(31, 2)
I suppose the GENMASK() use makes sense for these.
Regards,
Hartley
^ permalink raw reply [flat|nested] 28+ messages in thread
* RE: [PATCH 03/20] staging: comedi: drivers: rename PLX PCI 9080 register offsets
2016-05-20 16:30 ` Ian Abbott
@ 2016-05-20 16:51 ` Hartley Sweeten
0 siblings, 0 replies; 28+ messages in thread
From: Hartley Sweeten @ 2016-05-20 16:51 UTC (permalink / raw)
To: Ian Abbott, devel; +Cc: Greg Kroah-Hartman, linux-kernel
On Friday, May 20, 2016 9:31 AM, Ian Abbott wrote:
> On 20/05/16 17:21, Hartley Sweeten wrote:
>> Just an comment on your renaming.
>>
>> You also renamed the registers in the daqbook2000 driver in the
>> <driver>_REG_<name> format. Personally I prefer the format to be
>> <driver>_<name>_REG. That way a grep for <driver>_<name> will
>> return both the register and bit uses.
>
> It makes it easier to distinguish the register offsets from the register
> values, imho.
I guess. It's just not as common in comedi right now and it does make
grep'ing for all the register/bit uses a bit more cumbersome.
Regards,
Hartley
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 04/20] staging: comedi: drivers: re-do macros for PLX PCI 9080 LASxRR values
2016-05-20 16:37 ` Hartley Sweeten
@ 2016-05-20 17:17 ` Ian Abbott
2016-05-20 17:52 ` Hartley Sweeten
0 siblings, 1 reply; 28+ messages in thread
From: Ian Abbott @ 2016-05-20 17:17 UTC (permalink / raw)
To: Hartley Sweeten, devel; +Cc: Greg Kroah-Hartman, linux-kernel
On 20/05/16 17:37, Hartley Sweeten wrote:
> On Friday, May 20, 2016 6:49 AM, Ian Abbott wrote:
>> Rename the macros for the PLX PCI 9080 LAS0RR and LAS1RR registers in
>> "plx9080.h", using the prefix `PLX_LASRR_`. Make use of the `BIT(x)`
>> and `GENMASK(h,l)` macros to define the values.
>>
>> Define a macro `PLX_LASRR_PREFETCH` for the "prefetchable memory" bit in
>> this register, and define a macro `PLX_LASRR_MLOC_MASK` to mask the PCI
>> memory location control bits.
>>
>> Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
>> ---
>
> [snip]
>
>> diff --git a/drivers/staging/comedi/drivers/plx9080.h b/drivers/staging/comedi/drivers/plx9080.h
>> index 92d2480..8788117 100644
>> --- a/drivers/staging/comedi/drivers/plx9080.h
>> +++ b/drivers/staging/comedi/drivers/plx9080.h
>> @@ -54,14 +54,16 @@ struct plx_dma_desc {
>> /* Local Address Space 1 Range Register */
>> #define PLX_REG_LAS1RR 0x00f0
>>
>> -#define LRNG_IO 0x00000001 /* Map to: 1=I/O, 0=Mem */
>> -#define LRNG_ANY32 0x00000000 /* Locate anywhere in 32 bit */
>> -#define LRNG_LT1MB 0x00000002 /* Locate in 1st meg */
>> -#define LRNG_ANY64 0x00000004 /* Locate anywhere in 64 bit */
>> -/* bits that specify range for memory io */
>> -#define LRNG_MEM_MASK 0xfffffff0
>> -/* bits that specify range for normal io */
>> -#define LRNG_IO_MASK 0xfffffffc
>> +#define PLX_LASRR_IO BIT(0) /* Map to: 1=I/O, 0=Mem */
>> +#define PLX_LASRR_ANY32 (BIT(1) * 0) /* Locate anywhere in 32 bit */
>> +#define PLX_LASRR_LT1MB (BIT(1) * 1) /* Locate in 1st meg */
>> +#define PLX_LASRR_ANY64 (BIT(1) * 2) /* Locate anywhere in 64 bit */
>
> The (BIT(n) * x) looks ugly.
You won't like the remaining patches then!
FWIW, all the constants end up with the same type (unsigned long) this way.
I have been looking for a solution to the problem where random people
change something like this:
#define MY_COOLREG_VAL_FOO (0 << 5)
#define MY_COOLREG_VAL_BAR (1 << 5)
#define MY_COOLREG_VAL_BAZ (2 << 5)
to:
#define MY_COOLREG_VAL_FOO (0 << 5)
#define MY_COOLREG_VAL_BAR BIT(5)
#define MY_COOLREG_VAL_BAZ (2 << 5)
and this seemed like one way to do it.
> These bit define the memory space encoding. I would prefer something
> like this:
>
> #define PLX_LASSR_MLOC(x) (((x) & 0x3) << 1)
> #define PLX_LASSR_MLOC_ANY32 PLX_LASSR_MLOC(0)
> #define PLX_LASSR_MLOC_LT1MB PLX_LASSR_MLOC(1)
> #define PLX_LASSR_MLOC_ANY64 PLX_LASSR_MLOC(2)
>
>> +#define PLX_LASRR_MLOC_MASK GENMASK(2, 1) /* Memory location bits */
>
> I guess the GENMASK() macro is common but it's currently
> not used by any of the comedi code.
It is handy when matching it up with the data sheet though. I have a
field that occupies bits 2 and 1. It also doesn't expose a fairly
useless PLX_LASRR_MLOC() macro to the user of the header file.
>
> Using the macro above, the 'mask' would be:
>
> #define PLX_LASSR_MLOC_MASK PLX_LASSR_MLOC(3)
>
>> +#define PLX_LASRR_PREFETCH BIT(3) /* Memory is prefetchable */
>> +/* bits that specify range for memory space decode bits */
>> +#define PLX_LASRR_MEM_MASK GENMASK(31, 4)
>> +/* bits that specify range for i/o space decode bits */
>> +#define PLX_LASRR_IO_MASK GENMASK(31, 2)
>
> I suppose the GENMASK() use makes sense for these.
>
> Regards,
> Hartley
>
--
-=( Ian Abbott @ MEV Ltd. E-mail: <abbotti@mev.co.uk> )=-
-=( Web: http://www.mev.co.uk/ )=-
^ permalink raw reply [flat|nested] 28+ messages in thread
* RE: [PATCH 04/20] staging: comedi: drivers: re-do macros for PLX PCI 9080 LASxRR values
2016-05-20 17:17 ` Ian Abbott
@ 2016-05-20 17:52 ` Hartley Sweeten
2016-05-23 11:21 ` Ian Abbott
0 siblings, 1 reply; 28+ messages in thread
From: Hartley Sweeten @ 2016-05-20 17:52 UTC (permalink / raw)
To: Ian Abbott, devel; +Cc: Greg Kroah-Hartman, linux-kernel
On Friday, May 20, 2016 10:18 AM, Ian Abbott wrote:
> On 20/05/16 17:37, Hartley Sweeten wrote:
>> On Friday, May 20, 2016 6:49 AM, Ian Abbott wrote:
>>> Rename the macros for the PLX PCI 9080 LAS0RR and LAS1RR registers in
>>> "plx9080.h", using the prefix `PLX_LASRR_`. Make use of the `BIT(x)`
>>> and `GENMASK(h,l)` macros to define the values.
>>>
>>> Define a macro `PLX_LASRR_PREFETCH` for the "prefetchable memory" bit in
>>> this register, and define a macro `PLX_LASRR_MLOC_MASK` to mask the PCI
>>> memory location control bits.
[snip]
>>> +#define PLX_LASRR_IO BIT(0) /* Map to: 1=I/O, 0=Mem */
>>> +#define PLX_LASRR_ANY32 (BIT(1) * 0) /* Locate anywhere in 32 bit */
>>> +#define PLX_LASRR_LT1MB (BIT(1) * 1) /* Locate in 1st meg */
>>> +#define PLX_LASRR_ANY64 (BIT(1) * 2) /* Locate anywhere in 64 bit */
>>
>> The (BIT(n) * x) looks ugly.
>
> You won't like the remaining patches then!
You are correct... ;-)
> FWIW, all the constants end up with the same type (unsigned long) this way.
That's probably good but it sure makes the defines look ugly, and a bit hard to
understand imoh. You also don't know what the 'max' value for the bit-field
is without further digging.
I applied your whole series to see what the final header looks like. To me it
actually looks worse than the original.
The original had a number of whitespace issues that made it hard to follow and
the defines were lacking namespace. Personally I also don't can for all the enums
since the symbols are not actually used as enums just as raw values. But the 'bit'
usage of the registers was fairly clear.
With your series applied the whtespace and namespace issues are addressed.
You also converted all the enums to defines which is great. But the 'bit' usage
now is a bit muddled. I really don't care for the (BIT(n) * (x)) stuff. There are
also the various, unused and unnecessary, <foo>_SHIFT defines. Those just
add additional cruft.
I'm also not sure if all the bits require a comment. They seem to clutter the
header. Datasheets for the PLX-9080 are easy to find. Maybe just have a
comment for each register and remove all the bit comments.
> I have been looking for a solution to the problem where random people
> change something like this:
>
> #define MY_COOLREG_VAL_FOO (0 << 5)
> #define MY_COOLREG_VAL_BAR (1 << 5)
> #define MY_COOLREG_VAL_BAZ (2 << 5)
>
> to:
>
> #define MY_COOLREG_VAL_FOO (0 << 5)
> #define MY_COOLREG_VAL_BAR BIT(5)
> #define MY_COOLREG_VAL_BAZ (2 << 5)
>
> and this seemed like one way to do it.
Like I stated previously, I prefer something like this for the multi-bit
fields of a register.
>> #define PLX_LASSR_MLOC(x) (((x) & 0x3) << 1)
>> #define PLX_LASSR_MLOC_ANY32 PLX_LASSR_MLOC(0)
>> #define PLX_LASSR_MLOC_LT1MB PLX_LASSR_MLOC(1)
>> #define PLX_LASSR_MLOC_ANY64 PLX_LASSR_MLOC(2)
>> #define PLX_LASSR_MLOC_MASK PLX_LASSR_MLOC(3)
>
> It is handy when matching it up with the data sheet though. I have a
> field that occupies bits 2 and 1. It also doesn't expose a fairly
> useless PLX_LASRR_MLOC() macro to the user of the header file.
The (BIT(n) * (x)) just looks odd.
The GENMASK() for a multi-bit field also makes it more difficult to
figure out what the maximum value for the field is when there are
more than just a few bits and the lower bit is not 0.
Anyway.. Technically it looks like your series doesn't break anything
I just don't feel that it adds much clarity.
I'm still looking it over... Maybe I'll change my mind... ;-)
Regards,
Hartley
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 04/20] staging: comedi: drivers: re-do macros for PLX PCI 9080 LASxRR values
2016-05-20 17:52 ` Hartley Sweeten
@ 2016-05-23 11:21 ` Ian Abbott
0 siblings, 0 replies; 28+ messages in thread
From: Ian Abbott @ 2016-05-23 11:21 UTC (permalink / raw)
To: Hartley Sweeten, devel; +Cc: Greg Kroah-Hartman, linux-kernel
On 20/05/16 18:52, Hartley Sweeten wrote:
> On Friday, May 20, 2016 10:18 AM, Ian Abbott wrote:
>> On 20/05/16 17:37, Hartley Sweeten wrote:
>>> On Friday, May 20, 2016 6:49 AM, Ian Abbott wrote:
>>>> Rename the macros for the PLX PCI 9080 LAS0RR and LAS1RR registers in
>>>> "plx9080.h", using the prefix `PLX_LASRR_`. Make use of the `BIT(x)`
>>>> and `GENMASK(h,l)` macros to define the values.
>>>>
>>>> Define a macro `PLX_LASRR_PREFETCH` for the "prefetchable memory" bit in
>>>> this register, and define a macro `PLX_LASRR_MLOC_MASK` to mask the PCI
>>>> memory location control bits.
>
> [snip]
>
>>>> +#define PLX_LASRR_IO BIT(0) /* Map to: 1=I/O, 0=Mem */
>>>> +#define PLX_LASRR_ANY32 (BIT(1) * 0) /* Locate anywhere in 32 bit */
>>>> +#define PLX_LASRR_LT1MB (BIT(1) * 1) /* Locate in 1st meg */
>>>> +#define PLX_LASRR_ANY64 (BIT(1) * 2) /* Locate anywhere in 64 bit */
>>>
>>> The (BIT(n) * x) looks ugly.
>>
>> You won't like the remaining patches then!
>
> You are correct... ;-)
>
>> FWIW, all the constants end up with the same type (unsigned long) this way.
>
> That's probably good but it sure makes the defines look ugly, and a bit hard to
> understand imoh. You also don't know what the 'max' value for the bit-field
> is without further digging.
Where the values are just predefined constants, you don't need to know
the 'max' value. For cases where the value is a macro parameter, I
ANDed the value with a bit-mask, although calling the macro with an
out-of-range value is a bad idea anyway!
> I applied your whole series to see what the final header looks like. To me it
> actually looks worse than the original.
>
> The original had a number of whitespace issues that made it hard to follow and
> the defines were lacking namespace. Personally I also don't can for all the enums
> since the symbols are not actually used as enums just as raw values. But the 'bit'
> usage of the registers was fairly clear.
>
> With your series applied the whtespace and namespace issues are addressed.
> You also converted all the enums to defines which is great. But the 'bit' usage
> now is a bit muddled. I really don't care for the (BIT(n) * (x)) stuff. There are
> also the various, unused and unnecessary, <foo>_SHIFT defines. Those just
> add additional cruft.
The PLX_FOO_BAR_SHIFT defines are there to make it possible to extract
the field value from the register value using (reg_val &
PLX_FOO_BAR_MASK) >> PLX_FOO_BAR_SHIFT. I only did that when the field
value is parameterized in the PLX_FOO_BAR(x) macro. The alternative
would be to define PLX_FOO_TO_BAR(r) macros to do the same thing. I had
to do that anyway for the 'PAFL' field of the DMPBAM register due to its
unusual layout.
> I'm also not sure if all the bits require a comment. They seem to clutter the
> header. Datasheets for the PLX-9080 are easy to find. Maybe just have a
> comment for each register and remove all the bit comments.
(You used to have to create an account on plxtech.com to download the
datasheets, but that is no longer necessary since it became part of Avago.)
Some of the abbreviations used in the macro names are a bit contrived
for brevity, so I think the comments help to pin them down in the
datasheet. Of course, the comments are no substitution for the actual
datasheet.
>> I have been looking for a solution to the problem where random people
>> change something like this:
>>
>> #define MY_COOLREG_VAL_FOO (0 << 5)
>> #define MY_COOLREG_VAL_BAR (1 << 5)
>> #define MY_COOLREG_VAL_BAZ (2 << 5)
>>
>> to:
>>
>> #define MY_COOLREG_VAL_FOO (0 << 5)
>> #define MY_COOLREG_VAL_BAR BIT(5)
>> #define MY_COOLREG_VAL_BAZ (2 << 5)
>>
>> and this seemed like one way to do it.
>
> Like I stated previously, I prefer something like this for the multi-bit
> fields of a register.
>
>>> #define PLX_LASSR_MLOC(x) (((x) & 0x3) << 1)
>>> #define PLX_LASSR_MLOC_ANY32 PLX_LASSR_MLOC(0)
>>> #define PLX_LASSR_MLOC_LT1MB PLX_LASSR_MLOC(1)
>>> #define PLX_LASSR_MLOC_ANY64 PLX_LASSR_MLOC(2)
>>> #define PLX_LASSR_MLOC_MASK PLX_LASSR_MLOC(3)
>>
>> It is handy when matching it up with the data sheet though. I have a
>> field that occupies bits 2 and 1. It also doesn't expose a fairly
>> useless PLX_LASRR_MLOC() macro to the user of the header file.
>
> The (BIT(n) * (x)) just looks odd.
To be honest, I think the only benefit of using BIT(n) rather than 1 <<
n is that it forces some type consistency, particularly when the value
being shifted is a plain 'int' and there is some possibility of shifting
beyond bit 30.
With your way of doing it, you need to start adding type casts if the
field extends into bit 31.
> The GENMASK() for a multi-bit field also makes it more difficult to
> figure out what the maximum value for the field is when there are
> more than just a few bits and the lower bit is not 0.
That's true, although in cases where it matters (where the value is
supplied as a parameter), the maximum value is in a bit-mask. One thing
about the GENMASK() macro is that it ties in nicely with how the
datasheet defines the multi-bit fields.
>
> Anyway.. Technically it looks like your series doesn't break anything
> I just don't feel that it adds much clarity.
>
> I'm still looking it over... Maybe I'll change my mind... ;-)
>
> Regards,
> Hartley
>
>
--
-=( Ian Abbott @ MEV Ltd. E-mail: <abbotti@mev.co.uk> )=-
-=( Web: http://www.mev.co.uk/ )=-
^ permalink raw reply [flat|nested] 28+ messages in thread
end of thread, other threads:[~2016-05-23 11:21 UTC | newest]
Thread overview: 28+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-05-20 13:49 [PATCH 00/20] staging: comedi: re-do drivers/plx9080.h Ian Abbott
2016-05-20 13:49 ` [PATCH 01/20] staging: comedi: plx9080.h: correct LRNG_IO_MASK and LMAP_IO_MASK Ian Abbott
2016-05-20 13:49 ` [PATCH 02/20] staging: comedi: plx9080.h: remove Power-Up Test Suite stuff Ian Abbott
2016-05-20 13:49 ` [PATCH 03/20] staging: comedi: drivers: rename PLX PCI 9080 register offsets Ian Abbott
2016-05-20 16:21 ` Hartley Sweeten
2016-05-20 16:30 ` Ian Abbott
2016-05-20 16:51 ` Hartley Sweeten
2016-05-20 13:49 ` [PATCH 04/20] staging: comedi: drivers: re-do macros for PLX PCI 9080 LASxRR values Ian Abbott
2016-05-20 16:37 ` Hartley Sweeten
2016-05-20 17:17 ` Ian Abbott
2016-05-20 17:52 ` Hartley Sweeten
2016-05-23 11:21 ` Ian Abbott
2016-05-20 13:49 ` [PATCH 05/20] staging: comedi: drivers: re-do macros for PLX PCI 9080 LASxBA values Ian Abbott
2016-05-20 13:49 ` [PATCH 06/20] staging: comedi: drivers: re-do PLX PCI 9080 MARBR register values Ian Abbott
2016-05-20 13:49 ` [PATCH 07/20] staging: comedi: drivers: re-do PLX PCI 9080 BIGEND " Ian Abbott
2016-05-20 13:49 ` [PATCH 08/20] staging: comedi: drivers: re-do PLX PCI 9080 LBRDx " Ian Abbott
2016-05-20 13:49 ` [PATCH 09/20] staging: comedi: drivers: re-do PLX PCI 9080 DMPBAM " Ian Abbott
2016-05-20 13:49 ` [PATCH 10/20] staging: comedi: drivers: re-do PLX PCI 9080 DMCFGA " Ian Abbott
2016-05-20 13:49 ` [PATCH 11/20] staging: comedi: drivers: re-do PLX PCI 9080 INTCSR " Ian Abbott
2016-05-20 13:49 ` [PATCH 12/20] staging: comedi: drivers: re-do PLX PCI 9080 CNTRL " Ian Abbott
2016-05-20 13:49 ` [PATCH 13/20] staging: comedi: plx9080.h: add hard-coded PCIHIDR register value Ian Abbott
2016-05-20 13:49 ` [PATCH 14/20] staging: comedi: drivers: re-do PLX PCI 9080 DMAMODEx register values Ian Abbott
2016-05-20 13:49 ` [PATCH 15/20] staging: comedi: drivers: re-do PLX PCI 9080 DMADPRx " Ian Abbott
2016-05-20 13:49 ` [PATCH 16/20] staging: comedi: drivers: re-do PLX PCI 9080 DMACSRx " Ian Abbott
2016-05-20 13:49 ` [PATCH 17/20] staging: comedi: drivers: add PLX PCI 9080 DMATHR " Ian Abbott
2016-05-20 13:49 ` [PATCH 18/20] staging: comedi: plx9080.h: tidy up some comments Ian Abbott
2016-05-20 13:49 ` [PATCH 19/20] staging: comedi: plx9080.h: Add kerneldoc comments Ian Abbott
2016-05-20 13:49 ` [PATCH 20/20] staging: comedi: plx9080.h: include headers for declarations Ian Abbott
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