From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756723AbcE0Uls (ORCPT ); Fri, 27 May 2016 16:41:48 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:4841 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756499AbcE0Uiq (ORCPT ); Fri, 27 May 2016 16:38:46 -0400 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Fri, 27 May 2016 13:37:03 -0700 From: Rhyland Klein To: Peter De Schrijver , Thierry Reding CC: Michael Turquette , Stephen Boyd , Alexandre Courbot , , , , Stephen Warren , Rhyland Klein Subject: [PATCH v2 04/11] clk: tegra30: Mark certain clks as critical Date: Fri, 27 May 2016 16:38:07 -0400 Message-ID: <1464381494-27096-5-git-send-email-rklein@nvidia.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1464381494-27096-1-git-send-email-rklein@nvidia.com> References: <1464381494-27096-1-git-send-email-rklein@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Mark the required clks as critical so the core will enable them during registration and therefore they will stay on. Signed-off-by: Rhyland Klein --- drivers/clk/tegra/clk-tegra30.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index 9396f4930da7..fc91460ab892 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -948,8 +948,8 @@ static void __init tegra30_pll_init(void) /* PLLM */ clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, pmc_base, - CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE, - &pll_m_params, NULL); + CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE | + CLK_IS_CRITICAL, &pll_m_params, NULL); clks[TEGRA30_CLK_PLL_M] = clk; /* PLLM_OUT1 */ @@ -1104,7 +1104,8 @@ static void __init tegra30_super_clk_init(void) /* twd */ clk = clk_register_fixed_factor(NULL, "twd", "cclk_g", - CLK_SET_RATE_PARENT, 1, 2); + CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + 1, 2); clks[TEGRA30_CLK_TWD] = clk; tegra_super_clk_gen4_init(clk_base, pmc_base, tegra30_clks, NULL); @@ -1164,11 +1165,12 @@ static void __init tegra30_periph_clk_init(void) /* emc */ clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, ARRAY_SIZE(mux_pllmcp_clkm), - CLK_SET_RATE_NO_REPARENT, + CLK_SET_RATE_NO_REPARENT | CLK_IS_CRITICAL, clk_base + CLK_SOURCE_EMC, 30, 2, 0, &emc_lock); - clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0, - 57, periph_clk_enb_refcnt); + clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, + CLK_IS_CRITICAL, 57, + periph_clk_enb_refcnt); clks[TEGRA30_CLK_EMC] = clk; clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC, -- 1.9.1