From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755305AbcE1J41 (ORCPT ); Sat, 28 May 2016 05:56:27 -0400 Received: from mail.kernel.org ([198.145.29.136]:39934 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753884AbcE1J4X (ORCPT ); Sat, 28 May 2016 05:56:23 -0400 From: Krzysztof Kozlowski To: Kukjin Kim , Krzysztof Kozlowski , Sylwester Nawrocki , Tomasz Figa , Michael Turquette , Stephen Boyd , linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Cc: Javier Martinez Canillas , Rob Herring , Krzysztof Kozlowski Subject: [PATCH v5 19/22] clk: samsung: exynos5410: Add I2C, HSI2C and RTC clocks Date: Sat, 28 May 2016 11:54:30 +0200 Message-Id: <1464429273-23457-20-git-send-email-krzk@kernel.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1464429273-23457-1-git-send-email-krzk@kernel.org> References: <1464429273-23457-1-git-send-email-krzk@kernel.org> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add clocks for I2C, USI (HSI2C) and RTC to the Exynos5410 clock driver. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas --- drivers/clk/samsung/clk-exynos5410.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/clk/samsung/clk-exynos5410.c b/drivers/clk/samsung/clk-exynos5410.c index 5f892128849a..6c2e59c576ee 100644 --- a/drivers/clk/samsung/clk-exynos5410.c +++ b/drivers/clk/samsung/clk-exynos5410.c @@ -159,6 +159,7 @@ static struct samsung_div_clock exynos5410_div_clks[] __initdata = { static struct samsung_gate_clock exynos5410_gate_clks[] __initdata = { GATE(CLK_MCT, "mct", "aclk66", GATE_IP_PERIS, 18, 0, 0), + GATE(CLK_RTC, "rtc", "aclk66", GATE_IP_PERIS, 20, 0, 0), GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0", SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0), @@ -187,6 +188,14 @@ static struct samsung_gate_clock exynos5410_gate_clks[] __initdata = { GATE(CLK_UART1, "uart1", "aclk66", GATE_IP_PERIC, 1, 0, 0), GATE(CLK_UART2, "uart2", "aclk66", GATE_IP_PERIC, 2, 0, 0), GATE(CLK_UART3, "uart3", "aclk66", GATE_IP_PERIC, 3, 0, 0), + GATE(CLK_I2C0, "i2c0", "aclk66", GATE_IP_PERIC, 6, 0, 0), + GATE(CLK_I2C1, "i2c1", "aclk66", GATE_IP_PERIC, 7, 0, 0), + GATE(CLK_I2C2, "i2c2", "aclk66", GATE_IP_PERIC, 8, 0, 0), + GATE(CLK_I2C3, "i2c3", "aclk66", GATE_IP_PERIC, 9, 0, 0), + GATE(CLK_USI0, "usi0", "aclk66", GATE_IP_PERIC, 10, 0, 0), + GATE(CLK_USI1, "usi1", "aclk66", GATE_IP_PERIC, 11, 0, 0), + GATE(CLK_USI2, "usi2", "aclk66", GATE_IP_PERIC, 12, 0, 0), + GATE(CLK_USI3, "usi3", "aclk66", GATE_IP_PERIC, 13, 0, 0), GATE(CLK_PWM, "pwm", "aclk66", GATE_IP_PERIC, 24, 0, 0), GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0", -- 2.7.4