[PATCH 0/5] Patches for QCOM IPQ4019 clock driver

[PATCH 0/5] Patches for QCOM IPQ4019 clock driver

[Abhishek Sahu]

These patches are related to Qualcomm IPQ4019 GCC (Global Clock
Controller) driver code mainly adding support for multiple CPU
frequencies and corrected fixed clock values.

Abhishek Sahu (5):
  clk: qcom: ipq4019: Modified the fixed clock rate to proper values
  clk: qcom: ipq4019: Added the apss cpu pll divider clock node
  clk: qcom: ipq4019: Added the cpu pll divider and changed regmap limit
  clk: qcom: ipq4019: Added the cpu clock frequency change notifier
  clk: qcom: ipq4019: Added the turbo frequency for apps cpu

 drivers/clk/qcom/gcc-ipq4019.c               | 195 +++++++++++++++++++++++++--
 include/dt-bindings/clock/qcom,gcc-ipq4019.h |   1 +
 2 files changed, 183 insertions(+), 13 deletions(-)

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 1/5] clk: qcom: ipq4019: Modified the fixed clock rate to proper values

[Abhishek Sahu]

Modified the fixed clock rate initialization in the IPQ4019 clock
probe function with correct values.

Also some of the fixed clocks entries were not added in the current
driver file so added the same.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
 drivers/clk/qcom/gcc-ipq4019.c | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/drivers/clk/qcom/gcc-ipq4019.c
index 3cd1af0..db24cb8 100644
--- a/drivers/clk/qcom/gcc-ipq4019.c
+++ b/drivers/clk/qcom/gcc-ipq4019.c
@@ -80,7 +80,7 @@ static struct parent_map gcc_xo_sdcc1_500_map[] = {
 
 static const char * const gcc_xo_sdcc1_500[] = {
 	"xo",
-	"ddrpll",
+	"ddrpllsdcc",
 	"fepll500",
 };
 
@@ -1317,13 +1317,15 @@ static int gcc_ipq4019_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
 
-	clk_register_fixed_rate(dev, "fepll125", "xo", 0, 200000000);
-	clk_register_fixed_rate(dev, "fepll125dly", "xo", 0, 200000000);
-	clk_register_fixed_rate(dev, "fepllwcss2g", "xo", 0, 200000000);
-	clk_register_fixed_rate(dev, "fepllwcss5g", "xo", 0, 200000000);
+	clk_register_fixed_rate(dev, "fepll125", "xo", 0, 125000000);
+	clk_register_fixed_rate(dev, "fepll125dly", "xo", 0, 125000000);
+	clk_register_fixed_rate(dev, "fepllwcss2g", "xo", 0, 250000000);
+	clk_register_fixed_rate(dev, "fepllwcss5g", "xo", 0, 250000000);
 	clk_register_fixed_rate(dev, "fepll200", "xo", 0, 200000000);
-	clk_register_fixed_rate(dev, "fepll500", "xo", 0, 200000000);
+	clk_register_fixed_rate(dev, "fepll500", "xo", 0, 500000000);
 	clk_register_fixed_rate(dev, "ddrpllapss", "xo", 0, 666000000);
+	clk_register_fixed_rate(dev, "ddrpllsdcc", "xo", 0, 193000000);
+	clk_register_fixed_rate(dev, "pcnoc_clk_src", "xo", 0, 100000000);
 
 	return qcom_cc_probe(pdev, &gcc_ipq4019_desc);
 }
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 2/5] clk: qcom: ipq4019: Added the apss cpu pll divider clock node

[Abhishek Sahu]

The existing code does not have support for all the frequency
supported by APPS CPU. APPS CPU frequency is provided with APSS
CPU PLL divider which divides down the VCO frequency. This divider
is nonlinear and specific to IPQ4019 so the standard divider code
cannot be used for this.

This patch adds new node and its clock operations for APPS CPU clock
divider. Since, this divider is nonlinear, so frequency table is also
added for this, which contains the frequency and its corresponding
hardware divider values.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
 drivers/clk/qcom/gcc-ipq4019.c | 140 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 140 insertions(+)

diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/drivers/clk/qcom/gcc-ipq4019.c
index db24cb8..45f4749 100644
--- a/drivers/clk/qcom/gcc-ipq4019.c
+++ b/drivers/clk/qcom/gcc-ipq4019.c
@@ -20,6 +20,11 @@
 #include <linux/clk-provider.h>
 #include <linux/regmap.h>
 #include <linux/reset-controller.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/bitops.h>
+#include <linux/math64.h>
+#include <asm/div64.h>
 
 #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
 
@@ -28,6 +33,7 @@
 #include "clk-rcg.h"
 #include "clk-branch.h"
 #include "reset.h"
+#include "clk-regmap-divider.h"
 
 enum {
 	P_XO,
@@ -40,6 +46,18 @@ enum {
 	P_DDRPLLAPSS,
 };
 
+#define to_clk_regmap_div(_hw) container_of(to_clk_regmap(_hw),\
+					struct clk_regmap_div, clkr)
+
+#define to_clk_cdiv_rcg(_hw) container_of((to_clk_regmap_div(_hw)),\
+						struct clk_apps_cpu_div, cdiv)
+
+struct clk_apps_cpu_div {
+	struct clk_regmap_div cdiv;
+	const u8	*parent_map;
+	const struct freq_tbl	*freq_tbl;
+};
+
 static struct parent_map gcc_xo_200_500_map[] = {
 	{ P_XO, 0 },
 	{ P_FEPLL200, 1 },
@@ -524,6 +542,128 @@ static struct clk_rcg2  sdcc1_apps_clk_src = {
 	},
 };
 
+/*
+* Round rate function for APPS CPU PLL Clock divider.
+* It Returns the input rate without changing it. The hardware supported rate
+* will be calculated in set function by getting the same from frequency table.
+*/
+static long clk_cpu_div_round_rate(struct clk_hw *hw, unsigned long rate,
+				unsigned long *p_rate)
+{
+	return rate;
+};
+
+/*
+* Clock set rate function for APPS CPU PLL Clock divider.
+* It looks up the frequency table and updates the PLL divider to corresponding
+* divider value.
+*/
+static int clk_cpu_div_set_rate(struct clk_hw *hw, unsigned long rate,
+			      unsigned long parent_rate)
+{
+	struct clk_apps_cpu_div *rcg = to_clk_cdiv_rcg(hw);
+	const struct freq_tbl *f;
+	u32 mask;
+	int ret;
+
+	f = qcom_find_freq(rcg->freq_tbl, rate);
+	if (!f)
+		return -EINVAL;
+
+	mask = (BIT(rcg->cdiv.width) - 1) << rcg->cdiv.shift;
+	ret = regmap_update_bits(rcg->cdiv.clkr.regmap,
+				rcg->cdiv.reg, mask,
+				(f->pre_div << rcg->cdiv.shift) & mask);
+	udelay(1);
+
+	return 0;
+};
+
+/*
+* Clock frequency calculation function for APPS CPU PLL Clock divider.
+* It first calculates the VCO frequency with the parent rate. This clock divider
+* is nonlinear so this function calculates the actual divider and returns the
+* output frequency by dividing VCO Frequency with this actual divider value.
+*/
+static unsigned long clk_cpu_div_recalc_rate(struct clk_hw *hw,
+					   unsigned long parent_rate)
+{
+	struct clk_apps_cpu_div *rcg = to_clk_cdiv_rcg(hw);
+	u32 fdbkdiv, cdiv, rate, pre_div;
+	u32 fdbkdiv_shift = 16, fdbkdiv_mask =  0xff;
+	u64 vco;
+
+	regmap_read(rcg->cdiv.clkr.regmap, rcg->cdiv.reg, &cdiv);
+	fdbkdiv = cdiv & (fdbkdiv_mask << fdbkdiv_shift);
+	fdbkdiv = fdbkdiv >> fdbkdiv_shift;
+
+	cdiv &= (BIT(rcg->cdiv.width) - 1) << rcg->cdiv.shift;
+	cdiv = cdiv >> rcg->cdiv.shift;
+
+	/*
+	* Some dividers have value in 0.5 fraction so multiply both VCO
+	* frequency and pre_div with 2 to make integer calculation.
+	*/
+	vco = parent_rate;
+	vco *= fdbkdiv;
+	vco *= 2;
+
+	if (cdiv > 10)
+		pre_div = (cdiv + 1) * 2;
+	else
+		pre_div = cdiv + 12;
+
+	do_div(vco, pre_div);
+	do_div(vco, 1000000);
+	rate = (u32)vco * 1000000;
+
+	return rate;
+};
+
+const struct clk_ops clk_regmap_cpu_div_ops = {
+	.round_rate = clk_cpu_div_round_rate,
+	.set_rate = clk_cpu_div_set_rate,
+	.recalc_rate = clk_cpu_div_recalc_rate,
+};
+
+static const struct freq_tbl ftbl_apps_ddr_pll[] = {
+	{380000000, P_XO, 0xD, 0},
+	{409000000, P_XO, 0xC, 0, 0},
+	{444000000, P_XO, 0xB, 0, 0},
+	{484000000, P_XO, 0xA, 0, 0},
+	{507000000, P_XO, 0x9, 0, 0},
+	{532000000, P_XO, 0x8, 0, 0},
+	{560000000, P_XO, 0x7, 0, 0},
+	{592000000, P_XO, 0x6, 0, 0},
+	{626000000, P_XO, 0x5, 0, 0},
+	{666000000, P_XO, 0x4, 0, 0},
+	{710000000, P_XO, 0x3, 0, 0},
+	{761000000, P_XO, 0x2, 0, 0},
+	{819000000, P_XO, 0x1, 0, 0},
+	{888000000, P_XO, 0x0, 0, 0},
+	{}
+};
+
+static struct clk_apps_cpu_div gcc_apps_cpu_div_clk = {
+	.cdiv.reg = 0x2E020,
+	.cdiv.shift = 4,
+	.cdiv.width = 4,
+	.cdiv.clkr = {
+		.enable_reg = 0x2E000,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gcc_apps_cpu_div_clk",
+			.parent_names = (const char *[]){
+				"xo",
+			},
+			.num_parents = 1,
+			.ops = &clk_regmap_cpu_div_ops,
+			.flags = CLK_IGNORE_UNUSED,
+		},
+	},
+	.freq_tbl = ftbl_apps_ddr_pll,
+};
+
 static const struct freq_tbl ftbl_gcc_apps_clk[] = {
 	F(48000000, P_XO,	   1, 0, 0),
 	F(200000000, P_FEPLL200,   1, 0, 0),
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 3/5] clk: qcom: ipq4019: Added the cpu pll divider and changed regmap limit

[Abhishek Sahu]

This patch adds the APSS CPU PLL divider in clock framework and
its binding in IPQ4019 device tree binding.

Also, it changed the max_register value to 0x2FFFF in regmap config
to support the APSS CPU PLL divider operations.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
 drivers/clk/qcom/gcc-ipq4019.c               | 6 ++++--
 include/dt-bindings/clock/qcom,gcc-ipq4019.h | 1 +
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/drivers/clk/qcom/gcc-ipq4019.c
index 45f4749..263577c 100644
--- a/drivers/clk/qcom/gcc-ipq4019.c
+++ b/drivers/clk/qcom/gcc-ipq4019.c
@@ -143,7 +143,7 @@ static const char * const gcc_xo_ddr_500_200[] = {
 	"xo",
 	"fepll200",
 	"fepll500",
-	"ddrpllapss",
+	"gcc_apps_cpu_div_clk",
 };
 
 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
@@ -682,6 +682,7 @@ static struct clk_rcg2 apps_clk_src = {
 		.parent_names = gcc_xo_ddr_500_200,
 		.num_parents = 4,
 		.ops = &clk_rcg2_ops,
+		.flags = CLK_SET_RATE_PARENT,
 	},
 };
 
@@ -1355,6 +1356,7 @@ static struct clk_regmap *gcc_ipq4019_clocks[] = {
 	[GCC_WCSS5G_CLK] = &gcc_wcss5g_clk.clkr,
 	[GCC_WCSS5G_REF_CLK] = &gcc_wcss5g_ref_clk.clkr,
 	[GCC_WCSS5G_RTC_CLK] = &gcc_wcss5g_rtc_clk.clkr,
+	[GCC_APPS_CLK_CPU_DIV] = &gcc_apps_cpu_div_clk.cdiv.clkr,
 };
 
 static const struct qcom_reset_map gcc_ipq4019_resets[] = {
@@ -1435,7 +1437,7 @@ static const struct regmap_config gcc_ipq4019_regmap_config = {
 	.reg_bits	= 32,
 	.reg_stride	= 4,
 	.val_bits	= 32,
-	.max_register	= 0x2dfff,
+	.max_register	= 0x2FFFF,
 	.fast_io	= true,
 };
 
diff --git a/include/dt-bindings/clock/qcom,gcc-ipq4019.h b/include/dt-bindings/clock/qcom,gcc-ipq4019.h
index 6240e5b..417a722 100644
--- a/include/dt-bindings/clock/qcom,gcc-ipq4019.h
+++ b/include/dt-bindings/clock/qcom,gcc-ipq4019.h
@@ -154,5 +154,6 @@
 #define GCC_QDSS_BCR					69
 #define GCC_MPM_BCR					70
 #define GCC_SPDM_BCR					71
+#define GCC_APPS_CLK_CPU_DIV				72
 
 #endif
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 4/5] clk: qcom: ipq4019: Added the cpu clock frequency change notifier

[Abhishek Sahu]

The current IPQ4019 clock driver code gives the crash or gets hang
while switching the CPU frequency some time. The APSS CPU Clock
divider is not glitch free so the APPS clock need to be switched for
stable clock duringthe change.

This patch adds the frequency change notifier for APSS CPU clock.
It changes the parent of this clock to stable PLL FEPLL500 when it
gets for PRE_RATE_CHANGE event. This event will be generated before
actual clock set operations. The clock set operation will again change
its corresponding parent by getting the same from frequency table.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
 drivers/clk/qcom/gcc-ipq4019.c | 26 +++++++++++++++++++++++++-
 1 file changed, 25 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/drivers/clk/qcom/gcc-ipq4019.c
index 263577c..69a8250 100644
--- a/drivers/clk/qcom/gcc-ipq4019.c
+++ b/drivers/clk/qcom/gcc-ipq4019.c
@@ -1455,9 +1455,27 @@ static const struct of_device_id gcc_ipq4019_match_table[] = {
 };
 MODULE_DEVICE_TABLE(of, gcc_ipq4019_match_table);
 
+int cpu_clk_notifier_fn(struct notifier_block *nb,
+			unsigned long action, void *data)
+{
+	int err = 0;
+
+	if (action == PRE_RATE_CHANGE) {
+		err = clk_rcg2_ops.set_parent(&apps_clk_src.clkr.hw,
+							P_FEPLL500);
+	}
+
+	return notifier_from_errno(err);
+}
+
+struct notifier_block cpu_clk_notifier = {
+	.notifier_call = cpu_clk_notifier_fn,
+};
+
 static int gcc_ipq4019_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
+	int err;
 
 	clk_register_fixed_rate(dev, "fepll125", "xo", 0, 125000000);
 	clk_register_fixed_rate(dev, "fepll125dly", "xo", 0, 125000000);
@@ -1469,7 +1487,13 @@ static int gcc_ipq4019_probe(struct platform_device *pdev)
 	clk_register_fixed_rate(dev, "ddrpllsdcc", "xo", 0, 193000000);
 	clk_register_fixed_rate(dev, "pcnoc_clk_src", "xo", 0, 100000000);
 
-	return qcom_cc_probe(pdev, &gcc_ipq4019_desc);
+	err = qcom_cc_probe(pdev, &gcc_ipq4019_desc);
+
+	if (!err)
+		clk_notifier_register(apps_clk_src.clkr.hw.clk,
+					&cpu_clk_notifier);
+
+	return err;
 }
 
 static struct platform_driver gcc_ipq4019_driver = {
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 5/5] clk: qcom: ipq4019: Added the turbo frequency for apps cpu

[Abhishek Sahu]

Added the CPU turbo frequency (710 Mhz) to frequency table of
APPS CPU clock.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
 drivers/clk/qcom/gcc-ipq4019.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/drivers/clk/qcom/gcc-ipq4019.c
index 69a8250..c325618 100644
--- a/drivers/clk/qcom/gcc-ipq4019.c
+++ b/drivers/clk/qcom/gcc-ipq4019.c
@@ -665,11 +665,12 @@ static struct clk_apps_cpu_div gcc_apps_cpu_div_clk = {
 };
 
 static const struct freq_tbl ftbl_gcc_apps_clk[] = {
-	F(48000000, P_XO,	   1, 0, 0),
-	F(200000000, P_FEPLL200,   1, 0, 0),
-	F(500000000, P_FEPLL500,   1, 0, 0),
+	F(48000000, P_XO, 1, 0, 0),
+	F(200000000, P_FEPLL200, 1, 0, 0),
+	F(500000000, P_FEPLL500, 1, 0, 0),
 	F(626000000, P_DDRPLLAPSS, 1, 0, 0),
-	{ }
+	F(710000000, P_DDRPLLAPSS, 1, 0, 0),
+	{}
 };
 
 static struct clk_rcg2 apps_clk_src = {
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH 1/5] clk: qcom: ipq4019: Modified the fixed clock rate to proper values

[Stephen Boyd]

On 05/30, Abhishek Sahu wrote:
> Modified the fixed clock rate initialization in the IPQ4019 clock
> probe function with correct values.
> 
> Also some of the fixed clocks entries were not added in the current
> driver file so added the same.
> 
> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>

This was a temporary solution until the PLL recalc code could be
written. When is the real clk driver coming so we can get rid of
these fixed rate clks being registered in this driver?

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH 1/5] clk: qcom: ipq4019: Modified the fixed clock rate to proper values

[Banavathi, Pradeep]

The PLLs on IPQ4019 cannot be reconfigured by design. The recommendation 
is to program these PLLS only once. Since, the  Bootloaders configure 
the PLLs and clocks already. we did not support the recalc rate and 
marked them as fixed clocks.


On 6/2/2016 3:48 AM, Stephen Boyd wrote:
> This was a temporary solution until the PLL recalc code could be
> written. When is the real clk driver coming so we can get rid of
> these fixed rate clks being registered in this driver?

Re: [PATCH 1/5] clk: qcom: ipq4019: Modified the fixed clock rate to proper values

[Stephen Boyd]

On 06/02, Banavathi, Pradeep wrote:
> The PLLs on IPQ4019 cannot be reconfigured by design. The
> recommendation is to program these PLLS only once. Since, the
> Bootloaders configure the PLLs and clocks already. we did not
> support the recalc rate and marked them as fixed clocks.
> 

(Please don't top post)

That doesn't matter. We recalculate PLL rates on all other qcom
SoCs by reading the hardware even though an overwhelming majority
of them are fixed by the bootloader.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH 1/5] clk: qcom: ipq4019: Modified the fixed clock rate to proper values

[Abhishek Sahu]

On Thu, Jun 02, 2016 at 11:35:40AM -0700, Stephen Boyd wrote:
> On 06/02, Banavathi, Pradeep wrote:
> > The PLLs on IPQ4019 cannot be reconfigured by design. The
> > recommendation is to program these PLLS only once. Since, the
> > Bootloaders configure the PLLs and clocks already. we did not
> > support the recalc rate and marked them as fixed clocks.
> > 
> 
> (Please don't top post)
> 
> That doesn't matter. We recalculate PLL rates on all other qcom
> SoCs by reading the hardware even though an overwhelming majority
> of them are fixed by the bootloader.
>
We will check for this. Already we added the APSS CPU PLL divider
in clock framework in next 3 patches of this patchset. Could you
please review the same so that we can follow the similar thing for
other PLL and dividers.
> -- 
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
> a Linux Foundation Collaborative Project