From: Kedareswara rao Appana <appana.durga.rao@xilinx.com>
To: <robh+dt@kernel.org>, <pawel.moll@arm.com>,
<mark.rutland@arm.com>, <ijc+devicetree@hellion.org.uk>,
<galak@codeaurora.org>, <michal.simek@xilinx.com>,
<soren.brinkmann@xilinx.com>, <vinod.koul@intel.com>,
<dan.j.williams@intel.com>, <appanad@xilinx.com>,
<moritz.fischer@ettus.com>, <laurent.pinchart@ideasonboard.com>,
<luis@debethencourt.com>, <svemula@xilinx.com>,
<anirudh@xilinx.com>, <punnaia@xilinx.com>
Cc: <devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <dmaengine@vger.kernel.org>
Subject: [PATCH v10 1/2] Documentation: DT: dma: Add Xilinx zynqmp dma device tree binding documentation
Date: Wed, 1 Jun 2016 12:53:58 +0530 [thread overview]
Message-ID: <1464765839-29018-1-git-send-email-appanad@xilinx.com> (raw)
Device-tree binding documentation for Xilinx zynqmp dma engine
used in Zynq UltraScale+ MPSoC.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
---
Changes in v10:
- Added Rob Acked-by in the commit message.
Changs in v9:
- Removed include sg runtime configuration parameter
from the binding doc as suggested by Lars.
Changes in v8:
- Removed all the software runtime configuration parameters
from the binding doc as suggested by the Lars.
Changes in v7:
- None.
Changes in v6:
- Removed desc-axi-cache/dst-axi-cache/src-axi-cache properties
from the binding doc as it allow broken combinations when dma-coherent
is set as suggested by Rob.
- Fixed minor comments given by Rob related coding(lower case DT node name).
Changes in v5:
- Use dma-coherent flag for coherent transfers as suggested by rob.
- Removed unnecessary properties from binding doc as suggested by Rob.
Changes in v4:
- None
Changes in v3:
- None
Changes in v2:
- None.
.../devicetree/bindings/dma/xilinx/zynqmp_dma.txt | 27 ++++++++++++++++++++++
1 file changed, 27 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
diff --git a/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
new file mode 100644
index 0000000..a784cdd
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
@@ -0,0 +1,27 @@
+Xilinx ZynqMP DMA engine, it does support memory to memory transfers,
+memory to device and device to memory transfers. It also has flow
+control and rate control support for slave/peripheral dma access.
+
+Required properties:
+- compatible : Should be "xlnx,zynqmp-dma-1.0"
+- reg : Memory map for gdma/adma module access.
+- interrupt-parent : Interrupt controller the interrupt is routed through
+- interrupts : Should contain DMA channel interrupt.
+- xlnx,bus-width : Axi buswidth in bits. Should contain 128 or 64
+- clock-names : List of input clocks "clk_main", "clk_apb"
+ (see clock bindings for details)
+
+Optional properties:
+- dma-coherent : Present if dma operations are coherent.
+
+Example:
+++++++++
+fpd_dma_chan1: dma@fd500000 {
+ compatible = "xlnx,zynqmp-dma-1.0";
+ reg = <0x0 0xFD500000 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 117 4>;
+ clock-names = "clk_main", "clk_apb";
+ xlnx,bus-width = <128>;
+ dma-coherent;
+};
--
2.1.2
next reply other threads:[~2016-06-01 7:24 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-01 7:23 Kedareswara rao Appana [this message]
2016-06-01 7:23 ` [PATCH v10 2/2] dmaengine: Add Xilinx zynqmp dma engine driver support Kedareswara rao Appana
2016-06-07 7:08 ` Vinod Koul
2016-06-08 7:40 ` Appana Durga Kedareswara Rao
2016-06-13 5:50 ` Vinod Koul
2016-06-14 8:18 ` Appana Durga Kedareswara Rao
2016-06-15 16:50 ` Vinod Koul
2016-06-16 7:19 ` Appana Durga Kedareswara Rao
2016-06-21 15:41 ` Vinod Koul
2016-06-21 16:19 ` Punnaiah Choudary Kalluri
2016-06-21 16:38 ` Vinod Koul
2016-06-21 17:29 ` Punnaiah Choudary Kalluri
2016-06-28 4:14 ` Vinod Koul
2016-06-29 3:59 ` Punnaiah Choudary Kalluri
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