From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1160998AbcFEW3X (ORCPT ); Sun, 5 Jun 2016 18:29:23 -0400 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:57478 "EHLO mx0b-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932414AbcFEW3Q (ORCPT ); Sun, 5 Jun 2016 18:29:16 -0400 X-IBM-Helo: d23dlp03.au.ibm.com X-IBM-MailFrom: benh@au1.ibm.com X-IBM-RcptTo: linux-kernel@vger.kernel.org Subject: Re: [PATCH v5 08/11] powerpc/powernv: Add platform support for stop instruction From: Benjamin Herrenschmidt Reply-To: benh@au1.ibm.com To: "Shreyas B. Prabhu" , mpe@ellerman.id.au Cc: ego@linux.vnet.ibm.com, mikey@neuling.org, maddy@linux.vnet.ibm.com, linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org Date: Mon, 06 Jun 2016 08:28:38 +1000 In-Reply-To: <1464871141-11568-9-git-send-email-shreyas@linux.vnet.ibm.com> References: <1464871141-11568-1-git-send-email-shreyas@linux.vnet.ibm.com> <1464871141-11568-9-git-send-email-shreyas@linux.vnet.ibm.com> Organization: IBM Australia Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.18.5.2 (3.18.5.2-1.fc23) Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 16060522-0008-0000-0000-000000950AAB X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 16060522-0009-0000-0000-00000765C686 Message-Id: <1465165718.4274.20.camel@au1.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2016-06-05_09:,, signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1604210000 definitions=main-1606050276 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 2016-06-02 at 07:38 -0500, Shreyas B. Prabhu wrote: > @@ -61,8 +72,13 @@ save_sprs_to_stack: >          * Note all register i.e per-core, per-subcore or per-thread is saved >          * here since any thread in the core might wake up first >          */ > +BEGIN_FTR_SECTION > +       mfspr   r3,SPRN_PTCR > +       std     r3,_PTCR(r1) > +FTR_SECTION_ELSE >         mfspr   r3,SPRN_SDR1 >         std     r3,_SDR1(r1) > +ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300) This is the only new SPR we care about in P9 ? Cheers, Ben.