* [PATCH v4 0/5] MT2701 iommu support
@ 2016-06-08 9:50 honghui.zhang
2016-06-08 9:50 ` [PATCH v4 1/5] dt-bindings: mediatek: add descriptions for mediatek mt2701 iommu and smi honghui.zhang
` (4 more replies)
0 siblings, 5 replies; 20+ messages in thread
From: honghui.zhang @ 2016-06-08 9:50 UTC (permalink / raw)
To: joro, treding, mark.rutland, matthias.bgg, robh, robin.murphy
Cc: p.zabel, devicetree, pebolle, kendrick.hsu, arnd, srv_heupstream,
catalin.marinas, will.deacon, linux-kernel, tfiga, iommu,
robh+dt, djkurtz, kernel, linux-mediatek, linux-arm-kernel,
l.stach, yingjoe.chen, eddie.huang, youlin.pei, erin.lo,
Honghui Zhang
From: Honghui Zhang <honghui.zhang@mediatek.com>
Mediatek's m4u(Multimedia Memory Management Unit) and SMI(Smart
Multimedia Interface)have two generations HW. They basically sharing the
same hardware block diagram, but have some difference as below:
Generation one m4u only supports one layer, flat pagetable addressing,
and only supports 4K size page mapping. While generation two m4u supports 2
levels of pagetable which uses the ARM short-descriptor translation table
format for address translation.
They have slight different register base and register offset.
They have very different HW ports defines.
Generaion one SMI has additional "async" clock which transform the smi
clock into emi clock domain, this clock should be prepared and enabled for
SMI generation one HW.
The register which control the iommu need to translation the address or not
for a particular port is located at smi ao base(smi always on register
base) for generation one SMI HW, but located at each larb's register base
for generation two HW.
This patch set add mt2701 iommu support, it's based on 4.7-rc1 and James
Liao's "Add clock support for Mediatek MT2701 v8[1]" and "Mediatek MT2701
SCPSYS power domain support v7[2]" patch.
v4:
-Rebase on 4.7-rc1.
-Do not call of_node_put call in mtk_iommu_create_mapping.
v3: https://lists.linuxfoundation.org/pipermail/iommu/2016-May/017179.html
-Rebase on "of: Implement iterator for phandles[3]" and take use of
of_for_each_phandle.
-Forward-declare mtk_iommu_domain and implement the struct separately.
-Free the pagetable memory in mtk_iommu_domain_free
-Roll back the mapping in error case.
-Minor cleanups.
v2: https://lists.linuxfoundation.org/pipermail/iommu/2016-May/017068.html
-Fix syntax errors in dt-bindings.
-Use dma_alloc/free_coherent to allocate pagetable memory and reduce the
streaming DMA stuff.
-Make the mtk_iommu_ops.pgsize_bitmap as ~0UL << MT2701_IOMMU_PAGE_SHIFT.
-Use macro instead of variable to indicate the pagetable size.
-Change some macro name from MTK_XXX to MT2701_XXX.
v1: http://lists.infradead.org/pipermail/linux-mediatek/2016-May/005301.html
-initial version
[1] http://lists.infradead.org/pipermail/linux-mediatek/2016-May/005439.html
[2] http://lists.infradead.org/pipermail/linux-mediatek/2016-May/005429.html
[3] https://lists.linuxfoundation.org/pipermail/iommu/2016-April/016300.html
Honghui Zhang (5):
dt-bindings: mediatek: add descriptions for mediatek mt2701 iommu and
smi
iommu/mediatek: move the common struct into header file
memory/mediatek: add support for mt2701
iommu/mediatek: add support for mtk iommu generation one HW
ARM: dts: mt2701: add iommu/smi dtsi node for mt2701
.../devicetree/bindings/iommu/mediatek,iommu.txt | 13 +-
.../memory-controllers/mediatek,smi-common.txt | 21 +-
.../memory-controllers/mediatek,smi-larb.txt | 4 +-
arch/arm/boot/dts/mt2701.dtsi | 51 ++
drivers/iommu/Kconfig | 18 +
drivers/iommu/Makefile | 1 +
drivers/iommu/mtk_iommu.c | 48 +-
drivers/iommu/mtk_iommu.h | 77 +++
drivers/iommu/mtk_iommu_v1.c | 727 +++++++++++++++++++++
drivers/memory/mtk-smi.c | 167 ++++-
include/dt-bindings/memory/mt2701-larb-port.h | 85 +++
11 files changed, 1139 insertions(+), 73 deletions(-)
create mode 100644 drivers/iommu/mtk_iommu.h
create mode 100644 drivers/iommu/mtk_iommu_v1.c
create mode 100644 include/dt-bindings/memory/mt2701-larb-port.h
--
1.8.1.1.dirty
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v4 1/5] dt-bindings: mediatek: add descriptions for mediatek mt2701 iommu and smi
2016-06-08 9:50 [PATCH v4 0/5] MT2701 iommu support honghui.zhang
@ 2016-06-08 9:50 ` honghui.zhang
2016-06-08 9:50 ` [PATCH v4 2/5] iommu/mediatek: move the common struct into header file honghui.zhang
` (3 subsequent siblings)
4 siblings, 0 replies; 20+ messages in thread
From: honghui.zhang @ 2016-06-08 9:50 UTC (permalink / raw)
To: joro, treding, mark.rutland, matthias.bgg, robh, robin.murphy
Cc: p.zabel, devicetree, pebolle, kendrick.hsu, arnd, srv_heupstream,
catalin.marinas, will.deacon, linux-kernel, tfiga, iommu,
robh+dt, djkurtz, kernel, linux-mediatek, linux-arm-kernel,
l.stach, yingjoe.chen, eddie.huang, youlin.pei, erin.lo,
Honghui Zhang
From: Honghui Zhang <honghui.zhang@mediatek.com>
This patch defines the local arbitor port IDs for mediatek SoC MT2701 and
add descriptions of binding for mediatek generation one iommu and smi.
Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
Acked-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/iommu/mediatek,iommu.txt | 13 +++-
.../memory-controllers/mediatek,smi-common.txt | 21 +++++-
.../memory-controllers/mediatek,smi-larb.txt | 4 +-
include/dt-bindings/memory/mt2701-larb-port.h | 85 ++++++++++++++++++++++
4 files changed, 115 insertions(+), 8 deletions(-)
create mode 100644 include/dt-bindings/memory/mt2701-larb-port.h
diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
index cd1b1cd..53c20ca 100644
--- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
+++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
@@ -1,7 +1,9 @@
* Mediatek IOMMU Architecture Implementation
- Some Mediatek SOCs contain a Multimedia Memory Management Unit (M4U) which
-uses the ARM Short-Descriptor translation table format for address translation.
+ Some Mediatek SOCs contain a Multimedia Memory Management Unit (M4U), and
+this M4U have two generations of HW architecture. Generation one uses flat
+pagetable, and only supports 4K size page mapping. Generation two uses the
+ARM Short-Descriptor translation table format for address translation.
About the M4U Hardware Block Diagram, please check below:
@@ -36,7 +38,9 @@ in each larb. Take a example, There are many ports like MC, PP, VLD in the
video decode local arbiter, all these ports are according to the video HW.
Required properties:
-- compatible : must be "mediatek,mt8173-m4u".
+- compatible : must be one of the following string:
+ "mediatek,mt2701-m4u" for mt2701 which uses generation one m4u HW.
+ "mediatek,mt8173-m4u" for mt8173 which uses generation two m4u HW.
- reg : m4u register base and size.
- interrupts : the interrupt of m4u.
- clocks : must contain one entry for each clock-names.
@@ -46,7 +50,8 @@ Required properties:
according to the local arbiter index, like larb0, larb1, larb2...
- iommu-cells : must be 1. This is the mtk_m4u_id according to the HW.
Specifies the mtk_m4u_id as defined in
- dt-binding/memory/mt8173-larb-port.h.
+ dt-binding/memory/mt2701-larb-port.h for mt2701 and
+ dt-binding/memory/mt8173-larb-port.h for mt8173
Example:
iommu: iommu@10205000 {
diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
index 06a83ce..aa614b2 100644
--- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
+++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
@@ -2,16 +2,31 @@ SMI (Smart Multimedia Interface) Common
The hardware block diagram please check bindings/iommu/mediatek,iommu.txt
+Mediatek SMI have two generations of HW architecture, mt8173 uses the second
+generation of SMI HW while mt2701 uses the first generation HW of SMI.
+
+There's slight differences between the two SMI, for generation 2, the
+register which control the iommu port is at each larb's register base. But
+for generation 1, the register is at smi ao base(smi always on register
+base). Besides that, the smi async clock should be prepared and enabled for
+SMI generation 1 to transform the smi clock into emi clock domain, but that is
+not needed for SMI generation 2.
+
Required properties:
-- compatible : must be "mediatek,mt8173-smi-common"
+- compatible : must be one of :
+ "mediatek,mt2701-smi-common"
+ "mediatek,mt8173-smi-common"
- reg : the register and size of the SMI block.
- power-domains : a phandle to the power domain of this local arbiter.
- clocks : Must contain an entry for each entry in clock-names.
-- clock-names : must contain 2 entries, as follows:
+- clock-names : must contain 3 entries for generation 1 smi HW and 2 entries
+ for generation 2 smi HW as follows:
- "apb" : Advanced Peripheral Bus clock, It's the clock for setting
the register.
- "smi" : It's the clock for transfer data and command.
- They may be the same if both source clocks are the same.
+ They may be the same if both source clocks are the same.
+ - "async" : asynchronous clock, it help transform the smi clock into the emi
+ clock domain, this clock is only needed by generation 1 smi HW.
Example:
smi_common: smi@14022000 {
diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
index 55ff3b7..21277a5 100644
--- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
+++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
@@ -3,7 +3,9 @@ SMI (Smart Multimedia Interface) Local Arbiter
The hardware block diagram please check bindings/iommu/mediatek,iommu.txt
Required properties:
-- compatible : must be "mediatek,mt8173-smi-larb"
+- compatible : must be one of :
+ "mediatek,mt8173-smi-larb"
+ "mediatek,mt2701-smi-larb"
- reg : the register and size of this local arbiter.
- mediatek,smi : a phandle to the smi_common node.
- power-domains : a phandle to the power domain of this local arbiter.
diff --git a/include/dt-bindings/memory/mt2701-larb-port.h b/include/dt-bindings/memory/mt2701-larb-port.h
new file mode 100644
index 0000000..78f6678
--- /dev/null
+++ b/include/dt-bindings/memory/mt2701-larb-port.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2015 MediaTek Inc.
+ * Author: Honghui Zhang <honghui.zhang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _MT2701_LARB_PORT_H_
+#define _MT2701_LARB_PORT_H_
+
+/*
+ * Mediatek m4u generation 1 such as mt2701 has flat m4u port numbers,
+ * the first port's id for larb[N] would be the last port's id of larb[N - 1]
+ * plus one while larb[0]'s first port number is 0. The definition of
+ * MT2701_M4U_ID_LARBx is following HW register spec.
+ * But m4u generation 2 like mt8173 have different port number, it use fixed
+ * offset for each larb, the first port's id for larb[N] would be (N * 32).
+ */
+#define LARB0_PORT_OFFSET 0
+#define LARB1_PORT_OFFSET 11
+#define LARB2_PORT_OFFSET 21
+#define LARB3_PORT_OFFSET 43
+
+#define MT2701_M4U_ID_LARB0(port) ((port) + LARB0_PORT_OFFSET)
+#define MT2701_M4U_ID_LARB1(port) ((port) + LARB1_PORT_OFFSET)
+#define MT2701_M4U_ID_LARB2(port) ((port) + LARB2_PORT_OFFSET)
+
+/* Port define for larb0 */
+#define MT2701_M4U_PORT_DISP_OVL_0 MT2701_M4U_ID_LARB0(0)
+#define MT2701_M4U_PORT_DISP_RDMA1 MT2701_M4U_ID_LARB0(1)
+#define MT2701_M4U_PORT_DISP_RDMA MT2701_M4U_ID_LARB0(2)
+#define MT2701_M4U_PORT_DISP_WDMA MT2701_M4U_ID_LARB0(3)
+#define MT2701_M4U_PORT_MM_CMDQ MT2701_M4U_ID_LARB0(4)
+#define MT2701_M4U_PORT_MDP_RDMA MT2701_M4U_ID_LARB0(5)
+#define MT2701_M4U_PORT_MDP_WDMA MT2701_M4U_ID_LARB0(6)
+#define MT2701_M4U_PORT_MDP_ROTO MT2701_M4U_ID_LARB0(7)
+#define MT2701_M4U_PORT_MDP_ROTCO MT2701_M4U_ID_LARB0(8)
+#define MT2701_M4U_PORT_MDP_ROTVO MT2701_M4U_ID_LARB0(9)
+#define MT2701_M4U_PORT_MDP_RDMA1 MT2701_M4U_ID_LARB0(10)
+
+/* Port define for larb1 */
+#define MT2701_M4U_PORT_VDEC_MC_EXT MT2701_M4U_ID_LARB1(0)
+#define MT2701_M4U_PORT_VDEC_PP_EXT MT2701_M4U_ID_LARB1(1)
+#define MT2701_M4U_PORT_VDEC_PPWRAP_EXT MT2701_M4U_ID_LARB1(2)
+#define MT2701_M4U_PORT_VDEC_AVC_MV_EXT MT2701_M4U_ID_LARB1(3)
+#define MT2701_M4U_PORT_VDEC_PRED_RD_EXT MT2701_M4U_ID_LARB1(4)
+#define MT2701_M4U_PORT_VDEC_PRED_WR_EXT MT2701_M4U_ID_LARB1(5)
+#define MT2701_M4U_PORT_VDEC_VLD_EXT MT2701_M4U_ID_LARB1(6)
+#define MT2701_M4U_PORT_VDEC_VLD2_EXT MT2701_M4U_ID_LARB1(7)
+#define MT2701_M4U_PORT_VDEC_TILE_EXT MT2701_M4U_ID_LARB1(8)
+#define MT2701_M4U_PORT_VDEC_IMG_RESZ_EXT MT2701_M4U_ID_LARB1(9)
+
+/* Port define for larb2 */
+#define MT2701_M4U_PORT_VENC_RCPU MT2701_M4U_ID_LARB2(0)
+#define MT2701_M4U_PORT_VENC_REC_FRM MT2701_M4U_ID_LARB2(1)
+#define MT2701_M4U_PORT_VENC_BSDMA MT2701_M4U_ID_LARB2(2)
+#define MT2701_M4U_PORT_JPGENC_RDMA MT2701_M4U_ID_LARB2(3)
+#define MT2701_M4U_PORT_VENC_LT_RCPU MT2701_M4U_ID_LARB2(4)
+#define MT2701_M4U_PORT_VENC_LT_REC_FRM MT2701_M4U_ID_LARB2(5)
+#define MT2701_M4U_PORT_VENC_LT_BSDMA MT2701_M4U_ID_LARB2(6)
+#define MT2701_M4U_PORT_JPGDEC_BSDMA MT2701_M4U_ID_LARB2(7)
+#define MT2701_M4U_PORT_VENC_SV_COMV MT2701_M4U_ID_LARB2(8)
+#define MT2701_M4U_PORT_VENC_RD_COMV MT2701_M4U_ID_LARB2(9)
+#define MT2701_M4U_PORT_JPGENC_BSDMA MT2701_M4U_ID_LARB2(10)
+#define MT2701_M4U_PORT_VENC_CUR_LUMA MT2701_M4U_ID_LARB2(11)
+#define MT2701_M4U_PORT_VENC_CUR_CHROMA MT2701_M4U_ID_LARB2(12)
+#define MT2701_M4U_PORT_VENC_REF_LUMA MT2701_M4U_ID_LARB2(13)
+#define MT2701_M4U_PORT_VENC_REF_CHROMA MT2701_M4U_ID_LARB2(14)
+#define MT2701_M4U_PORT_IMG_RESZ MT2701_M4U_ID_LARB2(15)
+#define MT2701_M4U_PORT_VENC_LT_SV_COMV MT2701_M4U_ID_LARB2(16)
+#define MT2701_M4U_PORT_VENC_LT_RD_COMV MT2701_M4U_ID_LARB2(17)
+#define MT2701_M4U_PORT_VENC_LT_CUR_LUMA MT2701_M4U_ID_LARB2(18)
+#define MT2701_M4U_PORT_VENC_LT_CUR_CHROMA MT2701_M4U_ID_LARB2(19)
+#define MT2701_M4U_PORT_VENC_LT_REF_LUMA MT2701_M4U_ID_LARB2(20)
+#define MT2701_M4U_PORT_VENC_LT_REF_CHROMA MT2701_M4U_ID_LARB2(21)
+#define MT2701_M4U_PORT_JPGDEC_WDMA MT2701_M4U_ID_LARB2(22)
+
+#endif
--
1.8.1.1.dirty
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v4 2/5] iommu/mediatek: move the common struct into header file
2016-06-08 9:50 [PATCH v4 0/5] MT2701 iommu support honghui.zhang
2016-06-08 9:50 ` [PATCH v4 1/5] dt-bindings: mediatek: add descriptions for mediatek mt2701 iommu and smi honghui.zhang
@ 2016-06-08 9:50 ` honghui.zhang
2016-06-08 9:50 ` [PATCH v4 3/5] memory/mediatek: add support for mt2701 honghui.zhang
` (2 subsequent siblings)
4 siblings, 0 replies; 20+ messages in thread
From: honghui.zhang @ 2016-06-08 9:50 UTC (permalink / raw)
To: joro, treding, mark.rutland, matthias.bgg, robh, robin.murphy
Cc: p.zabel, devicetree, pebolle, kendrick.hsu, arnd, srv_heupstream,
catalin.marinas, will.deacon, linux-kernel, tfiga, iommu,
robh+dt, djkurtz, kernel, linux-mediatek, linux-arm-kernel,
l.stach, yingjoe.chen, eddie.huang, youlin.pei, erin.lo,
Honghui Zhang
From: Honghui Zhang <honghui.zhang@mediatek.com>
Move the struct defines of mtk iommu into a new header files for
common use.
Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 48 +----------------------------
drivers/iommu/mtk_iommu.h | 77 +++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 78 insertions(+), 47 deletions(-)
create mode 100644 drivers/iommu/mtk_iommu.h
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index c3043d8..4f18ff5 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -34,7 +34,7 @@
#include <dt-bindings/memory/mt8173-larb-port.h>
#include <soc/mediatek/smi.h>
-#include "io-pgtable.h"
+#include "mtk_iommu.h"
#define REG_MMU_PT_BASE_ADDR 0x000
@@ -93,20 +93,6 @@
#define MTK_PROTECT_PA_ALIGN 128
-struct mtk_iommu_suspend_reg {
- u32 standard_axi_mode;
- u32 dcm_dis;
- u32 ctrl_reg;
- u32 int_control0;
- u32 int_main_control;
-};
-
-struct mtk_iommu_client_priv {
- struct list_head client;
- unsigned int mtk_m4u_id;
- struct device *m4udev;
-};
-
struct mtk_iommu_domain {
spinlock_t pgtlock; /* lock for page table */
@@ -116,19 +102,6 @@ struct mtk_iommu_domain {
struct iommu_domain domain;
};
-struct mtk_iommu_data {
- void __iomem *base;
- int irq;
- struct device *dev;
- struct clk *bclk;
- phys_addr_t protect_base; /* protect memory base */
- struct mtk_iommu_suspend_reg reg;
- struct mtk_iommu_domain *m4u_dom;
- struct iommu_group *m4u_group;
- struct mtk_smi_iommu smi_imu; /* SMI larb iommu info */
- bool enable_4GB;
-};
-
static struct iommu_ops mtk_iommu_ops;
static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom)
@@ -552,25 +525,6 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
return 0;
}
-static int compare_of(struct device *dev, void *data)
-{
- return dev->of_node == data;
-}
-
-static int mtk_iommu_bind(struct device *dev)
-{
- struct mtk_iommu_data *data = dev_get_drvdata(dev);
-
- return component_bind_all(dev, &data->smi_imu);
-}
-
-static void mtk_iommu_unbind(struct device *dev)
-{
- struct mtk_iommu_data *data = dev_get_drvdata(dev);
-
- component_unbind_all(dev, &data->smi_imu);
-}
-
static const struct component_master_ops mtk_iommu_com_ops = {
.bind = mtk_iommu_bind,
.unbind = mtk_iommu_unbind,
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
new file mode 100644
index 0000000..9ed0a84
--- /dev/null
+++ b/drivers/iommu/mtk_iommu.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2015-2016 MediaTek Inc.
+ * Author: Honghui Zhang <honghui.zhang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _MTK_IOMMU_H_
+#define _MTK_IOMMU_H_
+
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/iommu.h>
+#include <linux/list.h>
+#include <linux/spinlock.h>
+#include <soc/mediatek/smi.h>
+
+#include "io-pgtable.h"
+
+struct mtk_iommu_suspend_reg {
+ u32 standard_axi_mode;
+ u32 dcm_dis;
+ u32 ctrl_reg;
+ u32 int_control0;
+ u32 int_main_control;
+};
+
+struct mtk_iommu_client_priv {
+ struct list_head client;
+ unsigned int mtk_m4u_id;
+ struct device *m4udev;
+};
+
+struct mtk_iommu_domain;
+
+struct mtk_iommu_data {
+ void __iomem *base;
+ int irq;
+ struct device *dev;
+ struct clk *bclk;
+ phys_addr_t protect_base; /* protect memory base */
+ struct mtk_iommu_suspend_reg reg;
+ struct mtk_iommu_domain *m4u_dom;
+ struct iommu_group *m4u_group;
+ struct mtk_smi_iommu smi_imu; /* SMI larb iommu info */
+ bool enable_4GB;
+};
+
+static int compare_of(struct device *dev, void *data)
+{
+ return dev->of_node == data;
+}
+
+static int mtk_iommu_bind(struct device *dev)
+{
+ struct mtk_iommu_data *data = dev_get_drvdata(dev);
+
+ return component_bind_all(dev, &data->smi_imu);
+}
+
+static void mtk_iommu_unbind(struct device *dev)
+{
+ struct mtk_iommu_data *data = dev_get_drvdata(dev);
+
+ component_unbind_all(dev, &data->smi_imu);
+}
+
+#endif
--
1.8.1.1.dirty
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v4 3/5] memory/mediatek: add support for mt2701
2016-06-08 9:50 [PATCH v4 0/5] MT2701 iommu support honghui.zhang
2016-06-08 9:50 ` [PATCH v4 1/5] dt-bindings: mediatek: add descriptions for mediatek mt2701 iommu and smi honghui.zhang
2016-06-08 9:50 ` [PATCH v4 2/5] iommu/mediatek: move the common struct into header file honghui.zhang
@ 2016-06-08 9:50 ` honghui.zhang
2016-06-08 9:51 ` [PATCH v4 4/5] iommu/mediatek: add support for mtk iommu generation one HW honghui.zhang
2016-06-08 9:51 ` [PATCH v4 5/5] ARM: dts: mt2701: add iommu/smi dtsi node for mt2701 honghui.zhang
4 siblings, 0 replies; 20+ messages in thread
From: honghui.zhang @ 2016-06-08 9:50 UTC (permalink / raw)
To: joro, treding, mark.rutland, matthias.bgg, robh, robin.murphy
Cc: p.zabel, devicetree, pebolle, kendrick.hsu, arnd, srv_heupstream,
catalin.marinas, will.deacon, linux-kernel, tfiga, iommu,
robh+dt, djkurtz, kernel, linux-mediatek, linux-arm-kernel,
l.stach, yingjoe.chen, eddie.huang, youlin.pei, erin.lo,
Honghui Zhang
From: Honghui Zhang <honghui.zhang@mediatek.com>
Mediatek SMI has two generations of HW architecture, mt8173 uses the
second generation of SMI HW while mt2701 uses the first generation
HW of SMI.
There's slight differences between the two generations, for generation 2,
the register which control the iommu port access PA or IOVA is at each
larb's register base. But for generation 1, the register is at smi ao
base(smi always on register base).
Besides that, the smi async clock should be prepared and enabled for SMI
generation 1 HW to transform the smi clock into emi clock domain, but is
not needed for SMI generation 2.
This patch add SMI driver for mt2701 which use generation 1 SMI HW.
Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
---
drivers/memory/mtk-smi.c | 167 ++++++++++++++++++++++++++++++++++++++++++-----
1 file changed, 149 insertions(+), 18 deletions(-)
diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
index f6b5757..4afbc41 100644
--- a/drivers/memory/mtk-smi.c
+++ b/drivers/memory/mtk-smi.c
@@ -21,19 +21,50 @@
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <soc/mediatek/smi.h>
+#include <dt-bindings/memory/mt2701-larb-port.h>
#define SMI_LARB_MMU_EN 0xf00
+#define REG_SMI_SECUR_CON_BASE 0x5c0
+
+/* every register control 8 port, register offset 0x4 */
+#define REG_SMI_SECUR_CON_OFFSET(id) (((id) >> 3) << 2)
+#define REG_SMI_SECUR_CON_ADDR(id) \
+ (REG_SMI_SECUR_CON_BASE + REG_SMI_SECUR_CON_OFFSET(id))
+
+/*
+ * every port have 4 bit to control, bit[port + 3] control virtual or physical,
+ * bit[port + 2 : port + 1] control the domain, bit[port] control the security
+ * or non-security.
+ */
+#define SMI_SECUR_CON_VAL_MSK(id) (~(0xf << (((id) & 0x7) << 2)))
+#define SMI_SECUR_CON_VAL_VIRT(id) BIT((((id) & 0x7) << 2) + 3)
+/* mt2701 domain should be set to 3 */
+#define SMI_SECUR_CON_VAL_DOMAIN(id) (0x3 << ((((id) & 0x7) << 2) + 1))
+
+struct mtk_smi_larb_gen {
+ int port_in_larb[MTK_LARB_NR_MAX + 1];
+ void (*config_port)(struct device *);
+};
struct mtk_smi {
- struct device *dev;
- struct clk *clk_apb, *clk_smi;
+ struct device *dev;
+ struct clk *clk_apb, *clk_smi;
+ struct clk *clk_async; /*only needed by mt2701*/
+ void __iomem *smi_ao_base;
};
struct mtk_smi_larb { /* larb: local arbiter */
- struct mtk_smi smi;
- void __iomem *base;
- struct device *smi_common_dev;
- u32 *mmu;
+ struct mtk_smi smi;
+ void __iomem *base;
+ struct device *smi_common_dev;
+ const struct mtk_smi_larb_gen *larb_gen;
+ int larbid;
+ u32 *mmu;
+};
+
+enum mtk_smi_gen {
+ MTK_SMI_GEN1,
+ MTK_SMI_GEN2
};
static int mtk_smi_enable(const struct mtk_smi *smi)
@@ -71,6 +102,7 @@ static void mtk_smi_disable(const struct mtk_smi *smi)
int mtk_smi_larb_get(struct device *larbdev)
{
struct mtk_smi_larb *larb = dev_get_drvdata(larbdev);
+ const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen;
struct mtk_smi *common = dev_get_drvdata(larb->smi_common_dev);
int ret;
@@ -87,7 +119,7 @@ int mtk_smi_larb_get(struct device *larbdev)
}
/* Configure the iommu info for this larb */
- writel(*larb->mmu, larb->base + SMI_LARB_MMU_EN);
+ larb_gen->config_port(larbdev);
return 0;
}
@@ -126,6 +158,45 @@ mtk_smi_larb_bind(struct device *dev, struct device *master, void *data)
return -ENODEV;
}
+static void mtk_smi_larb_config_port(struct device *dev)
+{
+ struct mtk_smi_larb *larb = dev_get_drvdata(dev);
+
+ writel(*larb->mmu, larb->base + SMI_LARB_MMU_EN);
+}
+
+
+static void mtk_smi_larb_config_port_gen1(struct device *dev)
+{
+ struct mtk_smi_larb *larb = dev_get_drvdata(dev);
+ const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen;
+ struct mtk_smi *common = dev_get_drvdata(larb->smi_common_dev);
+ int i, m4u_port_id, larb_port_num;
+ u32 sec_con_val, reg_val;
+
+ m4u_port_id = larb_gen->port_in_larb[larb->larbid];
+ larb_port_num = larb_gen->port_in_larb[larb->larbid + 1]
+ - larb_gen->port_in_larb[larb->larbid];
+
+ for (i = 0; i < larb_port_num; i++, m4u_port_id++) {
+ if (*larb->mmu & BIT(i)) {
+ /* bit[port + 3] controls the virtual or physical */
+ sec_con_val = SMI_SECUR_CON_VAL_VIRT(m4u_port_id);
+ } else {
+ /* do not need to enable m4u for this port */
+ continue;
+ }
+ reg_val = readl(common->smi_ao_base
+ + REG_SMI_SECUR_CON_ADDR(m4u_port_id));
+ reg_val &= SMI_SECUR_CON_VAL_MSK(m4u_port_id);
+ reg_val |= sec_con_val;
+ reg_val |= SMI_SECUR_CON_VAL_DOMAIN(m4u_port_id);
+ writel(reg_val,
+ common->smi_ao_base
+ + REG_SMI_SECUR_CON_ADDR(m4u_port_id));
+ }
+}
+
static void
mtk_smi_larb_unbind(struct device *dev, struct device *master, void *data)
{
@@ -137,6 +208,31 @@ static const struct component_ops mtk_smi_larb_component_ops = {
.unbind = mtk_smi_larb_unbind,
};
+static const struct mtk_smi_larb_gen mtk_smi_larb_mt8173 = {
+ /* mt8173 do not need the port in larb */
+ .config_port = mtk_smi_larb_config_port,
+};
+
+static const struct mtk_smi_larb_gen mtk_smi_larb_mt2701 = {
+ .port_in_larb = {
+ LARB0_PORT_OFFSET, LARB1_PORT_OFFSET,
+ LARB2_PORT_OFFSET, LARB3_PORT_OFFSET
+ },
+ .config_port = mtk_smi_larb_config_port_gen1,
+};
+
+static const struct of_device_id mtk_smi_larb_of_ids[] = {
+ {
+ .compatible = "mediatek,mt8173-smi-larb",
+ .data = &mtk_smi_larb_mt8173
+ },
+ {
+ .compatible = "mediatek,mt2701-smi-larb",
+ .data = &mtk_smi_larb_mt2701
+ },
+ {}
+};
+
static int mtk_smi_larb_probe(struct platform_device *pdev)
{
struct mtk_smi_larb *larb;
@@ -144,14 +240,20 @@ static int mtk_smi_larb_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct device_node *smi_node;
struct platform_device *smi_pdev;
+ const struct of_device_id *of_id;
if (!dev->pm_domain)
return -EPROBE_DEFER;
+ of_id = of_match_node(mtk_smi_larb_of_ids, pdev->dev.of_node);
+ if (!of_id)
+ return -EINVAL;
+
larb = devm_kzalloc(dev, sizeof(*larb), GFP_KERNEL);
if (!larb)
return -ENOMEM;
+ larb->larb_gen = of_id->data;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
larb->base = devm_ioremap_resource(dev, res);
if (IS_ERR(larb->base))
@@ -191,24 +293,34 @@ static int mtk_smi_larb_remove(struct platform_device *pdev)
return 0;
}
-static const struct of_device_id mtk_smi_larb_of_ids[] = {
- { .compatible = "mediatek,mt8173-smi-larb",},
- {}
-};
-
static struct platform_driver mtk_smi_larb_driver = {
.probe = mtk_smi_larb_probe,
- .remove = mtk_smi_larb_remove,
+ .remove = mtk_smi_larb_remove,
.driver = {
.name = "mtk-smi-larb",
.of_match_table = mtk_smi_larb_of_ids,
}
};
+static const struct of_device_id mtk_smi_common_of_ids[] = {
+ {
+ .compatible = "mediatek,mt8173-smi-common",
+ .data = (void *)MTK_SMI_GEN2
+ },
+ {
+ .compatible = "mediatek,mt2701-smi-common",
+ .data = (void *)MTK_SMI_GEN1
+ },
+ {}
+};
+
static int mtk_smi_common_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct mtk_smi *common;
+ struct resource *res;
+ const struct of_device_id *of_id;
+ enum mtk_smi_gen smi_gen;
if (!dev->pm_domain)
return -EPROBE_DEFER;
@@ -226,6 +338,29 @@ static int mtk_smi_common_probe(struct platform_device *pdev)
if (IS_ERR(common->clk_smi))
return PTR_ERR(common->clk_smi);
+ of_id = of_match_node(mtk_smi_common_of_ids, pdev->dev.of_node);
+ if (!of_id)
+ return -EINVAL;
+
+ /*
+ * for mtk smi gen 1, we need to get the ao(always on) base to config
+ * m4u port, and we need to enable the aync clock for transform the smi
+ * clock into emi clock domain, but for mtk smi gen2, there's no smi ao
+ * base.
+ */
+ smi_gen = (enum mtk_smi_gen)of_id->data;
+ if (smi_gen == MTK_SMI_GEN1) {
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ common->smi_ao_base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(common->smi_ao_base))
+ return PTR_ERR(common->smi_ao_base);
+
+ common->clk_async = devm_clk_get(dev, "async");
+ if (IS_ERR(common->clk_async))
+ return PTR_ERR(common->clk_async);
+
+ clk_prepare_enable(common->clk_async);
+ }
pm_runtime_enable(dev);
platform_set_drvdata(pdev, common);
return 0;
@@ -237,11 +372,6 @@ static int mtk_smi_common_remove(struct platform_device *pdev)
return 0;
}
-static const struct of_device_id mtk_smi_common_of_ids[] = {
- { .compatible = "mediatek,mt8173-smi-common", },
- {}
-};
-
static struct platform_driver mtk_smi_common_driver = {
.probe = mtk_smi_common_probe,
.remove = mtk_smi_common_remove,
@@ -272,4 +402,5 @@ err_unreg_smi:
platform_driver_unregister(&mtk_smi_common_driver);
return ret;
}
+
subsys_initcall(mtk_smi_init);
--
1.8.1.1.dirty
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v4 4/5] iommu/mediatek: add support for mtk iommu generation one HW
2016-06-08 9:50 [PATCH v4 0/5] MT2701 iommu support honghui.zhang
` (2 preceding siblings ...)
2016-06-08 9:50 ` [PATCH v4 3/5] memory/mediatek: add support for mt2701 honghui.zhang
@ 2016-06-08 9:51 ` honghui.zhang
2016-06-08 9:51 ` [PATCH v4 5/5] ARM: dts: mt2701: add iommu/smi dtsi node for mt2701 honghui.zhang
4 siblings, 0 replies; 20+ messages in thread
From: honghui.zhang @ 2016-06-08 9:51 UTC (permalink / raw)
To: joro, treding, mark.rutland, matthias.bgg, robh, robin.murphy
Cc: p.zabel, devicetree, pebolle, kendrick.hsu, arnd, srv_heupstream,
catalin.marinas, will.deacon, linux-kernel, tfiga, iommu,
robh+dt, djkurtz, kernel, linux-mediatek, linux-arm-kernel,
l.stach, yingjoe.chen, eddie.huang, youlin.pei, erin.lo,
Honghui Zhang
From: Honghui Zhang <honghui.zhang@mediatek.com>
Mediatek SoC's M4U has two generations of HW architcture. Generation one
uses flat, one layer pagetable, and was shipped with ARM architecture, it
only supports 4K size page mapping. MT2701 SoC uses this generation one
m4u HW. Generation two uses the ARM short-descriptor translation table
format for address translation, and was shipped with ARM64 architecture,
MT8173 uses this generation two m4u HW. All the two generation iommu HW
only have one iommu domain, and all its iommu clients share the same
iova address.
These two generation m4u HW have slit different register groups and
register offset, but most register names are the same. This patch add iommu
support for mediatek SoC mt2701.
Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
---
drivers/iommu/Kconfig | 18 ++
drivers/iommu/Makefile | 1 +
drivers/iommu/mtk_iommu_v1.c | 727 +++++++++++++++++++++++++++++++++++++++++++
3 files changed, 746 insertions(+)
create mode 100644 drivers/iommu/mtk_iommu_v1.c
diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig
index ad08603..32bb1e5 100644
--- a/drivers/iommu/Kconfig
+++ b/drivers/iommu/Kconfig
@@ -343,4 +343,22 @@ config MTK_IOMMU
If unsure, say N here.
+config MTK_IOMMU_V1
+ bool "MTK IOMMU Version 1 (M4U gen1) Support"
+ depends on ARM
+ depends on ARCH_MEDIATEK || COMPILE_TEST
+ select ARM_DMA_USE_IOMMU
+ select IOMMU_API
+ select MEMORY
+ select MTK_SMI
+ select COMMON_CLK_MT2701_MMSYS
+ select COMMON_CLK_MT2701_IMGSYS
+ select COMMON_CLK_MT2701_VDECSYS
+ help
+ Support for the M4U on certain Mediatek SoCs. M4U generation 1 HW is
+ Multimedia Memory Managememt Unit. This option enables remapping of
+ DMA memory accesses for the multimedia subsystem.
+
+ if unsure, say N here.
+
endif # IOMMU_SUPPORT
diff --git a/drivers/iommu/Makefile b/drivers/iommu/Makefile
index c6edb31..778baf5 100644
--- a/drivers/iommu/Makefile
+++ b/drivers/iommu/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_INTEL_IOMMU_SVM) += intel-svm.o
obj-$(CONFIG_IPMMU_VMSA) += ipmmu-vmsa.o
obj-$(CONFIG_IRQ_REMAP) += intel_irq_remapping.o irq_remapping.o
obj-$(CONFIG_MTK_IOMMU) += mtk_iommu.o
+obj-$(CONFIG_MTK_IOMMU_V1) += mtk_iommu_v1.o
obj-$(CONFIG_OMAP_IOMMU) += omap-iommu.o
obj-$(CONFIG_OMAP_IOMMU_DEBUG) += omap-iommu-debug.o
obj-$(CONFIG_ROCKCHIP_IOMMU) += rockchip-iommu.o
diff --git a/drivers/iommu/mtk_iommu_v1.c b/drivers/iommu/mtk_iommu_v1.c
new file mode 100644
index 0000000..294485d
--- /dev/null
+++ b/drivers/iommu/mtk_iommu_v1.c
@@ -0,0 +1,727 @@
+/*
+ * Copyright (c) 2015-2016 MediaTek Inc.
+ * Author: Honghui Zhang <honghui.zhang@mediatek.com>
+ *
+ * Based on driver/iommu/mtk_iommu.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <linux/bootmem.h>
+#include <linux/bug.h>
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/device.h>
+#include <linux/dma-iommu.h>
+#include <linux/err.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/iommu.h>
+#include <linux/iopoll.h>
+#include <linux/kmemleak.h>
+#include <linux/list.h>
+#include <linux/of_address.h>
+#include <linux/of_iommu.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <asm/barrier.h>
+#include <asm/dma-iommu.h>
+#include <linux/module.h>
+#include <dt-bindings/memory/mt2701-larb-port.h>
+#include <soc/mediatek/smi.h>
+#include "mtk_iommu.h"
+
+#define REG_MMU_PT_BASE_ADDR 0x000
+
+#define F_ALL_INVLD 0x2
+#define F_MMU_INV_RANGE 0x1
+#define F_INVLD_EN0 BIT(0)
+#define F_INVLD_EN1 BIT(1)
+
+#define F_MMU_FAULT_VA_MSK 0xfffff000
+#define MTK_PROTECT_PA_ALIGN 128
+
+#define REG_MMU_CTRL_REG 0x210
+#define F_MMU_CTRL_COHERENT_EN BIT(8)
+#define REG_MMU_IVRP_PADDR 0x214
+#define REG_MMU_INT_CONTROL 0x220
+#define F_INT_TRANSLATION_FAULT BIT(0)
+#define F_INT_MAIN_MULTI_HIT_FAULT BIT(1)
+#define F_INT_INVALID_PA_FAULT BIT(2)
+#define F_INT_ENTRY_REPLACEMENT_FAULT BIT(3)
+#define F_INT_TABLE_WALK_FAULT BIT(4)
+#define F_INT_TLB_MISS_FAULT BIT(5)
+#define F_INT_PFH_DMA_FIFO_OVERFLOW BIT(6)
+#define F_INT_MISS_DMA_FIFO_OVERFLOW BIT(7)
+
+#define F_MMU_TF_PROTECT_SEL(prot) (((prot) & 0x3) << 5)
+#define F_INT_CLR_BIT BIT(12)
+
+#define REG_MMU_FAULT_ST 0x224
+#define REG_MMU_FAULT_VA 0x228
+#define REG_MMU_INVLD_PA 0x22C
+#define REG_MMU_INT_ID 0x388
+#define REG_MMU_INVALIDATE 0x5c0
+#define REG_MMU_INVLD_START_A 0x5c4
+#define REG_MMU_INVLD_END_A 0x5c8
+
+#define REG_MMU_INV_SEL 0x5d8
+#define REG_MMU_STANDARD_AXI_MODE 0x5e8
+
+#define REG_MMU_DCM 0x5f0
+#define F_MMU_DCM_ON BIT(1)
+#define REG_MMU_CPE_DONE 0x60c
+#define F_DESC_VALID 0x2
+#define F_DESC_NONSEC BIT(3)
+#define MT2701_M4U_TF_LARB(TF) (6 - (((TF) >> 13) & 0x7))
+#define MT2701_M4U_TF_PORT(TF) (((TF) >> 8) & 0xF)
+/* MTK generation one iommu HW only support 4K size mapping */
+#define MT2701_IOMMU_PAGE_SHIFT 12
+#define MT2701_IOMMU_PAGE_SIZE (1UL << MT2701_IOMMU_PAGE_SHIFT)
+
+/*
+ * MTK m4u support 4GB iova address space, and only support 4K page
+ * mapping. So the pagetable size should be exactly as 4M.
+ */
+#define M2701_IOMMU_PGT_SIZE SZ_4M
+
+struct mtk_iommu_domain {
+ spinlock_t pgtlock; /* lock for page table */
+ struct iommu_domain domain;
+ u32 *pgt_va;
+ dma_addr_t pgt_pa;
+ struct mtk_iommu_data *data;
+};
+
+static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom)
+{
+ return container_of(dom, struct mtk_iommu_domain, domain);
+}
+
+static const int mt2701_m4u_in_larb[] = {
+ LARB0_PORT_OFFSET, LARB1_PORT_OFFSET,
+ LARB2_PORT_OFFSET, LARB3_PORT_OFFSET
+};
+
+static inline int mt2701_m4u_to_larb(int id)
+{
+ int i;
+
+ for (i = ARRAY_SIZE(mt2701_m4u_in_larb) - 1; i >= 0; i--)
+ if ((id) >= mt2701_m4u_in_larb[i])
+ return i;
+
+ return 0;
+}
+
+static inline int mt2701_m4u_to_port(int id)
+{
+ int larb = mt2701_m4u_to_larb(id);
+
+ return id - mt2701_m4u_in_larb[larb];
+}
+
+static void mtk_iommu_tlb_flush_all(struct mtk_iommu_data *data)
+{
+ writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
+ data->base + REG_MMU_INV_SEL);
+ writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE);
+ wmb(); /* Make sure the tlb flush all done */
+}
+
+static void mtk_iommu_tlb_flush_range(struct mtk_iommu_data *data,
+ unsigned long iova, size_t size)
+{
+ int ret;
+ u32 tmp;
+
+ writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
+ data->base + REG_MMU_INV_SEL);
+ writel_relaxed(iova & F_MMU_FAULT_VA_MSK,
+ data->base + REG_MMU_INVLD_START_A);
+ writel_relaxed((iova + size - 1) & F_MMU_FAULT_VA_MSK,
+ data->base + REG_MMU_INVLD_END_A);
+ writel_relaxed(F_MMU_INV_RANGE, data->base + REG_MMU_INVALIDATE);
+
+ ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE,
+ tmp, tmp != 0, 10, 100000);
+ if (ret) {
+ dev_warn(data->dev,
+ "Partial TLB flush timed out, falling back to full flush\n");
+ mtk_iommu_tlb_flush_all(data);
+ }
+ /* Clear the CPE status */
+ writel_relaxed(0, data->base + REG_MMU_CPE_DONE);
+}
+
+static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
+{
+ struct mtk_iommu_data *data = dev_id;
+ struct mtk_iommu_domain *dom = data->m4u_dom;
+ u32 int_state, regval, fault_iova, fault_pa;
+ unsigned int fault_larb, fault_port;
+
+ /* Read error information from registers */
+ int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST);
+ fault_iova = readl_relaxed(data->base + REG_MMU_FAULT_VA);
+
+ fault_iova &= F_MMU_FAULT_VA_MSK;
+ fault_pa = readl_relaxed(data->base + REG_MMU_INVLD_PA);
+ regval = readl_relaxed(data->base + REG_MMU_INT_ID);
+ fault_larb = MT2701_M4U_TF_LARB(regval);
+ fault_port = MT2701_M4U_TF_PORT(regval);
+
+ /*
+ * MTK v1 iommu HW could not determine whether the fault is read or
+ * write fault, report as read fault.
+ */
+ if (report_iommu_fault(&dom->domain, data->dev, fault_iova,
+ IOMMU_FAULT_READ))
+ dev_err_ratelimited(data->dev,
+ "fault type=0x%x iova=0x%x pa=0x%x larb=%d port=%d\n",
+ int_state, fault_iova, fault_pa,
+ fault_larb, fault_port);
+
+ /* Interrupt clear */
+ regval = readl_relaxed(data->base + REG_MMU_INT_CONTROL);
+ regval |= F_INT_CLR_BIT;
+ writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL);
+
+ mtk_iommu_tlb_flush_all(data);
+
+ return IRQ_HANDLED;
+}
+
+static void mtk_iommu_config(struct mtk_iommu_data *data,
+ struct device *dev, bool enable)
+{
+ struct mtk_iommu_client_priv *head, *cur, *next;
+ struct mtk_smi_larb_iommu *larb_mmu;
+ unsigned int larbid, portid;
+
+ head = dev->archdata.iommu;
+ list_for_each_entry_safe(cur, next, &head->client, client) {
+ larbid = mt2701_m4u_to_larb(cur->mtk_m4u_id);
+ portid = mt2701_m4u_to_port(cur->mtk_m4u_id);
+ larb_mmu = &data->smi_imu.larb_imu[larbid];
+
+ dev_dbg(dev, "%s iommu port: %d\n",
+ enable ? "enable" : "disable", portid);
+
+ if (enable)
+ larb_mmu->mmu |= MTK_SMI_MMU_EN(portid);
+ else
+ larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid);
+ }
+}
+
+static int mtk_iommu_domain_finalise(struct mtk_iommu_data *data)
+{
+ struct mtk_iommu_domain *dom = data->m4u_dom;
+
+ spin_lock_init(&dom->pgtlock);
+
+ dom->pgt_va = dma_zalloc_coherent(data->dev,
+ M2701_IOMMU_PGT_SIZE,
+ &dom->pgt_pa, GFP_KERNEL);
+ if (!dom->pgt_va)
+ return -ENOMEM;
+
+ writel(dom->pgt_pa, data->base + REG_MMU_PT_BASE_ADDR);
+
+ dom->data = data;
+
+ return 0;
+}
+
+static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type)
+{
+ struct mtk_iommu_domain *dom;
+
+ if (type != IOMMU_DOMAIN_UNMANAGED)
+ return NULL;
+
+ dom = kzalloc(sizeof(*dom), GFP_KERNEL);
+ if (!dom)
+ return NULL;
+
+ return &dom->domain;
+}
+
+static void mtk_iommu_domain_free(struct iommu_domain *domain)
+{
+ struct mtk_iommu_domain *dom = to_mtk_domain(domain);
+ struct mtk_iommu_data *data = dom->data;
+
+ dma_free_coherent(data->dev, M2701_IOMMU_PGT_SIZE,
+ dom->pgt_va, dom->pgt_pa);
+ kfree(to_mtk_domain(domain));
+}
+
+static int mtk_iommu_attach_device(struct iommu_domain *domain,
+ struct device *dev)
+{
+ struct mtk_iommu_domain *dom = to_mtk_domain(domain);
+ struct mtk_iommu_client_priv *priv = dev->archdata.iommu;
+ struct mtk_iommu_data *data;
+ int ret;
+
+ if (!priv)
+ return -ENODEV;
+
+ data = dev_get_drvdata(priv->m4udev);
+ if (!data->m4u_dom) {
+ data->m4u_dom = dom;
+ ret = mtk_iommu_domain_finalise(data);
+ if (ret) {
+ data->m4u_dom = NULL;
+ return ret;
+ }
+ }
+
+ mtk_iommu_config(data, dev, true);
+ return 0;
+}
+
+static void mtk_iommu_detach_device(struct iommu_domain *domain,
+ struct device *dev)
+{
+ struct mtk_iommu_client_priv *priv = dev->archdata.iommu;
+ struct mtk_iommu_data *data;
+
+ if (!priv)
+ return;
+
+ data = dev_get_drvdata(priv->m4udev);
+ mtk_iommu_config(data, dev, false);
+}
+
+static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova,
+ phys_addr_t paddr, size_t size, int prot)
+{
+ struct mtk_iommu_domain *dom = to_mtk_domain(domain);
+ unsigned int page_num = size >> MT2701_IOMMU_PAGE_SHIFT;
+ unsigned long flags;
+ unsigned int i;
+ u32 *pgt_base_iova = dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT);
+ u32 pabase = (u32)paddr;
+ int map_size = 0;
+
+ spin_lock_irqsave(&dom->pgtlock, flags);
+ for (i = 0; i < page_num; i++) {
+ if (pgt_base_iova[i]) {
+ memset(pgt_base_iova, 0, i * sizeof(u32));
+ break;
+ }
+ pgt_base_iova[i] = pabase | F_DESC_VALID | F_DESC_NONSEC;
+ pabase += MT2701_IOMMU_PAGE_SIZE;
+ map_size += MT2701_IOMMU_PAGE_SIZE;
+ }
+
+ spin_unlock_irqrestore(&dom->pgtlock, flags);
+
+ mtk_iommu_tlb_flush_range(dom->data, iova, size);
+
+ return map_size == size ? 0 : -EEXIST;
+}
+
+static size_t mtk_iommu_unmap(struct iommu_domain *domain,
+ unsigned long iova, size_t size)
+{
+ struct mtk_iommu_domain *dom = to_mtk_domain(domain);
+ unsigned long flags;
+ u32 *pgt_base_iova = dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT);
+ unsigned int page_num = size >> MT2701_IOMMU_PAGE_SHIFT;
+
+ spin_lock_irqsave(&dom->pgtlock, flags);
+ memset(pgt_base_iova, 0, page_num * sizeof(u32));
+ spin_unlock_irqrestore(&dom->pgtlock, flags);
+
+ mtk_iommu_tlb_flush_range(dom->data, iova, size);
+
+ return size;
+}
+
+static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
+ dma_addr_t iova)
+{
+ struct mtk_iommu_domain *dom = to_mtk_domain(domain);
+ unsigned long flags;
+ phys_addr_t pa;
+
+ spin_lock_irqsave(&dom->pgtlock, flags);
+ pa = *(dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT));
+ pa = pa & (~(MT2701_IOMMU_PAGE_SIZE - 1));
+ spin_unlock_irqrestore(&dom->pgtlock, flags);
+
+ return pa;
+}
+
+/*
+ * MTK generation one iommu HW only support one iommu domain, and all the client
+ * sharing the same iova address space.
+ */
+static int mtk_iommu_create_mapping(struct device *dev,
+ struct of_phandle_args *args)
+{
+ struct mtk_iommu_client_priv *head, *priv, *next;
+ struct platform_device *m4updev;
+ struct dma_iommu_mapping *mtk_mapping;
+ struct device *m4udev;
+ int ret;
+
+ if (args->args_count != 1) {
+ dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n",
+ args->args_count);
+ return -EINVAL;
+ }
+
+ if (!dev->archdata.iommu) {
+ /* Get the m4u device */
+ m4updev = of_find_device_by_node(args->np);
+ if (WARN_ON(!m4updev))
+ return -EINVAL;
+
+ head = kzalloc(sizeof(*head), GFP_KERNEL);
+ if (!head)
+ return -ENOMEM;
+
+ dev->archdata.iommu = head;
+ INIT_LIST_HEAD(&head->client);
+ head->m4udev = &m4updev->dev;
+ } else {
+ head = dev->archdata.iommu;
+ }
+
+ priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+ if (!priv) {
+ ret = -ENOMEM;
+ goto err_free_mem;
+ }
+ priv->mtk_m4u_id = args->args[0];
+ list_add_tail(&priv->client, &head->client);
+
+ m4udev = head->m4udev;
+ mtk_mapping = m4udev->archdata.iommu;
+ if (!mtk_mapping) {
+ /* MTK iommu support 4GB iova address space. */
+ mtk_mapping = arm_iommu_create_mapping(&platform_bus_type,
+ 0, 1ULL << 32);
+ if (IS_ERR(mtk_mapping)) {
+ ret = PTR_ERR(mtk_mapping);
+ goto err_free_mem;
+ }
+ m4udev->archdata.iommu = mtk_mapping;
+ }
+
+ ret = arm_iommu_attach_device(dev, mtk_mapping);
+ if (ret)
+ goto err_release_mapping;
+
+ return 0;
+
+err_release_mapping:
+ arm_iommu_release_mapping(mtk_mapping);
+ m4udev->archdata.iommu = NULL;
+err_free_mem:
+ list_for_each_entry_safe(priv, next, &head->client, client)
+ kfree(priv);
+ kfree(head);
+ dev->archdata.iommu = NULL;
+ return ret;
+}
+
+static int mtk_iommu_add_device(struct device *dev)
+{
+ struct iommu_group *group;
+ struct of_phandle_args iommu_spec;
+ struct of_phandle_iterator it;
+ int err;
+
+ of_for_each_phandle(&it, err, dev->of_node, "iommus",
+ "#iommu-cells", 0) {
+ int count = of_phandle_iterator_args(&it, iommu_spec.args,
+ MAX_PHANDLE_ARGS);
+ iommu_spec.np = of_node_get(it.node);
+ iommu_spec.args_count = count;
+
+ mtk_iommu_create_mapping(dev, &iommu_spec);
+ of_node_put(iommu_spec.np);
+ }
+
+ if (!dev->archdata.iommu) /* Not a iommu client device */
+ return -ENODEV;
+
+ group = iommu_group_get_for_dev(dev);
+ if (IS_ERR(group))
+ return PTR_ERR(group);
+
+ iommu_group_put(group);
+ return 0;
+}
+
+static void mtk_iommu_remove_device(struct device *dev)
+{
+ struct mtk_iommu_client_priv *head, *cur, *next;
+
+ head = dev->archdata.iommu;
+ if (!head)
+ return;
+
+ list_for_each_entry_safe(cur, next, &head->client, client) {
+ list_del(&cur->client);
+ kfree(cur);
+ }
+ kfree(head);
+ dev->archdata.iommu = NULL;
+
+ iommu_group_remove_device(dev);
+}
+
+static struct iommu_group *mtk_iommu_device_group(struct device *dev)
+{
+ struct mtk_iommu_data *data;
+ struct mtk_iommu_client_priv *priv;
+
+ priv = dev->archdata.iommu;
+ if (!priv)
+ return ERR_PTR(-ENODEV);
+
+ /* All the client devices are in the same m4u iommu-group */
+ data = dev_get_drvdata(priv->m4udev);
+ if (!data->m4u_group) {
+ data->m4u_group = iommu_group_alloc();
+ if (IS_ERR(data->m4u_group))
+ dev_err(dev, "Failed to allocate M4U IOMMU group\n");
+ }
+ return data->m4u_group;
+}
+
+static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
+{
+ u32 regval;
+ int ret;
+
+ ret = clk_prepare_enable(data->bclk);
+ if (ret) {
+ dev_err(data->dev, "Failed to enable iommu bclk(%d)\n", ret);
+ return ret;
+ }
+
+ regval = F_MMU_CTRL_COHERENT_EN | F_MMU_TF_PROTECT_SEL(2);
+ writel_relaxed(regval, data->base + REG_MMU_CTRL_REG);
+
+ regval = F_INT_TRANSLATION_FAULT |
+ F_INT_MAIN_MULTI_HIT_FAULT |
+ F_INT_INVALID_PA_FAULT |
+ F_INT_ENTRY_REPLACEMENT_FAULT |
+ F_INT_TABLE_WALK_FAULT |
+ F_INT_TLB_MISS_FAULT |
+ F_INT_PFH_DMA_FIFO_OVERFLOW |
+ F_INT_MISS_DMA_FIFO_OVERFLOW;
+ writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL);
+
+ /* protect memory,hw will write here while translation fault */
+ writel_relaxed(data->protect_base,
+ data->base + REG_MMU_IVRP_PADDR);
+
+ writel_relaxed(F_MMU_DCM_ON, data->base + REG_MMU_DCM);
+
+ if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0,
+ dev_name(data->dev), (void *)data)) {
+ writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR);
+ clk_disable_unprepare(data->bclk);
+ dev_err(data->dev, "Failed @ IRQ-%d Request\n", data->irq);
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+static struct iommu_ops mtk_iommu_ops = {
+ .domain_alloc = mtk_iommu_domain_alloc,
+ .domain_free = mtk_iommu_domain_free,
+ .attach_dev = mtk_iommu_attach_device,
+ .detach_dev = mtk_iommu_detach_device,
+ .map = mtk_iommu_map,
+ .unmap = mtk_iommu_unmap,
+ .map_sg = default_iommu_map_sg,
+ .iova_to_phys = mtk_iommu_iova_to_phys,
+ .add_device = mtk_iommu_add_device,
+ .remove_device = mtk_iommu_remove_device,
+ .device_group = mtk_iommu_device_group,
+ .pgsize_bitmap = ~0UL << MT2701_IOMMU_PAGE_SHIFT,
+};
+
+static const struct of_device_id mtk_iommu_of_ids[] = {
+ { .compatible = "mediatek,mt2701-m4u", },
+ {}
+};
+
+static const struct component_master_ops mtk_iommu_com_ops = {
+ .bind = mtk_iommu_bind,
+ .unbind = mtk_iommu_unbind,
+};
+
+static int mtk_iommu_probe(struct platform_device *pdev)
+{
+ struct mtk_iommu_data *data;
+ struct device *dev = &pdev->dev;
+ struct resource *res;
+ struct component_match *match = NULL;
+ struct of_phandle_args larb_spec;
+ struct of_phandle_iterator it;
+ void *protect;
+ int larb_nr, ret, err;
+
+ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ data->dev = dev;
+
+ /* Protect memory. HW will access here while translation fault.*/
+ protect = devm_kzalloc(dev, MTK_PROTECT_PA_ALIGN * 2,
+ GFP_KERNEL | GFP_DMA);
+ if (!protect)
+ return -ENOMEM;
+ data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ data->base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(data->base))
+ return PTR_ERR(data->base);
+
+ data->irq = platform_get_irq(pdev, 0);
+ if (data->irq < 0)
+ return data->irq;
+
+ data->bclk = devm_clk_get(dev, "bclk");
+ if (IS_ERR(data->bclk))
+ return PTR_ERR(data->bclk);
+
+ larb_nr = 0;
+ of_for_each_phandle(&it, err, dev->of_node,
+ "mediatek,larbs", NULL, 0) {
+ struct platform_device *plarbdev;
+ int count = of_phandle_iterator_args(&it, larb_spec.args,
+ MAX_PHANDLE_ARGS);
+
+ if (count)
+ continue;
+
+ larb_spec.np = of_node_get(it.node);
+ if (!of_device_is_available(larb_spec.np))
+ continue;
+
+ plarbdev = of_find_device_by_node(larb_spec.np);
+ of_node_put(larb_spec.np);
+ if (!plarbdev) {
+ plarbdev = of_platform_device_create(
+ larb_spec.np, NULL,
+ platform_bus_type.dev_root);
+ if (!plarbdev)
+ return -EPROBE_DEFER;
+ }
+
+ data->smi_imu.larb_imu[larb_nr].dev = &plarbdev->dev;
+ component_match_add(dev, &match, compare_of, larb_spec.np);
+ larb_nr++;
+ }
+
+ data->smi_imu.larb_nr = larb_nr;
+
+ platform_set_drvdata(pdev, data);
+
+ ret = mtk_iommu_hw_init(data);
+ if (ret)
+ return ret;
+
+ if (!iommu_present(&platform_bus_type))
+ bus_set_iommu(&platform_bus_type, &mtk_iommu_ops);
+
+ return component_master_add_with_match(dev, &mtk_iommu_com_ops, match);
+}
+
+static int mtk_iommu_remove(struct platform_device *pdev)
+{
+ struct mtk_iommu_data *data = platform_get_drvdata(pdev);
+
+ if (iommu_present(&platform_bus_type))
+ bus_set_iommu(&platform_bus_type, NULL);
+
+ clk_disable_unprepare(data->bclk);
+ devm_free_irq(&pdev->dev, data->irq, data);
+ component_master_del(&pdev->dev, &mtk_iommu_com_ops);
+ return 0;
+}
+
+static int __maybe_unused mtk_iommu_suspend(struct device *dev)
+{
+ struct mtk_iommu_data *data = dev_get_drvdata(dev);
+ struct mtk_iommu_suspend_reg *reg = &data->reg;
+ void __iomem *base = data->base;
+
+ reg->standard_axi_mode = readl_relaxed(base +
+ REG_MMU_STANDARD_AXI_MODE);
+ reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM);
+ reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG);
+ reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL);
+ return 0;
+}
+
+static int __maybe_unused mtk_iommu_resume(struct device *dev)
+{
+ struct mtk_iommu_data *data = dev_get_drvdata(dev);
+ struct mtk_iommu_suspend_reg *reg = &data->reg;
+ void __iomem *base = data->base;
+
+ writel_relaxed(data->m4u_dom->pgt_pa, base + REG_MMU_PT_BASE_ADDR);
+ writel_relaxed(reg->standard_axi_mode,
+ base + REG_MMU_STANDARD_AXI_MODE);
+ writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM);
+ writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG);
+ writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL);
+ writel_relaxed(data->protect_base, base + REG_MMU_IVRP_PADDR);
+ return 0;
+}
+
+const struct dev_pm_ops mtk_iommu_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(mtk_iommu_suspend, mtk_iommu_resume)
+};
+
+static struct platform_driver mtk_iommu_driver = {
+ .probe = mtk_iommu_probe,
+ .remove = mtk_iommu_remove,
+ .driver = {
+ .name = "mtk-iommu",
+ .of_match_table = mtk_iommu_of_ids,
+ .pm = &mtk_iommu_pm_ops,
+ }
+};
+
+static int __init m4u_init(void)
+{
+ return platform_driver_register(&mtk_iommu_driver);
+}
+
+static void __exit m4u_exit(void)
+{
+ return platform_driver_unregister(&mtk_iommu_driver);
+}
+
+subsys_initcall(m4u_init);
+module_exit(m4u_exit);
+
+MODULE_DESCRIPTION("IOMMU API for MTK architected m4u v1 implementations");
+MODULE_AUTHOR("Honghui Zhang <honghui.zhang@mediatek.com>");
+MODULE_LICENSE("GPL v2");
--
1.8.1.1.dirty
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v4 5/5] ARM: dts: mt2701: add iommu/smi dtsi node for mt2701
2016-06-08 9:50 [PATCH v4 0/5] MT2701 iommu support honghui.zhang
` (3 preceding siblings ...)
2016-06-08 9:51 ` [PATCH v4 4/5] iommu/mediatek: add support for mtk iommu generation one HW honghui.zhang
@ 2016-06-08 9:51 ` honghui.zhang
2016-06-21 9:41 ` Joerg Roedel
` (2 more replies)
4 siblings, 3 replies; 20+ messages in thread
From: honghui.zhang @ 2016-06-08 9:51 UTC (permalink / raw)
To: joro, treding, mark.rutland, matthias.bgg, robh, robin.murphy
Cc: p.zabel, devicetree, pebolle, kendrick.hsu, arnd, srv_heupstream,
catalin.marinas, will.deacon, linux-kernel, tfiga, iommu,
robh+dt, djkurtz, kernel, linux-mediatek, linux-arm-kernel,
l.stach, yingjoe.chen, eddie.huang, youlin.pei, erin.lo,
Honghui Zhang
From: Honghui Zhang <honghui.zhang@mediatek.com>
Add the dtsi node of iommu and smi for mt2701.
Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
---
arch/arm/boot/dts/mt2701.dtsi | 51 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 51 insertions(+)
diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 42d5a37..363de0d 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -16,6 +16,7 @@
#include <dt-bindings/power/mt2701-power.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/memory/mt2701-larb-port.h>
#include "skeleton64.dtsi"
#include "mt2701-pinfunc.h"
@@ -160,6 +161,16 @@
clock-names = "system-clk", "rtc-clk";
};
+ smi_common: smi@1000c000 {
+ compatible = "mediatek,mt2701-smi-common";
+ reg = <0 0x1000c000 0 0x1000>;
+ clocks = <&infracfg CLK_INFRA_SMI>,
+ <&mmsys CLK_MM_SMI_COMMON>,
+ <&infracfg CLK_INFRA_SMI>;
+ clock-names = "apb", "smi", "async";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
+ };
+
sysirq: interrupt-controller@10200100 {
compatible = "mediatek,mt2701-sysirq",
"mediatek,mt6577-sysirq";
@@ -169,6 +180,16 @@
reg = <0 0x10200100 0 0x1c>;
};
+ iommu: mmsys_iommu@10205000 {
+ compatible = "mediatek,mt2701-m4u";
+ reg = <0 0x10205000 0 0x1000>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg CLK_INFRA_M4U>;
+ clock-names = "bclk";
+ mediatek,larbs = <&larb0 &larb1 &larb2>;
+ #iommu-cells = <1>;
+ };
+
apmixedsys: syscon@10209000 {
compatible = "mediatek,mt2701-apmixedsys", "syscon";
reg = <0 0x10209000 0 0x1000>;
@@ -234,6 +255,16 @@
status = "disabled";
};
+ larb0: larb@14010000 {
+ compatible = "mediatek,mt2701-smi-larb";
+ reg = <0 0x14010000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&mmsys CLK_MM_SMI_LARB0>,
+ <&mmsys CLK_MM_SMI_LARB0>;
+ clock-names = "apb", "smi";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
+ };
+
imgsys: syscon@15000000 {
compatible = "mediatek,mt2701-imgsys", "syscon";
reg = <0 0x15000000 0 0x1000>;
@@ -241,6 +272,16 @@
status = "disabled";
};
+ larb2: larb@15001000 {
+ compatible = "mediatek,mt2701-smi-larb";
+ reg = <0 0x15001000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&imgsys CLK_IMG_SMI_COMM>,
+ <&imgsys CLK_IMG_SMI_COMM>;
+ clock-names = "apb", "smi";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
+ };
+
vdecsys: syscon@16000000 {
compatible = "mediatek,mt2701-vdecsys", "syscon";
reg = <0 0x16000000 0 0x1000>;
@@ -248,6 +289,16 @@
status = "disabled";
};
+ larb1: larb@16010000 {
+ compatible = "mediatek,mt2701-smi-larb";
+ reg = <0 0x16010000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&vdecsys CLK_VDEC_CKGEN>,
+ <&vdecsys CLK_VDEC_LARB>;
+ clock-names = "apb", "smi";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
+ };
+
hifsys: syscon@1a000000 {
compatible = "mediatek,mt2701-hifsys", "syscon";
reg = <0 0x1a000000 0 0x1000>;
--
1.8.1.1.dirty
^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH v4 5/5] ARM: dts: mt2701: add iommu/smi dtsi node for mt2701
2016-06-08 9:51 ` [PATCH v4 5/5] ARM: dts: mt2701: add iommu/smi dtsi node for mt2701 honghui.zhang
@ 2016-06-21 9:41 ` Joerg Roedel
2016-06-21 9:55 ` Honghui Zhang
2016-06-21 9:57 ` Joerg Roedel
2016-07-03 6:24 ` Matthias Brugger
2 siblings, 1 reply; 20+ messages in thread
From: Joerg Roedel @ 2016-06-21 9:41 UTC (permalink / raw)
To: honghui.zhang
Cc: treding, mark.rutland, matthias.bgg, robh, robin.murphy, p.zabel,
devicetree, pebolle, kendrick.hsu, arnd, srv_heupstream,
catalin.marinas, will.deacon, linux-kernel, tfiga, iommu,
robh+dt, djkurtz, kernel, linux-mediatek, linux-arm-kernel,
l.stach, yingjoe.chen, eddie.huang, youlin.pei, erin.lo
On Wed, Jun 08, 2016 at 05:51:01PM +0800, honghui.zhang@mediatek.com wrote:
> From: Honghui Zhang <honghui.zhang@mediatek.com>
>
> Add the dtsi node of iommu and smi for mt2701.
>
> Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
> ---
> arch/arm/boot/dts/mt2701.dtsi | 51 +++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 51 insertions(+)
Applied the series, except this last patch. It didn't apply cleanly and
I was not sure how to correctly fix that. Can you please resubmit the
patch based on my arm/mediatek branch once I pushed it?
Thanks,
Joerg
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v4 5/5] ARM: dts: mt2701: add iommu/smi dtsi node for mt2701
2016-06-21 9:41 ` Joerg Roedel
@ 2016-06-21 9:55 ` Honghui Zhang
0 siblings, 0 replies; 20+ messages in thread
From: Honghui Zhang @ 2016-06-21 9:55 UTC (permalink / raw)
To: Joerg Roedel
Cc: treding, mark.rutland, matthias.bgg, robh, robin.murphy, p.zabel,
devicetree, pebolle, kendrick.hsu, arnd, srv_heupstream,
catalin.marinas, will.deacon, linux-kernel, tfiga, iommu,
robh+dt, djkurtz, kernel, linux-mediatek, linux-arm-kernel,
l.stach, yingjoe.chen, eddie.huang, youlin.pei, erin.lo
On Tue, 2016-06-21 at 11:41 +0200, Joerg Roedel wrote:
> On Wed, Jun 08, 2016 at 05:51:01PM +0800, honghui.zhang@mediatek.com wrote:
> > From: Honghui Zhang <honghui.zhang@mediatek.com>
> >
> > Add the dtsi node of iommu and smi for mt2701.
> >
> > Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
> > ---
> > arch/arm/boot/dts/mt2701.dtsi | 51 +++++++++++++++++++++++++++++++++++++++++++
> > 1 file changed, 51 insertions(+)
>
> Applied the series, except this last patch. It didn't apply cleanly and
> I was not sure how to correctly fix that. Can you please resubmit the
> patch based on my arm/mediatek branch once I pushed it?
>
I will rebase this one later after your push.
Thanks.
> Thanks,
>
> Joerg
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v4 5/5] ARM: dts: mt2701: add iommu/smi dtsi node for mt2701
2016-06-08 9:51 ` [PATCH v4 5/5] ARM: dts: mt2701: add iommu/smi dtsi node for mt2701 honghui.zhang
2016-06-21 9:41 ` Joerg Roedel
@ 2016-06-21 9:57 ` Joerg Roedel
2016-06-22 5:45 ` Eddie Huang
2016-07-03 6:24 ` Matthias Brugger
2 siblings, 1 reply; 20+ messages in thread
From: Joerg Roedel @ 2016-06-21 9:57 UTC (permalink / raw)
To: honghui.zhang
Cc: treding, mark.rutland, matthias.bgg, robh, robin.murphy, p.zabel,
devicetree, pebolle, kendrick.hsu, arnd, srv_heupstream,
catalin.marinas, will.deacon, linux-kernel, tfiga, iommu,
robh+dt, djkurtz, kernel, linux-mediatek, linux-arm-kernel,
l.stach, yingjoe.chen, eddie.huang, youlin.pei, erin.lo
On Wed, Jun 08, 2016 at 05:51:01PM +0800, honghui.zhang@mediatek.com wrote:
> From: Honghui Zhang <honghui.zhang@mediatek.com>
>
> Add the dtsi node of iommu and smi for mt2701.
>
> Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
> ---
> arch/arm/boot/dts/mt2701.dtsi | 51 +++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 51 insertions(+)
Okay, I pushed my arm/mediatek branch to my tree at
git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git
Please base the patch on that branch and re-send.
Thanks,
Joerg
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v4 5/5] ARM: dts: mt2701: add iommu/smi dtsi node for mt2701
2016-06-21 9:57 ` Joerg Roedel
@ 2016-06-22 5:45 ` Eddie Huang
2016-06-22 7:45 ` Honghui Zhang
0 siblings, 1 reply; 20+ messages in thread
From: Eddie Huang @ 2016-06-22 5:45 UTC (permalink / raw)
To: Joerg Roedel, matthias.bgg
Cc: Honghui Zhang (张洪辉),
treding, mark.rutland, robh, robin.murphy, p.zabel, devicetree,
pebolle, Kendrick Hsu (徐子凡),
arnd, srv_heupstream, catalin.marinas, will.deacon, linux-kernel,
tfiga, iommu, robh+dt, djkurtz, kernel, linux-mediatek,
linux-arm-kernel, l.stach, Yingjoe Chen (??英洲),
Youlin Pei (裴友林), Erin Lo (?_雅?g)
On Tue, 2016-06-21 at 17:57 +0800, Joerg Roedel wrote:
> On Wed, Jun 08, 2016 at 05:51:01PM +0800, honghui.zhang@mediatek.com wrote:
> > From: Honghui Zhang <honghui.zhang@mediatek.com>
> >
> > Add the dtsi node of iommu and smi for mt2701.
> >
> > Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
> > ---
> > arch/arm/boot/dts/mt2701.dtsi | 51 +++++++++++++++++++++++++++++++++++++++++++
> > 1 file changed, 51 insertions(+)
>
> Okay, I pushed my arm/mediatek branch to my tree at
>
> git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git
>
> Please base the patch on that branch and re-send.
>
I think it is better let Mediatek SoC maintainer Matthias to accept dtsi
patch like other drivers. This can avoid dtsi conflict. As I
remember,last time MT8173 IOMMU dtsi patch accepted in iommu tree and
mt8173.dtsi had conflict with arm soc tree at the merge window. Honghui
should resend this patch to Matthias, and elaborate your dependency with
clock and power domain dtsi, then Matthias know the merge sequence.
Eddie
Thanks
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v4 5/5] ARM: dts: mt2701: add iommu/smi dtsi node for mt2701
2016-06-22 5:45 ` Eddie Huang
@ 2016-06-22 7:45 ` Honghui Zhang
2016-06-22 8:31 ` Joerg Roedel
0 siblings, 1 reply; 20+ messages in thread
From: Honghui Zhang @ 2016-06-22 7:45 UTC (permalink / raw)
To: Eddie Huang
Cc: Joerg Roedel, matthias.bgg, treding, mark.rutland, robh,
robin.murphy, p.zabel, devicetree, pebolle,
Kendrick Hsu (徐子凡),
arnd, srv_heupstream, catalin.marinas, will.deacon, linux-kernel,
tfiga, iommu, robh+dt, djkurtz, kernel, linux-mediatek,
linux-arm-kernel, l.stach, Yingjoe Chen (??英洲),
Youlin Pei (裴友林), Erin Lo (?_雅?g)
On Wed, 2016-06-22 at 13:45 +0800, Eddie Huang wrote:
> On Tue, 2016-06-21 at 17:57 +0800, Joerg Roedel wrote:
> > On Wed, Jun 08, 2016 at 05:51:01PM +0800, honghui.zhang@mediatek.com wrote:
> > > From: Honghui Zhang <honghui.zhang@mediatek.com>
> > >
> > > Add the dtsi node of iommu and smi for mt2701.
> > >
> > > Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
> > > ---
> > > arch/arm/boot/dts/mt2701.dtsi | 51 +++++++++++++++++++++++++++++++++++++++++++
> > > 1 file changed, 51 insertions(+)
> >
> > Okay, I pushed my arm/mediatek branch to my tree at
> >
> > git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git
> >
> > Please base the patch on that branch and re-send.
> >
>
> I think it is better let Mediatek SoC maintainer Matthias to accept dtsi
> patch like other drivers. This can avoid dtsi conflict. As I
> remember,last time MT8173 IOMMU dtsi patch accepted in iommu tree and
> mt8173.dtsi had conflict with arm soc tree at the merge window. Honghui
> should resend this patch to Matthias, and elaborate your dependency with
> clock and power domain dtsi, then Matthias know the merge sequence.
>
Thanks, Eddie.
Hi, Joerg,
This one is based on CCF "arm: dts: mt2701: Add clock controller device
nodes"[1] and power domain patch "Mediatek MT2701 SCPSYS power domain
support v7"[2],
But these two patchset are still being review now.
Do you think it's better that I send this one later after ccf and power
domain patch got merged, and let Matthias take it?
Thanks.
[1] https://patchwork.kernel.org/patch/9109081
[2]
http://lists.infradead.org/pipermail/linux-mediatek/2016-May/005429.html
> Eddie
> Thanks
>
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v4 5/5] ARM: dts: mt2701: add iommu/smi dtsi node for mt2701
2016-06-22 7:45 ` Honghui Zhang
@ 2016-06-22 8:31 ` Joerg Roedel
2016-06-22 8:39 ` Honghui Zhang
0 siblings, 1 reply; 20+ messages in thread
From: Joerg Roedel @ 2016-06-22 8:31 UTC (permalink / raw)
To: Honghui Zhang
Cc: Eddie Huang, matthias.bgg, treding, mark.rutland, robh,
robin.murphy, p.zabel, devicetree, pebolle,
Kendrick Hsu (徐子凡),
arnd, srv_heupstream, catalin.marinas, will.deacon, linux-kernel,
tfiga, iommu, robh+dt, djkurtz, kernel, linux-mediatek,
linux-arm-kernel, l.stach, Yingjoe Chen (??英洲),
Youlin Pei (裴友林), Erin Lo (?_雅?g)
On Wed, Jun 22, 2016 at 03:45:47PM +0800, Honghui Zhang wrote:
> This one is based on CCF "arm: dts: mt2701: Add clock controller device
> nodes"[1] and power domain patch "Mediatek MT2701 SCPSYS power domain
> support v7"[2],
> But these two patchset are still being review now.
>
> Do you think it's better that I send this one later after ccf and power
> domain patch got merged, and let Matthias take it?
Sure, but the patches I already merged can stay in the tree for now?
Joerg
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v4 5/5] ARM: dts: mt2701: add iommu/smi dtsi node for mt2701
2016-06-22 8:31 ` Joerg Roedel
@ 2016-06-22 8:39 ` Honghui Zhang
2016-06-22 8:58 ` Joerg Roedel
0 siblings, 1 reply; 20+ messages in thread
From: Honghui Zhang @ 2016-06-22 8:39 UTC (permalink / raw)
To: Joerg Roedel
Cc: Eddie Huang, matthias.bgg, treding, mark.rutland, robh,
robin.murphy, p.zabel, devicetree, pebolle,
Kendrick Hsu (徐子凡),
arnd, srv_heupstream, catalin.marinas, will.deacon, linux-kernel,
tfiga, iommu, robh+dt, djkurtz, kernel, linux-mediatek,
linux-arm-kernel, l.stach, Yingjoe Chen (??英洲),
Youlin Pei (裴友林), Erin Lo (?_雅?g)
On Wed, 2016-06-22 at 10:31 +0200, Joerg Roedel wrote:
> On Wed, Jun 22, 2016 at 03:45:47PM +0800, Honghui Zhang wrote:
> > This one is based on CCF "arm: dts: mt2701: Add clock controller device
> > nodes"[1] and power domain patch "Mediatek MT2701 SCPSYS power domain
> > support v7"[2],
> > But these two patchset are still being review now.
> >
> > Do you think it's better that I send this one later after ccf and power
> > domain patch got merged, and let Matthias take it?
>
> Sure, but the patches I already merged can stay in the tree for now?
>
>
I think that driver and dtsi could merged separately, I would prefer
those previous patches stay in the tree if it's OK for you.
Thanks.
>
> Joerg
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v4 5/5] ARM: dts: mt2701: add iommu/smi dtsi node for mt2701
2016-06-22 8:39 ` Honghui Zhang
@ 2016-06-22 8:58 ` Joerg Roedel
0 siblings, 0 replies; 20+ messages in thread
From: Joerg Roedel @ 2016-06-22 8:58 UTC (permalink / raw)
To: Honghui Zhang
Cc: Eddie Huang, matthias.bgg, treding, mark.rutland, robh,
robin.murphy, p.zabel, devicetree, pebolle,
Kendrick Hsu (徐子凡),
arnd, srv_heupstream, catalin.marinas, will.deacon, linux-kernel,
tfiga, iommu, robh+dt, djkurtz, kernel, linux-mediatek,
linux-arm-kernel, l.stach, Yingjoe Chen (??英洲),
Youlin Pei (裴友林), Erin Lo (?_雅?g)
On Wed, Jun 22, 2016 at 04:39:01PM +0800, Honghui Zhang wrote:
> I think that driver and dtsi could merged separately, I would prefer
> those previous patches stay in the tree if it's OK for you.
Sure, I send them upstream through my tree.
Thanks,
Joerg
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v4 5/5] ARM: dts: mt2701: add iommu/smi dtsi node for mt2701
2016-06-08 9:51 ` [PATCH v4 5/5] ARM: dts: mt2701: add iommu/smi dtsi node for mt2701 honghui.zhang
2016-06-21 9:41 ` Joerg Roedel
2016-06-21 9:57 ` Joerg Roedel
@ 2016-07-03 6:24 ` Matthias Brugger
2016-07-03 19:12 ` Matthias Brugger
2 siblings, 1 reply; 20+ messages in thread
From: Matthias Brugger @ 2016-07-03 6:24 UTC (permalink / raw)
To: honghui.zhang, joro, treding, mark.rutland, robh, robin.murphy
Cc: p.zabel, devicetree, pebolle, kendrick.hsu, arnd, srv_heupstream,
catalin.marinas, will.deacon, linux-kernel, tfiga, iommu,
robh+dt, djkurtz, kernel, linux-mediatek, linux-arm-kernel,
l.stach, yingjoe.chen, eddie.huang, youlin.pei, erin.lo
On 06/08/2016 11:51 AM, honghui.zhang@mediatek.com wrote:
> From: Honghui Zhang <honghui.zhang@mediatek.com>
>
> Add the dtsi node of iommu and smi for mt2701.
>
> Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
> ---
> arch/arm/boot/dts/mt2701.dtsi | 51 +++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 51 insertions(+)
>
Applied,
Thanks.
> diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
> index 42d5a37..363de0d 100644
> --- a/arch/arm/boot/dts/mt2701.dtsi
> +++ b/arch/arm/boot/dts/mt2701.dtsi
> @@ -16,6 +16,7 @@
> #include <dt-bindings/power/mt2701-power.h>
> #include <dt-bindings/interrupt-controller/irq.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/memory/mt2701-larb-port.h>
> #include "skeleton64.dtsi"
> #include "mt2701-pinfunc.h"
>
> @@ -160,6 +161,16 @@
> clock-names = "system-clk", "rtc-clk";
> };
>
> + smi_common: smi@1000c000 {
> + compatible = "mediatek,mt2701-smi-common";
> + reg = <0 0x1000c000 0 0x1000>;
> + clocks = <&infracfg CLK_INFRA_SMI>,
> + <&mmsys CLK_MM_SMI_COMMON>,
> + <&infracfg CLK_INFRA_SMI>;
> + clock-names = "apb", "smi", "async";
> + power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
> + };
> +
> sysirq: interrupt-controller@10200100 {
> compatible = "mediatek,mt2701-sysirq",
> "mediatek,mt6577-sysirq";
> @@ -169,6 +180,16 @@
> reg = <0 0x10200100 0 0x1c>;
> };
>
> + iommu: mmsys_iommu@10205000 {
> + compatible = "mediatek,mt2701-m4u";
> + reg = <0 0x10205000 0 0x1000>;
> + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&infracfg CLK_INFRA_M4U>;
> + clock-names = "bclk";
> + mediatek,larbs = <&larb0 &larb1 &larb2>;
> + #iommu-cells = <1>;
> + };
> +
> apmixedsys: syscon@10209000 {
> compatible = "mediatek,mt2701-apmixedsys", "syscon";
> reg = <0 0x10209000 0 0x1000>;
> @@ -234,6 +255,16 @@
> status = "disabled";
> };
>
> + larb0: larb@14010000 {
> + compatible = "mediatek,mt2701-smi-larb";
> + reg = <0 0x14010000 0 0x1000>;
> + mediatek,smi = <&smi_common>;
> + clocks = <&mmsys CLK_MM_SMI_LARB0>,
> + <&mmsys CLK_MM_SMI_LARB0>;
> + clock-names = "apb", "smi";
> + power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
> + };
> +
> imgsys: syscon@15000000 {
> compatible = "mediatek,mt2701-imgsys", "syscon";
> reg = <0 0x15000000 0 0x1000>;
> @@ -241,6 +272,16 @@
> status = "disabled";
> };
>
> + larb2: larb@15001000 {
> + compatible = "mediatek,mt2701-smi-larb";
> + reg = <0 0x15001000 0 0x1000>;
> + mediatek,smi = <&smi_common>;
> + clocks = <&imgsys CLK_IMG_SMI_COMM>,
> + <&imgsys CLK_IMG_SMI_COMM>;
> + clock-names = "apb", "smi";
> + power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
> + };
> +
> vdecsys: syscon@16000000 {
> compatible = "mediatek,mt2701-vdecsys", "syscon";
> reg = <0 0x16000000 0 0x1000>;
> @@ -248,6 +289,16 @@
> status = "disabled";
> };
>
> + larb1: larb@16010000 {
> + compatible = "mediatek,mt2701-smi-larb";
> + reg = <0 0x16010000 0 0x1000>;
> + mediatek,smi = <&smi_common>;
> + clocks = <&vdecsys CLK_VDEC_CKGEN>,
> + <&vdecsys CLK_VDEC_LARB>;
> + clock-names = "apb", "smi";
> + power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
> + };
> +
> hifsys: syscon@1a000000 {
> compatible = "mediatek,mt2701-hifsys", "syscon";
> reg = <0 0x1a000000 0 0x1000>;
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v4 5/5] ARM: dts: mt2701: add iommu/smi dtsi node for mt2701
2016-07-03 6:24 ` Matthias Brugger
@ 2016-07-03 19:12 ` Matthias Brugger
2016-07-04 1:32 ` Honghui Zhang
0 siblings, 1 reply; 20+ messages in thread
From: Matthias Brugger @ 2016-07-03 19:12 UTC (permalink / raw)
To: honghui.zhang, joro, treding, mark.rutland, robh, robin.murphy
Cc: p.zabel, devicetree, pebolle, kendrick.hsu, arnd, srv_heupstream,
catalin.marinas, will.deacon, linux-kernel, tfiga, iommu,
robh+dt, djkurtz, kernel, linux-mediatek, linux-arm-kernel,
l.stach, yingjoe.chen, eddie.huang, youlin.pei, erin.lo
On 07/03/2016 08:24 AM, Matthias Brugger wrote:
>
>
> On 06/08/2016 11:51 AM, honghui.zhang@mediatek.com wrote:
>> From: Honghui Zhang <honghui.zhang@mediatek.com>
>>
>> Add the dtsi node of iommu and smi for mt2701.
>>
>> Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
>> ---
>> arch/arm/boot/dts/mt2701.dtsi | 51
>> +++++++++++++++++++++++++++++++++++++++++++
>> 1 file changed, 51 insertions(+)
>>
>
> Applied,
Please resend the patch including the infracfg and mmsys node.
Regards,
Matthias
>
> Thanks.
>
>> diff --git a/arch/arm/boot/dts/mt2701.dtsi
>> b/arch/arm/boot/dts/mt2701.dtsi
>> index 42d5a37..363de0d 100644
>> --- a/arch/arm/boot/dts/mt2701.dtsi
>> +++ b/arch/arm/boot/dts/mt2701.dtsi
>> @@ -16,6 +16,7 @@
>> #include <dt-bindings/power/mt2701-power.h>
>> #include <dt-bindings/interrupt-controller/irq.h>
>> #include <dt-bindings/interrupt-controller/arm-gic.h>
>> +#include <dt-bindings/memory/mt2701-larb-port.h>
>> #include "skeleton64.dtsi"
>> #include "mt2701-pinfunc.h"
>>
>> @@ -160,6 +161,16 @@
>> clock-names = "system-clk", "rtc-clk";
>> };
>>
>> + smi_common: smi@1000c000 {
>> + compatible = "mediatek,mt2701-smi-common";
>> + reg = <0 0x1000c000 0 0x1000>;
>> + clocks = <&infracfg CLK_INFRA_SMI>,
>> + <&mmsys CLK_MM_SMI_COMMON>,
>> + <&infracfg CLK_INFRA_SMI>;
>> + clock-names = "apb", "smi", "async";
>> + power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
>> + };
>> +
>> sysirq: interrupt-controller@10200100 {
>> compatible = "mediatek,mt2701-sysirq",
>> "mediatek,mt6577-sysirq";
>> @@ -169,6 +180,16 @@
>> reg = <0 0x10200100 0 0x1c>;
>> };
>>
>> + iommu: mmsys_iommu@10205000 {
>> + compatible = "mediatek,mt2701-m4u";
>> + reg = <0 0x10205000 0 0x1000>;
>> + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
>> + clocks = <&infracfg CLK_INFRA_M4U>;
>> + clock-names = "bclk";
>> + mediatek,larbs = <&larb0 &larb1 &larb2>;
>> + #iommu-cells = <1>;
>> + };
>> +
>> apmixedsys: syscon@10209000 {
>> compatible = "mediatek,mt2701-apmixedsys", "syscon";
>> reg = <0 0x10209000 0 0x1000>;
>> @@ -234,6 +255,16 @@
>> status = "disabled";
>> };
>>
>> + larb0: larb@14010000 {
>> + compatible = "mediatek,mt2701-smi-larb";
>> + reg = <0 0x14010000 0 0x1000>;
>> + mediatek,smi = <&smi_common>;
>> + clocks = <&mmsys CLK_MM_SMI_LARB0>,
>> + <&mmsys CLK_MM_SMI_LARB0>;
>> + clock-names = "apb", "smi";
>> + power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
>> + };
>> +
>> imgsys: syscon@15000000 {
>> compatible = "mediatek,mt2701-imgsys", "syscon";
>> reg = <0 0x15000000 0 0x1000>;
>> @@ -241,6 +272,16 @@
>> status = "disabled";
>> };
>>
>> + larb2: larb@15001000 {
>> + compatible = "mediatek,mt2701-smi-larb";
>> + reg = <0 0x15001000 0 0x1000>;
>> + mediatek,smi = <&smi_common>;
>> + clocks = <&imgsys CLK_IMG_SMI_COMM>,
>> + <&imgsys CLK_IMG_SMI_COMM>;
>> + clock-names = "apb", "smi";
>> + power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
>> + };
>> +
>> vdecsys: syscon@16000000 {
>> compatible = "mediatek,mt2701-vdecsys", "syscon";
>> reg = <0 0x16000000 0 0x1000>;
>> @@ -248,6 +289,16 @@
>> status = "disabled";
>> };
>>
>> + larb1: larb@16010000 {
>> + compatible = "mediatek,mt2701-smi-larb";
>> + reg = <0 0x16010000 0 0x1000>;
>> + mediatek,smi = <&smi_common>;
>> + clocks = <&vdecsys CLK_VDEC_CKGEN>,
>> + <&vdecsys CLK_VDEC_LARB>;
>> + clock-names = "apb", "smi";
>> + power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
>> + };
>> +
>> hifsys: syscon@1a000000 {
>> compatible = "mediatek,mt2701-hifsys", "syscon";
>> reg = <0 0x1a000000 0 0x1000>;
>>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v4 5/5] ARM: dts: mt2701: add iommu/smi dtsi node for mt2701
2016-07-03 19:12 ` Matthias Brugger
@ 2016-07-04 1:32 ` Honghui Zhang
2016-07-04 8:00 ` Matthias Brugger
0 siblings, 1 reply; 20+ messages in thread
From: Honghui Zhang @ 2016-07-04 1:32 UTC (permalink / raw)
To: Matthias Brugger
Cc: joro, treding, mark.rutland, robh, robin.murphy, p.zabel,
devicetree, pebolle, kendrick.hsu, arnd, srv_heupstream,
catalin.marinas, will.deacon, linux-kernel, tfiga, iommu,
robh+dt, djkurtz, kernel, linux-mediatek, linux-arm-kernel,
l.stach, yingjoe.chen, eddie.huang, youlin.pei, erin.lo
On Sun, 2016-07-03 at 21:12 +0200, Matthias Brugger wrote:
>
> On 07/03/2016 08:24 AM, Matthias Brugger wrote:
> >
> >
> > On 06/08/2016 11:51 AM, honghui.zhang@mediatek.com wrote:
> >> From: Honghui Zhang <honghui.zhang@mediatek.com>
> >>
> >> Add the dtsi node of iommu and smi for mt2701.
> >>
> >> Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
> >> ---
> >> arch/arm/boot/dts/mt2701.dtsi | 51
> >> +++++++++++++++++++++++++++++++++++++++++++
> >> 1 file changed, 51 insertions(+)
> >>
> >
> > Applied,
>
> Please resend the patch including the infracfg and mmsys node.
>
Hi, Matthias,
Please hold this one.
This one is based on CCF "arm: dts: mt2701: Add clock controller device
nodes"[1] and power domain patch "Mediatek MT2701 SCPSYS power domain
support v7"[2],
But these two patchset are still being reviewed now.
Do you think it's better that I send this one later after ccf and power
domain patch got merged? I will send this patch later if it's OK with
you.
Thanks.
[1] https://patchwork.kernel.org/patch/9109081
[2]
http://lists.infradead.org/pipermail/linux-mediatek/2016-May/005429.html
> Regards,
> Matthias
>
> >
> > Thanks.
> >
> >> diff --git a/arch/arm/boot/dts/mt2701.dtsi
> >> b/arch/arm/boot/dts/mt2701.dtsi
> >> index 42d5a37..363de0d 100644
> >> --- a/arch/arm/boot/dts/mt2701.dtsi
> >> +++ b/arch/arm/boot/dts/mt2701.dtsi
> >> @@ -16,6 +16,7 @@
> >> #include <dt-bindings/power/mt2701-power.h>
> >> #include <dt-bindings/interrupt-controller/irq.h>
> >> #include <dt-bindings/interrupt-controller/arm-gic.h>
> >> +#include <dt-bindings/memory/mt2701-larb-port.h>
> >> #include "skeleton64.dtsi"
> >> #include "mt2701-pinfunc.h"
> >>
> >> @@ -160,6 +161,16 @@
> >> clock-names = "system-clk", "rtc-clk";
> >> };
> >>
> >> + smi_common: smi@1000c000 {
> >> + compatible = "mediatek,mt2701-smi-common";
> >> + reg = <0 0x1000c000 0 0x1000>;
> >> + clocks = <&infracfg CLK_INFRA_SMI>,
> >> + <&mmsys CLK_MM_SMI_COMMON>,
> >> + <&infracfg CLK_INFRA_SMI>;
> >> + clock-names = "apb", "smi", "async";
> >> + power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
> >> + };
> >> +
> >> sysirq: interrupt-controller@10200100 {
> >> compatible = "mediatek,mt2701-sysirq",
> >> "mediatek,mt6577-sysirq";
> >> @@ -169,6 +180,16 @@
> >> reg = <0 0x10200100 0 0x1c>;
> >> };
> >>
> >> + iommu: mmsys_iommu@10205000 {
> >> + compatible = "mediatek,mt2701-m4u";
> >> + reg = <0 0x10205000 0 0x1000>;
> >> + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
> >> + clocks = <&infracfg CLK_INFRA_M4U>;
> >> + clock-names = "bclk";
> >> + mediatek,larbs = <&larb0 &larb1 &larb2>;
> >> + #iommu-cells = <1>;
> >> + };
> >> +
> >> apmixedsys: syscon@10209000 {
> >> compatible = "mediatek,mt2701-apmixedsys", "syscon";
> >> reg = <0 0x10209000 0 0x1000>;
> >> @@ -234,6 +255,16 @@
> >> status = "disabled";
> >> };
> >>
> >> + larb0: larb@14010000 {
> >> + compatible = "mediatek,mt2701-smi-larb";
> >> + reg = <0 0x14010000 0 0x1000>;
> >> + mediatek,smi = <&smi_common>;
> >> + clocks = <&mmsys CLK_MM_SMI_LARB0>,
> >> + <&mmsys CLK_MM_SMI_LARB0>;
> >> + clock-names = "apb", "smi";
> >> + power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
> >> + };
> >> +
> >> imgsys: syscon@15000000 {
> >> compatible = "mediatek,mt2701-imgsys", "syscon";
> >> reg = <0 0x15000000 0 0x1000>;
> >> @@ -241,6 +272,16 @@
> >> status = "disabled";
> >> };
> >>
> >> + larb2: larb@15001000 {
> >> + compatible = "mediatek,mt2701-smi-larb";
> >> + reg = <0 0x15001000 0 0x1000>;
> >> + mediatek,smi = <&smi_common>;
> >> + clocks = <&imgsys CLK_IMG_SMI_COMM>,
> >> + <&imgsys CLK_IMG_SMI_COMM>;
> >> + clock-names = "apb", "smi";
> >> + power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
> >> + };
> >> +
> >> vdecsys: syscon@16000000 {
> >> compatible = "mediatek,mt2701-vdecsys", "syscon";
> >> reg = <0 0x16000000 0 0x1000>;
> >> @@ -248,6 +289,16 @@
> >> status = "disabled";
> >> };
> >>
> >> + larb1: larb@16010000 {
> >> + compatible = "mediatek,mt2701-smi-larb";
> >> + reg = <0 0x16010000 0 0x1000>;
> >> + mediatek,smi = <&smi_common>;
> >> + clocks = <&vdecsys CLK_VDEC_CKGEN>,
> >> + <&vdecsys CLK_VDEC_LARB>;
> >> + clock-names = "apb", "smi";
> >> + power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
> >> + };
> >> +
> >> hifsys: syscon@1a000000 {
> >> compatible = "mediatek,mt2701-hifsys", "syscon";
> >> reg = <0 0x1a000000 0 0x1000>;
> >>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v4 5/5] ARM: dts: mt2701: add iommu/smi dtsi node for mt2701
2016-07-04 1:32 ` Honghui Zhang
@ 2016-07-04 8:00 ` Matthias Brugger
2017-01-13 14:54 ` Matthias Brugger
0 siblings, 1 reply; 20+ messages in thread
From: Matthias Brugger @ 2016-07-04 8:00 UTC (permalink / raw)
To: Honghui Zhang
Cc: joro, treding, mark.rutland, robh, robin.murphy, p.zabel,
devicetree, pebolle, kendrick.hsu, arnd, srv_heupstream,
catalin.marinas, will.deacon, linux-kernel, tfiga, iommu,
robh+dt, djkurtz, kernel, linux-mediatek, linux-arm-kernel,
l.stach, yingjoe.chen, eddie.huang, youlin.pei, erin.lo
On 04/07/16 03:32, Honghui Zhang wrote:
> On Sun, 2016-07-03 at 21:12 +0200, Matthias Brugger wrote:
>>
>> On 07/03/2016 08:24 AM, Matthias Brugger wrote:
>>>
>>>
>>> On 06/08/2016 11:51 AM, honghui.zhang@mediatek.com wrote:
>>>> From: Honghui Zhang <honghui.zhang@mediatek.com>
>>>>
>>>> Add the dtsi node of iommu and smi for mt2701.
>>>>
>>>> Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
>>>> ---
>>>> arch/arm/boot/dts/mt2701.dtsi | 51
>>>> +++++++++++++++++++++++++++++++++++++++++++
>>>> 1 file changed, 51 insertions(+)
>>>>
>>>
>>> Applied,
>>
>> Please resend the patch including the infracfg and mmsys node.
>>
>
> Hi, Matthias,
>
> Please hold this one.
> This one is based on CCF "arm: dts: mt2701: Add clock controller device
> nodes"[1] and power domain patch "Mediatek MT2701 SCPSYS power domain
> support v7"[2],
> But these two patchset are still being reviewed now.
>
> Do you think it's better that I send this one later after ccf and power
> domain patch got merged? I will send this patch later if it's OK with
> you.
>
Sounds good.
Thanks a lot,
Matthias
> Thanks.
> [1] https://patchwork.kernel.org/patch/9109081
> [2]
> http://lists.infradead.org/pipermail/linux-mediatek/2016-May/005429.html
>
>> Regards,
>> Matthias
>>
>>>
>>> Thanks.
>>>
>>>> diff --git a/arch/arm/boot/dts/mt2701.dtsi
>>>> b/arch/arm/boot/dts/mt2701.dtsi
>>>> index 42d5a37..363de0d 100644
>>>> --- a/arch/arm/boot/dts/mt2701.dtsi
>>>> +++ b/arch/arm/boot/dts/mt2701.dtsi
>>>> @@ -16,6 +16,7 @@
>>>> #include <dt-bindings/power/mt2701-power.h>
>>>> #include <dt-bindings/interrupt-controller/irq.h>
>>>> #include <dt-bindings/interrupt-controller/arm-gic.h>
>>>> +#include <dt-bindings/memory/mt2701-larb-port.h>
>>>> #include "skeleton64.dtsi"
>>>> #include "mt2701-pinfunc.h"
>>>>
>>>> @@ -160,6 +161,16 @@
>>>> clock-names = "system-clk", "rtc-clk";
>>>> };
>>>>
>>>> + smi_common: smi@1000c000 {
>>>> + compatible = "mediatek,mt2701-smi-common";
>>>> + reg = <0 0x1000c000 0 0x1000>;
>>>> + clocks = <&infracfg CLK_INFRA_SMI>,
>>>> + <&mmsys CLK_MM_SMI_COMMON>,
>>>> + <&infracfg CLK_INFRA_SMI>;
>>>> + clock-names = "apb", "smi", "async";
>>>> + power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
>>>> + };
>>>> +
>>>> sysirq: interrupt-controller@10200100 {
>>>> compatible = "mediatek,mt2701-sysirq",
>>>> "mediatek,mt6577-sysirq";
>>>> @@ -169,6 +180,16 @@
>>>> reg = <0 0x10200100 0 0x1c>;
>>>> };
>>>>
>>>> + iommu: mmsys_iommu@10205000 {
>>>> + compatible = "mediatek,mt2701-m4u";
>>>> + reg = <0 0x10205000 0 0x1000>;
>>>> + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
>>>> + clocks = <&infracfg CLK_INFRA_M4U>;
>>>> + clock-names = "bclk";
>>>> + mediatek,larbs = <&larb0 &larb1 &larb2>;
>>>> + #iommu-cells = <1>;
>>>> + };
>>>> +
>>>> apmixedsys: syscon@10209000 {
>>>> compatible = "mediatek,mt2701-apmixedsys", "syscon";
>>>> reg = <0 0x10209000 0 0x1000>;
>>>> @@ -234,6 +255,16 @@
>>>> status = "disabled";
>>>> };
>>>>
>>>> + larb0: larb@14010000 {
>>>> + compatible = "mediatek,mt2701-smi-larb";
>>>> + reg = <0 0x14010000 0 0x1000>;
>>>> + mediatek,smi = <&smi_common>;
>>>> + clocks = <&mmsys CLK_MM_SMI_LARB0>,
>>>> + <&mmsys CLK_MM_SMI_LARB0>;
>>>> + clock-names = "apb", "smi";
>>>> + power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
>>>> + };
>>>> +
>>>> imgsys: syscon@15000000 {
>>>> compatible = "mediatek,mt2701-imgsys", "syscon";
>>>> reg = <0 0x15000000 0 0x1000>;
>>>> @@ -241,6 +272,16 @@
>>>> status = "disabled";
>>>> };
>>>>
>>>> + larb2: larb@15001000 {
>>>> + compatible = "mediatek,mt2701-smi-larb";
>>>> + reg = <0 0x15001000 0 0x1000>;
>>>> + mediatek,smi = <&smi_common>;
>>>> + clocks = <&imgsys CLK_IMG_SMI_COMM>,
>>>> + <&imgsys CLK_IMG_SMI_COMM>;
>>>> + clock-names = "apb", "smi";
>>>> + power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
>>>> + };
>>>> +
>>>> vdecsys: syscon@16000000 {
>>>> compatible = "mediatek,mt2701-vdecsys", "syscon";
>>>> reg = <0 0x16000000 0 0x1000>;
>>>> @@ -248,6 +289,16 @@
>>>> status = "disabled";
>>>> };
>>>>
>>>> + larb1: larb@16010000 {
>>>> + compatible = "mediatek,mt2701-smi-larb";
>>>> + reg = <0 0x16010000 0 0x1000>;
>>>> + mediatek,smi = <&smi_common>;
>>>> + clocks = <&vdecsys CLK_VDEC_CKGEN>,
>>>> + <&vdecsys CLK_VDEC_LARB>;
>>>> + clock-names = "apb", "smi";
>>>> + power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
>>>> + };
>>>> +
>>>> hifsys: syscon@1a000000 {
>>>> compatible = "mediatek,mt2701-hifsys", "syscon";
>>>> reg = <0 0x1a000000 0 0x1000>;
>>>>
>
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v4 5/5] ARM: dts: mt2701: add iommu/smi dtsi node for mt2701
2016-07-04 8:00 ` Matthias Brugger
@ 2017-01-13 14:54 ` Matthias Brugger
2017-01-16 2:48 ` Honghui Zhang
0 siblings, 1 reply; 20+ messages in thread
From: Matthias Brugger @ 2017-01-13 14:54 UTC (permalink / raw)
To: Honghui Zhang
Cc: joro, treding, mark.rutland, robh, robin.murphy, p.zabel,
devicetree, pebolle, kendrick.hsu, arnd, srv_heupstream,
catalin.marinas, will.deacon, linux-kernel, tfiga, iommu,
robh+dt, djkurtz, kernel, linux-mediatek, linux-arm-kernel,
l.stach, yingjoe.chen, eddie.huang, youlin.pei, erin.lo
On 04/07/16 10:00, Matthias Brugger wrote:
>
>
> On 04/07/16 03:32, Honghui Zhang wrote:
>> On Sun, 2016-07-03 at 21:12 +0200, Matthias Brugger wrote:
>>>
>>> On 07/03/2016 08:24 AM, Matthias Brugger wrote:
>>>>
>>>>
>>>> On 06/08/2016 11:51 AM, honghui.zhang@mediatek.com wrote:
>>>>> From: Honghui Zhang <honghui.zhang@mediatek.com>
>>>>>
>>>>> Add the dtsi node of iommu and smi for mt2701.
>>>>>
>>>>> Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
>>>>> ---
>>>>> arch/arm/boot/dts/mt2701.dtsi | 51
>>>>> +++++++++++++++++++++++++++++++++++++++++++
>>>>> 1 file changed, 51 insertions(+)
>>>>>
>>>>
>>>> Applied,
>>>
>>> Please resend the patch including the infracfg and mmsys node.
>>>
>>
>> Hi, Matthias,
>>
>> Please hold this one.
>> This one is based on CCF "arm: dts: mt2701: Add clock controller device
>> nodes"[1] and power domain patch "Mediatek MT2701 SCPSYS power domain
>> support v7"[2],
>> But these two patchset are still being reviewed now.
>>
>> Do you think it's better that I send this one later after ccf and power
>> domain patch got merged? I will send this patch later if it's OK with
>> you.
>>
>
> Sounds good.
Applied now to v4.10-next/dts32
Thanks.
>
> Thanks a lot,
> Matthias
>
>> Thanks.
>> [1] https://patchwork.kernel.org/patch/9109081
>> [2]
>> http://lists.infradead.org/pipermail/linux-mediatek/2016-May/005429.html
>>
>>> Regards,
>>> Matthias
>>>
>>>>
>>>> Thanks.
>>>>
>>>>> diff --git a/arch/arm/boot/dts/mt2701.dtsi
>>>>> b/arch/arm/boot/dts/mt2701.dtsi
>>>>> index 42d5a37..363de0d 100644
>>>>> --- a/arch/arm/boot/dts/mt2701.dtsi
>>>>> +++ b/arch/arm/boot/dts/mt2701.dtsi
>>>>> @@ -16,6 +16,7 @@
>>>>> #include <dt-bindings/power/mt2701-power.h>
>>>>> #include <dt-bindings/interrupt-controller/irq.h>
>>>>> #include <dt-bindings/interrupt-controller/arm-gic.h>
>>>>> +#include <dt-bindings/memory/mt2701-larb-port.h>
>>>>> #include "skeleton64.dtsi"
>>>>> #include "mt2701-pinfunc.h"
>>>>>
>>>>> @@ -160,6 +161,16 @@
>>>>> clock-names = "system-clk", "rtc-clk";
>>>>> };
>>>>>
>>>>> + smi_common: smi@1000c000 {
>>>>> + compatible = "mediatek,mt2701-smi-common";
>>>>> + reg = <0 0x1000c000 0 0x1000>;
>>>>> + clocks = <&infracfg CLK_INFRA_SMI>,
>>>>> + <&mmsys CLK_MM_SMI_COMMON>,
>>>>> + <&infracfg CLK_INFRA_SMI>;
>>>>> + clock-names = "apb", "smi", "async";
>>>>> + power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
>>>>> + };
>>>>> +
>>>>> sysirq: interrupt-controller@10200100 {
>>>>> compatible = "mediatek,mt2701-sysirq",
>>>>> "mediatek,mt6577-sysirq";
>>>>> @@ -169,6 +180,16 @@
>>>>> reg = <0 0x10200100 0 0x1c>;
>>>>> };
>>>>>
>>>>> + iommu: mmsys_iommu@10205000 {
>>>>> + compatible = "mediatek,mt2701-m4u";
>>>>> + reg = <0 0x10205000 0 0x1000>;
>>>>> + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
>>>>> + clocks = <&infracfg CLK_INFRA_M4U>;
>>>>> + clock-names = "bclk";
>>>>> + mediatek,larbs = <&larb0 &larb1 &larb2>;
>>>>> + #iommu-cells = <1>;
>>>>> + };
>>>>> +
>>>>> apmixedsys: syscon@10209000 {
>>>>> compatible = "mediatek,mt2701-apmixedsys", "syscon";
>>>>> reg = <0 0x10209000 0 0x1000>;
>>>>> @@ -234,6 +255,16 @@
>>>>> status = "disabled";
>>>>> };
>>>>>
>>>>> + larb0: larb@14010000 {
>>>>> + compatible = "mediatek,mt2701-smi-larb";
>>>>> + reg = <0 0x14010000 0 0x1000>;
>>>>> + mediatek,smi = <&smi_common>;
>>>>> + clocks = <&mmsys CLK_MM_SMI_LARB0>,
>>>>> + <&mmsys CLK_MM_SMI_LARB0>;
>>>>> + clock-names = "apb", "smi";
>>>>> + power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
>>>>> + };
>>>>> +
>>>>> imgsys: syscon@15000000 {
>>>>> compatible = "mediatek,mt2701-imgsys", "syscon";
>>>>> reg = <0 0x15000000 0 0x1000>;
>>>>> @@ -241,6 +272,16 @@
>>>>> status = "disabled";
>>>>> };
>>>>>
>>>>> + larb2: larb@15001000 {
>>>>> + compatible = "mediatek,mt2701-smi-larb";
>>>>> + reg = <0 0x15001000 0 0x1000>;
>>>>> + mediatek,smi = <&smi_common>;
>>>>> + clocks = <&imgsys CLK_IMG_SMI_COMM>,
>>>>> + <&imgsys CLK_IMG_SMI_COMM>;
>>>>> + clock-names = "apb", "smi";
>>>>> + power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
>>>>> + };
>>>>> +
>>>>> vdecsys: syscon@16000000 {
>>>>> compatible = "mediatek,mt2701-vdecsys", "syscon";
>>>>> reg = <0 0x16000000 0 0x1000>;
>>>>> @@ -248,6 +289,16 @@
>>>>> status = "disabled";
>>>>> };
>>>>>
>>>>> + larb1: larb@16010000 {
>>>>> + compatible = "mediatek,mt2701-smi-larb";
>>>>> + reg = <0 0x16010000 0 0x1000>;
>>>>> + mediatek,smi = <&smi_common>;
>>>>> + clocks = <&vdecsys CLK_VDEC_CKGEN>,
>>>>> + <&vdecsys CLK_VDEC_LARB>;
>>>>> + clock-names = "apb", "smi";
>>>>> + power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
>>>>> + };
>>>>> +
>>>>> hifsys: syscon@1a000000 {
>>>>> compatible = "mediatek,mt2701-hifsys", "syscon";
>>>>> reg = <0 0x1a000000 0 0x1000>;
>>>>>
>>
>>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v4 5/5] ARM: dts: mt2701: add iommu/smi dtsi node for mt2701
2017-01-13 14:54 ` Matthias Brugger
@ 2017-01-16 2:48 ` Honghui Zhang
0 siblings, 0 replies; 20+ messages in thread
From: Honghui Zhang @ 2017-01-16 2:48 UTC (permalink / raw)
To: Matthias Brugger
Cc: joro, treding, mark.rutland, robh, robin.murphy, p.zabel,
devicetree, pebolle, kendrick.hsu, arnd, srv_heupstream,
catalin.marinas, will.deacon, linux-kernel, tfiga, iommu,
robh+dt, djkurtz, kernel, linux-mediatek, linux-arm-kernel,
l.stach, yingjoe.chen, eddie.huang, youlin.pei, erin.lo
On Fri, 2017-01-13 at 15:54 +0100, Matthias Brugger wrote:
>
> On 04/07/16 10:00, Matthias Brugger wrote:
> >
> >
> > On 04/07/16 03:32, Honghui Zhang wrote:
> >> On Sun, 2016-07-03 at 21:12 +0200, Matthias Brugger wrote:
> >>>
> >>> On 07/03/2016 08:24 AM, Matthias Brugger wrote:
> >>>>
> >>>>
> >>>> On 06/08/2016 11:51 AM, honghui.zhang@mediatek.com wrote:
> >>>>> From: Honghui Zhang <honghui.zhang@mediatek.com>
> >>>>>
> >>>>> Add the dtsi node of iommu and smi for mt2701.
> >>>>>
> >>>>> Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
> >>>>> ---
> >>>>> arch/arm/boot/dts/mt2701.dtsi | 51
> >>>>> +++++++++++++++++++++++++++++++++++++++++++
> >>>>> 1 file changed, 51 insertions(+)
> >>>>>
> >>>>
> >>>> Applied,
> >>>
> >>> Please resend the patch including the infracfg and mmsys node.
> >>>
> >>
> >> Hi, Matthias,
> >>
> >> Please hold this one.
> >> This one is based on CCF "arm: dts: mt2701: Add clock controller device
> >> nodes"[1] and power domain patch "Mediatek MT2701 SCPSYS power domain
> >> support v7"[2],
> >> But these two patchset are still being reviewed now.
> >>
> >> Do you think it's better that I send this one later after ccf and power
> >> domain patch got merged? I will send this patch later if it's OK with
> >> you.
> >>
> >
> > Sounds good.
>
> Applied now to v4.10-next/dts32
>
> Thanks.
>
Thanks.
> >
> > Thanks a lot,
> > Matthias
> >
> >> Thanks.
> >> [1] https://patchwork.kernel.org/patch/9109081
> >> [2]
> >> http://lists.infradead.org/pipermail/linux-mediatek/2016-May/005429.html
> >>
^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2017-01-16 2:48 UTC | newest]
Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-06-08 9:50 [PATCH v4 0/5] MT2701 iommu support honghui.zhang
2016-06-08 9:50 ` [PATCH v4 1/5] dt-bindings: mediatek: add descriptions for mediatek mt2701 iommu and smi honghui.zhang
2016-06-08 9:50 ` [PATCH v4 2/5] iommu/mediatek: move the common struct into header file honghui.zhang
2016-06-08 9:50 ` [PATCH v4 3/5] memory/mediatek: add support for mt2701 honghui.zhang
2016-06-08 9:51 ` [PATCH v4 4/5] iommu/mediatek: add support for mtk iommu generation one HW honghui.zhang
2016-06-08 9:51 ` [PATCH v4 5/5] ARM: dts: mt2701: add iommu/smi dtsi node for mt2701 honghui.zhang
2016-06-21 9:41 ` Joerg Roedel
2016-06-21 9:55 ` Honghui Zhang
2016-06-21 9:57 ` Joerg Roedel
2016-06-22 5:45 ` Eddie Huang
2016-06-22 7:45 ` Honghui Zhang
2016-06-22 8:31 ` Joerg Roedel
2016-06-22 8:39 ` Honghui Zhang
2016-06-22 8:58 ` Joerg Roedel
2016-07-03 6:24 ` Matthias Brugger
2016-07-03 19:12 ` Matthias Brugger
2016-07-04 1:32 ` Honghui Zhang
2016-07-04 8:00 ` Matthias Brugger
2017-01-13 14:54 ` Matthias Brugger
2017-01-16 2:48 ` Honghui Zhang
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