From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1423981AbcFMNxg (ORCPT ); Mon, 13 Jun 2016 09:53:36 -0400 Received: from mga11.intel.com ([192.55.52.93]:8412 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1423417AbcFMNxU (ORCPT ); Mon, 13 Jun 2016 09:53:20 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.26,466,1459839600"; d="scan'208";a="1000892217" Message-ID: <1465826071.30123.18.camel@linux.intel.com> Subject: Re: [PATCH v3 2/3] x86/platform/p2sb: New Primary to Sideband bridge support driver for Intel SOC's From: Andy Shevchenko To: Mika Westerberg , Tan Jui Nee Cc: heikki.krogerus@linux.intel.com, tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com, x86@kernel.org, ptyser@xes-inc.com, lee.jones@linaro.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, jonathan.yong@intel.com, ong.hock.yu@intel.com, weifeng.voon@intel.com, wan.ahmad.zainie.wan.mohamad@intel.com Date: Mon, 13 Jun 2016 16:54:31 +0300 In-Reply-To: <20160609140538.GL1791@lahna.fi.intel.com> References: <1465282553-28396-1-git-send-email-jui.nee.tan@intel.com> <1465282553-28396-3-git-send-email-jui.nee.tan@intel.com> <20160609140538.GL1791@lahna.fi.intel.com> Organization: Intel Finland Oy Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.20.3-1 Mime-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 2016-06-09 at 17:05 +0300, Mika Westerberg wrote: > On Tue, Jun 07, 2016 at 02:55:52PM +0800, Tan Jui Nee wrote: > > From: Andy Shevchenko > > > > There is already one and at least one more user coming which > > require an access to Primary to Sideband bridge (P2SB) in order > > to get IO or MMIO bar hidden by BIOS. > > Create a driver to access P2SB for x86 devices. > > > > Signed-off-by: Yong, Jonathan > > Signed-off-by: Andy Shevchenko > > --- > >  arch/x86/Kconfig                 | 14 ++++++ > >  arch/x86/include/asm/p2sb.h      | 27 +++++++++++ > >  arch/x86/platform/intel/Makefile |  1 + > >  arch/x86/platform/intel/p2sb.c   | 99 > > ++++++++++++++++++++++++++++++++++++++++ > >  4 files changed, 141 insertions(+) > >  create mode 100644 arch/x86/include/asm/p2sb.h > >  create mode 100644 arch/x86/platform/intel/p2sb.c > > > > diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig > > index 2dc18605..589045e 100644 > > --- a/arch/x86/Kconfig > > +++ b/arch/x86/Kconfig > > @@ -606,6 +606,20 @@ config IOSF_MBI_DEBUG > >   > >     If you don't require the option or are in doubt, say N. > >   > > +config X86_INTEL_NON_ACPI > > + bool "Enable support non-ACPI Intel platforms" > > + select PINCTRL > > + ---help--- > > +   Select this option to enables MMIO BAR access over the > > P2SB for > > +   non-ACPI Intel SoC platforms. This driver uses the P2SB > > hide/unhide > > +   mechanism cooperatively to pass the PCI BAR address to > > the platform > > +   driver, currently GPIO on the following SoC products. > > +    - Apollo Lake > > Why do we need Kconfig option for this? In one of previous review I was wondering how we could not to build this at all. I don't like this option either. > > I think better is to make P2SB available on CPUs which have one, and > that can be detected runtime. If P2SB is not available then p2sb_bar() > returns -ENODEV. Would work to me, though still the same question: is it possible to avoid building it on even most of Intel platforms, since there, I assume, will be not many users of the module? -- Andy Shevchenko Intel Finland Oy