From: Andrey Smirnov <andrew.smirnov@gmail.com>
To: linux-arm-kernel@lists.infradead.org
Cc: Russell King <linux@arm.linux.org.uk>,
Shawn Guo <shawnguo@kernel.org>,
Sascha Hauer <kernel@pengutronix.de>,
Arnd Bergmann <arnd@arndb.de>,
linux-kernel@vger.kernel.org,
Andrey Smirnov <andrew.smirnov@gmail.com>
Subject: [PATCH v2 1/6] i.MX: system.c: Convert goto to if statement
Date: Tue, 14 Jun 2016 18:29:48 -0700 [thread overview]
Message-ID: <1465954193-5894-2-git-send-email-andrew.smirnov@gmail.com> (raw)
In-Reply-To: <1465954193-5894-1-git-send-email-andrew.smirnov@gmail.com>
Using goto here doesn't bring any advantages and only makes the code
flow less clear. No functional changes.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
arch/arm/mach-imx/system.c | 36 +++++++++++++++++-------------------
1 file changed, 17 insertions(+), 19 deletions(-)
diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c
index 105d1ce..d9f8b0e 100644
--- a/arch/arm/mach-imx/system.c
+++ b/arch/arm/mach-imx/system.c
@@ -106,26 +106,24 @@ void __init imx_init_l2cache(void)
goto out;
}
- if (readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)
- goto skip_if_enabled;
-
- /* Configure the L2 PREFETCH and POWER registers */
- val = readl_relaxed(l2x0_base + L310_PREFETCH_CTRL);
- val |= 0x70800000;
- /*
- * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
- * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
- * But according to ARM PL310 errata: 752271
- * ID: 752271: Double linefill feature can cause data corruption
- * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
- * Workaround: The only workaround to this erratum is to disable the
- * double linefill feature. This is the default behavior.
- */
- if (cpu_is_imx6q())
- val &= ~(1 << 30 | 1 << 23);
- writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL);
+ if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
+ /* Configure the L2 PREFETCH and POWER registers */
+ val = readl_relaxed(l2x0_base + L310_PREFETCH_CTRL);
+ val |= 0x70800000;
+ /*
+ * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
+ * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
+ * But according to ARM PL310 errata: 752271
+ * ID: 752271: Double linefill feature can cause data corruption
+ * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
+ * Workaround: The only workaround to this erratum is to disable the
+ * double linefill feature. This is the default behavior.
+ */
+ if (cpu_is_imx6q())
+ val &= ~(1 << 30 | 1 << 23);
+ writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL);
+ }
-skip_if_enabled:
iounmap(l2x0_base);
of_node_put(np);
--
2.5.5
next prev parent reply other threads:[~2016-06-15 1:30 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-15 1:29 [PATCH v2 0/6] i.MX L2-cache code cleanups and performance tweaks Andrey Smirnov
2016-06-15 1:29 ` Andrey Smirnov [this message]
2016-06-15 1:29 ` [PATCH v2 2/6] i.MX: system.c: Remove redundant errata 752271 code Andrey Smirnov
2016-06-15 1:29 ` [PATCH v2 3/6] i.MX: system.c: Replace magic numbers Andrey Smirnov
2016-06-15 6:18 ` Uwe Kleine-König
2016-06-16 2:00 ` Shawn Guo
2016-06-15 1:29 ` [PATCH v2 4/6] ARM: cache-l2x0: Do not clear bit 23 in prefetch control register Andrey Smirnov
2016-06-15 1:29 ` [PATCH v2 5/6] i.MX: system.c: Tweak prefetch settings for performance Andrey Smirnov
2016-06-15 1:29 ` [PATCH v2 6/6] i.MX: Do not explicitly call l2x0_of_init() Andrey Smirnov
2016-06-15 10:41 ` Arnd Bergmann
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