From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752961AbcFOBaN (ORCPT ); Tue, 14 Jun 2016 21:30:13 -0400 Received: from mail-pa0-f68.google.com ([209.85.220.68]:36657 "EHLO mail-pa0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752474AbcFOBaK (ORCPT ); Tue, 14 Jun 2016 21:30:10 -0400 From: Andrey Smirnov To: linux-arm-kernel@lists.infradead.org Cc: Russell King , Shawn Guo , Sascha Hauer , Arnd Bergmann , linux-kernel@vger.kernel.org, Andrey Smirnov Subject: [PATCH v2 1/6] i.MX: system.c: Convert goto to if statement Date: Tue, 14 Jun 2016 18:29:48 -0700 Message-Id: <1465954193-5894-2-git-send-email-andrew.smirnov@gmail.com> X-Mailer: git-send-email 2.5.5 In-Reply-To: <1465954193-5894-1-git-send-email-andrew.smirnov@gmail.com> References: <1465954193-5894-1-git-send-email-andrew.smirnov@gmail.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Using goto here doesn't bring any advantages and only makes the code flow less clear. No functional changes. Signed-off-by: Andrey Smirnov --- arch/arm/mach-imx/system.c | 36 +++++++++++++++++------------------- 1 file changed, 17 insertions(+), 19 deletions(-) diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c index 105d1ce..d9f8b0e 100644 --- a/arch/arm/mach-imx/system.c +++ b/arch/arm/mach-imx/system.c @@ -106,26 +106,24 @@ void __init imx_init_l2cache(void) goto out; } - if (readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN) - goto skip_if_enabled; - - /* Configure the L2 PREFETCH and POWER registers */ - val = readl_relaxed(l2x0_base + L310_PREFETCH_CTRL); - val |= 0x70800000; - /* - * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0 - * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2 - * But according to ARM PL310 errata: 752271 - * ID: 752271: Double linefill feature can cause data corruption - * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2 - * Workaround: The only workaround to this erratum is to disable the - * double linefill feature. This is the default behavior. - */ - if (cpu_is_imx6q()) - val &= ~(1 << 30 | 1 << 23); - writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL); + if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) { + /* Configure the L2 PREFETCH and POWER registers */ + val = readl_relaxed(l2x0_base + L310_PREFETCH_CTRL); + val |= 0x70800000; + /* + * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0 + * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2 + * But according to ARM PL310 errata: 752271 + * ID: 752271: Double linefill feature can cause data corruption + * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2 + * Workaround: The only workaround to this erratum is to disable the + * double linefill feature. This is the default behavior. + */ + if (cpu_is_imx6q()) + val &= ~(1 << 30 | 1 << 23); + writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL); + } -skip_if_enabled: iounmap(l2x0_base); of_node_put(np); -- 2.5.5