From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932286AbcFOBat (ORCPT ); Tue, 14 Jun 2016 21:30:49 -0400 Received: from mail-pa0-f65.google.com ([209.85.220.65]:34734 "EHLO mail-pa0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752919AbcFOBaN (ORCPT ); Tue, 14 Jun 2016 21:30:13 -0400 From: Andrey Smirnov To: linux-arm-kernel@lists.infradead.org Cc: Russell King , Shawn Guo , Sascha Hauer , Arnd Bergmann , linux-kernel@vger.kernel.org, Andrey Smirnov Subject: [PATCH v2 4/6] ARM: cache-l2x0: Do not clear bit 23 in prefetch control register Date: Tue, 14 Jun 2016 18:29:51 -0700 Message-Id: <1465954193-5894-5-git-send-email-andrew.smirnov@gmail.com> X-Mailer: git-send-email 2.5.5 In-Reply-To: <1465954193-5894-1-git-send-email-andrew.smirnov@gmail.com> References: <1465954193-5894-1-git-send-email-andrew.smirnov@gmail.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org As per L2C-310 TRM[1]: "... You can control this feature using bits 30,27, and 23 of the Prefetch Control Register. Bit 23 and27 are only used if you set bit 30 HIGH..." which means there is no need to clear bit 23 if bit 30 is being cleared. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0246e/CJAJACBJ.html Signed-off-by: Andrey Smirnov --- arch/arm/mm/cache-l2x0.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 30e2012..12c1ba7 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -715,11 +715,8 @@ static void __init l2c310_fixup(void __iomem *base, u32 cache_id, if (revision >= L310_CACHE_ID_RTL_R3P0 && revision < L310_CACHE_ID_RTL_R3P2) { u32 val = l2x0_saved_regs.prefetch_ctrl; - /* I don't think bit23 is required here... but iMX6 does so */ - if (val & (L310_PREFETCH_CTRL_DBL_LINEFILL | - L310_PREFETCH_CTRL_DBL_LINEFILL_INCR)) { - val &= ~(L310_PREFETCH_CTRL_DBL_LINEFILL | - L310_PREFETCH_CTRL_DBL_LINEFILL_INCR); + if (val & L310_PREFETCH_CTRL_DBL_LINEFILL) { + val &= ~L310_PREFETCH_CTRL_DBL_LINEFILL; l2x0_saved_regs.prefetch_ctrl = val; errata[n++] = "752271"; } -- 2.5.5