From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756187AbcFTScc (ORCPT ); Mon, 20 Jun 2016 14:32:32 -0400 Received: from mail-pf0-f178.google.com ([209.85.192.178]:35929 "EHLO mail-pf0-f178.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751996AbcFTScZ (ORCPT ); Mon, 20 Jun 2016 14:32:25 -0400 From: Douglas Anderson To: ulf.hansson@linaro.org, Heiko Stuebner Cc: kishon@ti.com, robh+dt@kernel.org, shawn.lin@rock-chips.com, xzy.xu@rock-chips.com, briannorris@chromium.org, adrian.hunter@intel.com, linux-rockchip@lists.infradead.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, groeck@chromium.org, Douglas Anderson , pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 10/15] Documentation: mmc: sdhci-of-arasan: Add ability to export card clock Date: Mon, 20 Jun 2016 10:56:49 -0700 Message-Id: <1466445414-11974-11-git-send-email-dianders@chromium.org> X-Mailer: git-send-email 2.8.0.rc3.226.g39d4020 In-Reply-To: <1466445414-11974-1-git-send-email-dianders@chromium.org> References: <1466445414-11974-1-git-send-email-dianders@chromium.org> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Some SD/eMMC PHYs (like the PHY from Arasan that is designed to work with arasan,sdhci-5.1) need to know the card clock frequency in order to function properly. Physically in a SoC this clock is exported from the SDHCI IP block to the PHY IP block and the PHY needs to know the speed. Let's export the SDHCI card clock using a standard device tree mechanism so that the PHY can get access to it and query the card clock frequency. Signed-off-by: Douglas Anderson Acked-by: Rob Herring Reviewed-by: Heiko Stuebner --- Changes in v3: - Add collected tags Changes in v2: - Adjust commit message wording (Rob) - Add Rob Herring's Ack. Documentation/devicetree/bindings/mmc/arasan,sdhci.txt | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt index 476604e6ce2a..3404afa9b938 100644 --- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt +++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt @@ -30,6 +30,12 @@ Optional Properties: - arasan,soc-ctl-syscon: A phandle to a syscon device (see ../mfd/syscon.txt) used to access core corecfg registers. Offsets of registers in this syscon are determined based on the main compatible string for the device. + - clock-output-names: If specified, this will be the name of the card clock + which will be exposed by this device. Required if #clock-cells is + specified. + - #clock-cells: If specified this should be the value <0>. With this property + in place we will export a clock representing the Card Clock. This clock + is expected to be consumed by our PHY. You must also specify Example: sdhci@e0100000 { @@ -61,7 +67,9 @@ Example: arasan,soc-ctl-syscon = <&grf>; assigned-clocks = <&cru SCLK_EMMC>; assigned-clock-rates = <200000000>; + clock-output-names = "emmc_cardclock"; phys = <&emmc_phy>; phy-names = "phy_arasan"; + #clock-cells = <0>; status = "disabled"; }; -- 2.8.0.rc3.226.g39d4020