From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932897AbcF3QYO (ORCPT ); Thu, 30 Jun 2016 12:24:14 -0400 Received: from mirror2.csie.ntu.edu.tw ([140.112.30.76]:38278 "EHLO wens.csie.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932654AbcF3QYK (ORCPT ); Thu, 30 Jun 2016 12:24:10 -0400 From: Chen-Yu Tsai To: Lee Jones , Alessandro Zummo , Alexandre Belloni , Rob Herring , Mark Rutland , Maxime Ripard , Michael Turquette , Stephen Boyd Cc: Chen-Yu Tsai , linux-arm-kernel@lists.infradead.org, rtc-linux@googlegroups.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 7/7] ARM: dts: sun9i: Switch to the AC100 RTC clock outputs for osc32k Date: Thu, 30 Jun 2016 23:58:51 +0800 Message-Id: <1467302331-9663-8-git-send-email-wens@csie.org> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1467302331-9663-1-git-send-email-wens@csie.org> References: <1467302331-9663-1-git-send-email-wens@csie.org> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The 32.768 kHz clock inside the A80 SoC is fed from an external source, typically the AC100 RTC module. Make the osc32k placeholder a fixed-factor clock so board dts files can specify its source. Signed-off-by: Chen-Yu Tsai --- Changes since v3: none Changes since v2: none Changes since v1: none --- arch/arm/boot/dts/sun9i-a80-cubieboard4.dts | 5 +++++ arch/arm/boot/dts/sun9i-a80-optimus.dts | 5 +++++ arch/arm/boot/dts/sun9i-a80.dtsi | 9 +++------ 3 files changed, 13 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts index cf2f4b72a841..04b014603659 100644 --- a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts +++ b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts @@ -103,6 +103,11 @@ allwinner,drive = ; }; +&osc32k { + /* osc32k input is from AC100 */ + clocks = <&ac100_rtc 0>; +}; + &pio { led_pins_cubieboard4: led-pins@0 { allwinner,pins = "PH6", "PH17"; diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts b/arch/arm/boot/dts/sun9i-a80-optimus.dts index e35c06c162a7..fd874ded890e 100644 --- a/arch/arm/boot/dts/sun9i-a80-optimus.dts +++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts @@ -152,6 +152,11 @@ status = "okay"; }; +&osc32k { + /* osc32k input is from AC100 */ + clocks = <&ac100_rtc 0>; +}; + &pio { led_pins_optimus: led-pins@0 { allwinner,pins = "PH0", "PH1"; diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi index f68b3242b33a..dd11115ec087 100644 --- a/arch/arm/boot/dts/sun9i-a80.dtsi +++ b/arch/arm/boot/dts/sun9i-a80.dtsi @@ -148,15 +148,12 @@ /* * The 32k clock is from an external source, normally the - * AC100 codec/RTC chip. This clock is by default enabled - * and clocked at 32768 Hz, from the oscillator connected - * to the AC100. It is configurable, but no such driver or - * bindings exist yet. + * AC100 codec/RTC chip. This serves as a placeholder for + * board dts files to specify the source. */ osc32k: osc32k_clk { #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; + compatible = "fixed-factor-clock"; clock-output-names = "osc32k"; }; -- 2.8.1