From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752232AbcGOCUy (ORCPT ); Thu, 14 Jul 2016 22:20:54 -0400 Received: from mail-pf0-f171.google.com ([209.85.192.171]:34810 "EHLO mail-pf0-f171.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751771AbcGOCUv (ORCPT ); Thu, 14 Jul 2016 22:20:51 -0400 From: Andrey Pronin To: Jarkko Sakkinen Cc: Peter Huewe , Marcel Selhorst , Jason Gunthorpe , tpmdd-devel@lists.sourceforge.net, linux-kernel@vger.kernel.org, Andrey Pronin , groeck@chromium.org, smbarber@chromium.org, dianders@chromium.org, devicetree@vger.kernel.org, =?UTF-8?q?=C2=A0=C2=A0=C2=A0Rob=20Herring?= , =?UTF-8?q?=C2=A0=C2=A0=C2=A0Pawel=20Moll?= , =?UTF-8?q?=C2=A0=C2=A0=C2=A0Mark=20Rutland?= , =?UTF-8?q?=C2=A0=C2=A0=C2=A0Ian=20Campbell?= , =?UTF-8?q?=C2=A0=C2=A0=C2=A0Kumar=20Gala?= Subject: [PATCH 1/2] tpm: devicetree: document properties for cr50 Date: Thu, 14 Jul 2016 19:20:17 -0700 Message-Id: <1468549218-19215-2-git-send-email-apronin@chromium.org> X-Mailer: git-send-email 2.8.0.rc3.226.g39d4020 In-Reply-To: <1468549218-19215-1-git-send-email-apronin@chromium.org> References: <1468549218-19215-1-git-send-email-apronin@chromium.org> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add TPM2.0-compatible interface to Cr50. Document its properties in devicetree. Signed-off-by: Andrey Pronin --- .../devicetree/bindings/security/tpm/cr50_spi.txt | 30 ++++++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 Documentation/devicetree/bindings/security/tpm/cr50_spi.txt diff --git a/Documentation/devicetree/bindings/security/tpm/cr50_spi.txt b/Documentation/devicetree/bindings/security/tpm/cr50_spi.txt new file mode 100644 index 0000000..1b05e51 --- /dev/null +++ b/Documentation/devicetree/bindings/security/tpm/cr50_spi.txt @@ -0,0 +1,30 @@ +* Cr50 Chip on SPI. + +TCG PTP FIFO Compliant Interface to Cr50 on SPI bus. + +Required properties: +- compatible: Should be "google,cr50_spi". +- spi-max-frequency: Maximum SPI frequency. + +Optional properties: +- access-delay-msec: Required delay between subsequent transactions on SPI. +- sleep-delay-msec: Time after the last SPI activity, after which the chip + may go to sleep. +- wake-start-delay-msec: Time after initiating wake up before the chip is + ready to accept commands over SPI. + +Example: + +&spi0 { + status = "okay"; + + cr50@0 { + compatible = "google,cr50_spi"; + reg = <0>; + spi-max-frequency = <800000>; + + access-delay-msec = <2>; + sleep-delay-msec = <1000>; + wake-start-delay-msec = <60>; + }; +}; -- 2.6.6