From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754914AbcG1EZj (ORCPT ); Thu, 28 Jul 2016 00:25:39 -0400 Received: from mail-pa0-f51.google.com ([209.85.220.51]:35420 "EHLO mail-pa0-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750740AbcG1EZU (ORCPT ); Thu, 28 Jul 2016 00:25:20 -0400 From: Andrey Pronin To: Jarkko Sakkinen Cc: Peter Huewe , Marcel Selhorst , Jason Gunthorpe , tpmdd-devel@lists.sourceforge.net, linux-kernel@vger.kernel.org, Christophe Ricard , dtor@chromium.org, smbarber@chromium.org, dianders@chromium.org, Andrey Pronin , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , devicetree@vger.kernel.org Subject: [PATCH v3 1/2] tpm: devicetree: document properties for cr50 Date: Wed, 27 Jul 2016 21:25:16 -0700 Message-Id: <1469679917-120240-2-git-send-email-apronin@chromium.org> X-Mailer: git-send-email 2.8.0.rc3.226.g39d4020 In-Reply-To: <1469679917-120240-1-git-send-email-apronin@chromium.org> References: <1468549218-19215-1-git-send-email-apronin@chromium.org> <1469679917-120240-1-git-send-email-apronin@chromium.org> In-Reply-To: <1468549218-19215-1-git-send-email-apronin@chromium.org> References: <1468549218-19215-1-git-send-email-apronin@chromium.org> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add TPM2.0 PTP FIFO compatible SPI interface for chips with Cr50 firmware. Signed-off-by: Andrey Pronin --- .../devicetree/bindings/security/tpm/cr50_spi.txt | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 Documentation/devicetree/bindings/security/tpm/cr50_spi.txt diff --git a/Documentation/devicetree/bindings/security/tpm/cr50_spi.txt b/Documentation/devicetree/bindings/security/tpm/cr50_spi.txt new file mode 100644 index 0000000..2fbebd3 --- /dev/null +++ b/Documentation/devicetree/bindings/security/tpm/cr50_spi.txt @@ -0,0 +1,21 @@ +* H1 Secure Microcontroller with Cr50 Firmware on SPI Bus. + +H1 Secure Microcontroller running Cr50 firmware provides several +functions, including TPM-like functionality. It communicates over +SPI using the FIFO protocol described in the PTP Spec, section 6. + +Required properties: +- compatible: Should be "google,cr50". +- spi-max-frequency: Maximum SPI frequency. + +Example: + +&spi0 { + status = "okay"; + + cr50@0 { + compatible = "google,cr50"; + reg = <0>; + spi-max-frequency = <800000>; + }; +}; -- 2.6.6