From: Andrey Smirnov <andrew.smirnov@gmail.com>
To: linux-arm-kernel@lists.infradead.org
Cc: Andrey Smirnov <andrew.smirnov@gmail.com>,
Russell King <linux@arm.linux.org.uk>,
Arnd Bergmann <arnd@arndb.de>,
linux-kernel@vger.kernel.org
Subject: [RESEND PATCH 1/2] ARM: cache-l2x0.c: Replace magic numbers
Date: Thu, 28 Jul 2016 17:48:41 -0700 [thread overview]
Message-ID: <1469753322-11407-1-git-send-email-andrew.smirnov@gmail.com> (raw)
Replace magic numbers used for L310 Prefetch Control Register
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
arch/arm/mm/cache-l2x0.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 9f9d542..30e2012 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -716,8 +716,10 @@ static void __init l2c310_fixup(void __iomem *base, u32 cache_id,
revision < L310_CACHE_ID_RTL_R3P2) {
u32 val = l2x0_saved_regs.prefetch_ctrl;
/* I don't think bit23 is required here... but iMX6 does so */
- if (val & (BIT(30) | BIT(23))) {
- val &= ~(BIT(30) | BIT(23));
+ if (val & (L310_PREFETCH_CTRL_DBL_LINEFILL |
+ L310_PREFETCH_CTRL_DBL_LINEFILL_INCR)) {
+ val &= ~(L310_PREFETCH_CTRL_DBL_LINEFILL |
+ L310_PREFETCH_CTRL_DBL_LINEFILL_INCR);
l2x0_saved_regs.prefetch_ctrl = val;
errata[n++] = "752271";
}
--
2.5.5
next reply other threads:[~2016-07-29 0:49 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-07-29 0:48 Andrey Smirnov [this message]
2016-07-29 0:48 ` [RESEND PATCH 2/2] ARM: cache-l2x0.c: Do not clear bit 23 in prefetch control register Andrey Smirnov
2016-07-29 8:30 ` [RESEND PATCH 1/2] ARM: cache-l2x0.c: Replace magic numbers Arnd Bergmann
-- strict thread matches above, loose matches on Subject: below --
2016-06-28 4:34 Andrey Smirnov
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