From: York Sun <york.sun@nxp.com>
To: <linux-edac@vger.kernel.org>
Cc: <morbidrsa@gmail.com>, <oss@buserror.net>, <stuart.yoder@nxp.com>,
<bp@alien8.de>, York Sun <york.sun@nxp.com>,
Doug Thompson <dougthompson@xmission.com>, <mchehab@kernel.org>,
<linux-kernel@vger.kernel.org>
Subject: [Patch v4 5/9] driver/edac/fsl_ddr: Add DDR types
Date: Tue, 9 Aug 2016 14:55:42 -0700 [thread overview]
Message-ID: <1470779760-16483-6-git-send-email-york.sun@nxp.com> (raw)
In-Reply-To: <1470779760-16483-1-git-send-email-york.sun@nxp.com>
The compatible DDR controllers may support DDR, DDR2, DDR3, DDR4. An
individual controller doesn't support all of them. EDAC driver reads
the controller to determine which mode is running.
Signed-off-by: York Sun <york.sun@nxp.com>
---
Change log
v4: Drop DSC_SDTYPE_DDR* macros, use naked numbers as suggested
Update commit message.
v3: no change
v2: no change
drivers/edac/fsl_ddr_edac.c | 24 ++++++++++++++++--------
drivers/edac/fsl_ddr_edac.h | 4 ----
2 files changed, 16 insertions(+), 12 deletions(-)
diff --git a/drivers/edac/fsl_ddr_edac.c b/drivers/edac/fsl_ddr_edac.c
index 2675833..46b00e1 100644
--- a/drivers/edac/fsl_ddr_edac.c
+++ b/drivers/edac/fsl_ddr_edac.c
@@ -371,30 +371,36 @@ static void fsl_ddr_init_csrows(struct mem_ctl_info *mci)
sdtype = sdram_ctl & DSC_SDTYPE_MASK;
if (sdram_ctl & DSC_RD_EN) {
switch (sdtype) {
- case DSC_SDTYPE_DDR:
+ case 0x02000000:
mtype = MEM_RDDR;
break;
- case DSC_SDTYPE_DDR2:
+ case 0x03000000:
mtype = MEM_RDDR2;
break;
- case DSC_SDTYPE_DDR3:
+ case 0x07000000:
mtype = MEM_RDDR3;
break;
+ case 0x05000000:
+ mtype = MEM_RDDR4;
+ break;
default:
mtype = MEM_UNKNOWN;
break;
}
} else {
switch (sdtype) {
- case DSC_SDTYPE_DDR:
+ case 0x02000000:
mtype = MEM_DDR;
break;
- case DSC_SDTYPE_DDR2:
+ case 0x03000000:
mtype = MEM_DDR2;
break;
- case DSC_SDTYPE_DDR3:
+ case 0x07000000:
mtype = MEM_DDR3;
break;
+ case 0x05000000:
+ mtype = MEM_DDR4;
+ break;
default:
mtype = MEM_UNKNOWN;
break;
@@ -499,8 +505,10 @@ int fsl_mc_err_probe(struct platform_device *op)
}
edac_dbg(3, "init mci\n");
- mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_RDDR2 |
- MEM_FLAG_DDR | MEM_FLAG_DDR2;
+ mci->mtype_cap = MEM_FLAG_DDR | MEM_FLAG_RDDR |
+ MEM_FLAG_DDR2 | MEM_FLAG_RDDR2 |
+ MEM_FLAG_DDR3 | MEM_FLAG_RDDR3 |
+ MEM_FLAG_DDR4 | MEM_FLAG_RDDR4;
mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
mci->edac_cap = EDAC_FLAG_SECDED;
mci->mod_name = EDAC_MOD_STR;
diff --git a/drivers/edac/fsl_ddr_edac.h b/drivers/edac/fsl_ddr_edac.h
index 1eccc62..4ccee29 100644
--- a/drivers/edac/fsl_ddr_edac.h
+++ b/drivers/edac/fsl_ddr_edac.h
@@ -50,10 +50,6 @@
#define DSC_DBW_64 0x00000000
#define DSC_SDTYPE_MASK 0x07000000
-
-#define DSC_SDTYPE_DDR 0x02000000
-#define DSC_SDTYPE_DDR2 0x03000000
-#define DSC_SDTYPE_DDR3 0x07000000
#define DSC_X32_EN 0x00000020
/* Err_Int_En */
--
2.7.4
next prev parent reply other threads:[~2016-08-09 21:57 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <1470779760-16483-1-git-send-email-york.sun@nxp.com>
2016-08-09 21:55 ` [Patch v4 1/9] driver/edac/mpc85xx_edac: Drop setting/clearing RFXE bit in HID1 York Sun
2016-08-09 21:55 ` [Patch v4 2/9] driver/edac/mpc85xx_edac: Replace printk with proper pr_* format York Sun
2016-08-09 21:55 ` [Patch v4 3/9] driver/edac/fsl-ddr: Separate FSL DDR EDAC driver from MPC85xx York Sun
2016-08-11 13:36 ` Borislav Petkov
2016-08-11 15:05 ` york sun
2016-08-11 20:13 ` york sun
2016-08-09 21:55 ` [Patch v4 4/9] driver/edac/fsl_ddr: Rename macros and names York Sun
2016-08-09 21:55 ` York Sun [this message]
2016-08-09 21:55 ` [Patch v4 6/9] driver/edac/fsl_ddr: Add support of little endian York Sun
2016-08-10 22:26 ` Rob Herring
2016-08-12 7:41 ` Borislav Petkov
2016-08-09 21:55 ` [Patch v4 7/9] driver/edac/fsl_ddr: Fix kernel warning when module is removed York Sun
2016-08-09 21:55 ` [Patch v4 8/9] driver/edac/layerscape_edac: Add Layerscape EDAC support York Sun
2016-08-12 9:12 ` Borislav Petkov
2016-08-23 16:46 ` york sun
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